CN112350699A - High voltage fet circuit and system - Google Patents

Abstract

The present application relates to a high withstand voltage field effect transistor circuit and system, the high withstand voltage field effect transistor circuit separates a first field effect transistor assembly and a second field effect transistor assembly by providing the first field effect transistor assembly and the second field effect transistor assembly which are connected in parallel with each other. When the voltage-withstanding type field effect transistor is used, only the first field effect transistor component is required to be turned off through the control circuit, and the second field effect transistor component is turned on, namely, the voltage-withstanding capability of negative electricity which is multiplied by the original single field effect transistor is borne; the voltage-withstanding capability of positive electricity which is multiplied by the original single field effect tube can be borne only by switching on the first field effect tube component and switching off the second field effect tube component through the control circuit. The technical problem that once the existing field effect tube in the prior art is fixed, the existing field effect tube can only bear rated working voltage and cannot bear voltage with higher strength is solved by adopting the first field effect tube assembly and the second field effect tube assembly to be separated, and the technical effect of greatly improving the pressure resistance of the field effect tube is achieved.

Description

High voltage fet circuit and system

Technical Field

The present application relates to the field of driving technologies, and in particular, to a high voltage-withstanding fet circuit and system.

Background

The field effect transistor is a metal-oxide-semiconductor (semiconductor) field effect transistor, which is also called mos transistor, and is widely used as an ideal analog switch device in other driving circuit systems such as power supply systems. At present, due to the limitation of the production process, the voltage withstanding degree of the fet is limited, for example, when the fet is required to withstand a maximum voltage of 40V in the actual use process, it is required to provide an output system of the fet of ± 40V, obviously, the voltage withstanding of ± 40V is required to be 80V, but the fet of 40V cannot withstand a voltage of 80V at present. Therefore, once fixed, the field effect transistor can only bear the rated working voltage and cannot bear the voltage with higher intensity.

Disclosure of Invention

Therefore, it is necessary to provide a high voltage resistant fet circuit and system to solve the technical problem that once the fet is fixed, it can only withstand the rated operating voltage and cannot withstand the higher voltage.

A high withstand voltage fet circuit, comprising:

the first field effect tube assembly comprises at least two first field effect tubes which are connected in series, and the first end of the first field effect tube assembly is used for connecting the anode of an external power supply;

the second field effect tube assembly comprises at least two second field effect tubes which are connected in series, the first end of the second field effect tube assembly is used for being connected with the negative electrode of the external power supply, the second end of the second field effect tube assembly is electrically connected with the second end of the first field effect tube assembly, and the second end of the second field effect tube assembly and the common end of the first field effect tube assembly are used for being connected with electric equipment;

the control circuit is respectively and electrically connected with the control ends of the first field effect tube assembly and the second field effect tube assembly and is used for controlling the on-off of the first field effect tube assembly and the first field effect tube assembly.

In one embodiment, the method further comprises the following steps:

and a first end of the first grounding switch is connected between two adjacent first field effect transistors, and a second end of the first grounding switch is used for grounding.

In one embodiment, the number of the first field effect transistors is even.

In one embodiment, the number of the first field effect transistors on both sides of the first grounding switch is equal.

In one embodiment, the method further comprises the following steps:

and a first end of the second grounding switch is connected between two adjacent second field effect transistors, and a second end of the second grounding switch is used for grounding.

In one embodiment, the number of the second field effect transistors is even.

In one embodiment, the number of the second fets on both sides of the second grounding switch is equal.

In one embodiment, the number of the first field effect transistor and the second field effect transistor is two.

In one embodiment, the first field effect transistor is P-type and the second field effect transistor is N-type, or the first field effect transistor is N-type and the second field effect transistor is P-type.

A high voltage tolerant field effect transistor system comprising:

the high withstand voltage fet circuit as described above;

and the anode of the external power supply is electrically connected with the first end of the first field effect tube component, and the cathode of the external power supply is electrically connected with the first end of the first field effect tube component.

The embodiment of the application provides a high-voltage field effect transistor circuit, which is characterized in that a first field effect transistor component and a second field effect transistor component which are connected in parallel are arranged to separate the first field effect transistor component from the second field effect transistor component. When the voltage-withstanding type field effect transistor is used, the first field effect transistor assembly is turned off only through the control circuit, and the second field effect transistor assembly is turned on, namely, the voltage-withstanding capability of negative electricity which is multiplied by the original single field effect transistor is borne; similarly, the voltage withstanding capability of the positive electricity which is multiplied by the original single field effect tube can be borne only by turning on the first field effect tube component and turning off the second field effect tube component through the control circuit. Therefore, the embodiment of the application provides a high-voltage-resistance field-effect tube circuit, and the technical problems that the existing field-effect tube in the prior art can only bear rated working voltage and cannot bear voltage with higher strength once being fixed are solved by adopting a mode that the first field-effect tube component and the second field-effect tube component are separated, so that the technical effect of greatly improving the voltage resistance of the field-effect tube is achieved.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments or the conventional technologies of the present application, the drawings used in the descriptions of the embodiments or the conventional technologies will be briefly introduced below, it is obvious that the drawings in the following descriptions are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a high voltage fet circuit and an application scenario according to an embodiment of the present application;

fig. 2 is a schematic diagram of a high voltage fet circuit according to an embodiment of the present application;

fig. 3 is a schematic diagram of a high voltage fet circuit according to an embodiment of the present application;

fig. 4 is a schematic structural diagram of a high voltage fet system according to an embodiment of the present application.

Description of reference numerals:

10. a high withstand voltage field effect transistor circuit; 100. a first field effect tube assembly; 110. a first field effect transistor; 200. a second field effect transistor assembly; 210. a second field effect transistor; 300. a control circuit; 400. a first ground switch; 500. a second ground switch; 20. a high withstand voltage field effect transistor system; 21. and an external power supply.

Detailed Description

In order to make the purpose, technical solution and advantages of the present application more apparent, a high voltage fet circuit and a system according to the present application are described in further detail below by way of embodiments and with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.

The numbering of the components as such, e.g., "first", "second", etc., is used herein only to distinguish the objects as described, and does not have any sequential or technical meaning. The term "connected" and "coupled" when used in this application, unless otherwise indicated, includes both direct and indirect connections (couplings). In the description of the present application, it is to be understood that the terms "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", and the like, indicate orientations or positional relationships based on those shown in the drawings, and are used only for convenience in describing the present application and for simplicity in description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed in a particular orientation, and be operated, and thus, are not to be considered as limiting the present application.

In this application, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may be directly contacting the first and second features or indirectly contacting the first and second features through intervening media. Also, a first feature "on," "over," and "above" a second feature may be directly or diagonally above the second feature, or may simply indicate that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature may be directly under or obliquely under the first feature, or may simply mean that the first feature is at a lesser elevation than the second feature.

The embodiment of the application provides a high-voltage-resistance field-effect transistor circuit 10 which can be applied to any circuit or control system and used as a driving device or a control device. The following embodiment is a detailed description of the high withstand voltage fet circuit 10.

Referring to fig. 1 and fig. 2 together, an embodiment of the present application provides a high voltage fet circuit 10, including: a first fet assembly 100 and a second fet assembly 200.

The first fet assembly 100 includes at least two first fets 110 connected in series, a first end of the first fet assembly 100 is used to connect to the positive electrode of the external power source 21, and when in use, the first end of the first fet assembly 100 is electrically connected to the positive electrode of the external power source 21 to bear a positive voltage during operation. The plurality of first field effect transistors 110 connected in series means that the drain electrode of the first field effect transistor 110 is electrically connected to the source electrode of the adjacent first field effect transistor 110, so that the first field effect transistors 110 are sequentially electrically connected to realize the series connection of the plurality of first field effect transistors 110. It should be noted that the gate of each of the first fets 110 is electrically connected to the control circuit 300, and the control circuit 300 controls on/off of each of the first fets 110, thereby controlling on/off of the first fet assembly 100. The number of the first field effect transistors 110 in the first field effect transistor assembly 100 may be two, three, four, or the like, and the first field effect transistors 110 may be N-type field effect transistors or P-type field effect transistors, and in this embodiment, no limitation is made on the number, the type, or the like of the first field effect transistors 110, and the first field effect transistors may be specifically selected according to actual situations. However, it should be noted that the voltage endurance of the high voltage mosfet circuit 10 is continuously improved with the increase of the number of the first fets 110, for example, if the number of the first fets 110 is two, the voltage endurance of the high voltage mosfet circuit 10 is improved by two times, and if the number of the first fets 110 is three, the voltage endurance of the high voltage mosfet circuit 10 is improved by three times.

The second fet assembly 200 includes at least two second fets 210 connected in series, a first end of the second fet assembly 200 is used to connect a negative electrode of the external power source 21, a second end of the second fet assembly 200 is electrically connected to a second end of the first fet assembly 100, and a second end of the second fet assembly 200 and a common end of the first fet assembly 100 are used to connect an electric device. In use, the first terminal of the second fet assembly 200 is electrically connected to the negative terminal of the external power supply 21 to assume a negative voltage during operation. The plurality of second fets 210 are connected in series, that is, the drain of each second fet 210 is electrically connected to the source of the adjacent second fet 210, so that the second fets 210 are sequentially electrically connected to each other, thereby realizing the series connection between the plurality of second fets 210. It should be noted that the gate of each second fet 210 is electrically connected to the control circuit 300, and the control circuit 300 controls on/off of each second fet 210, thereby controlling on/off of the second fet 200. The number of the second field effect transistors 210 in the second field effect transistor assembly 200 may be two, three, four, or the like, the second field effect transistors 210 may be N-type field effect transistors, or P-type field effect transistors, and the number, the type, or the like of the second field effect transistors 210 are not limited in any way in this embodiment, and may be specifically selected according to actual situations. However, it should be noted that the voltage endurance of the high voltage mosfet circuit 10 is continuously improved with the number of the second mosfets 210, for example, if the number of the second mosfets 210 is two, the voltage endurance of the high voltage mosfet circuit 10 is improved by two times, and if the number of the second mosfets 210 is three, the voltage endurance of the high voltage mosfet circuit 10 is improved by three times.

The control circuit 300 is electrically connected to the control terminals of the first fet device 100 and the second fet device 200, that is, to the gates of each of the first fet 110 and the second fet 210, respectively, so as to control the on/off of the first fet device 100 and the first fet device 100. When in use, the control circuit 300 generates a control signal, and transmits the control signal to the gate of each of the first fet 110 and the second fet 210, and controls the on/off of each of the first fet 110 and the second fet 210 through the control signal. The control signal can be a level signal, the N-type field effect transistor is switched on when a high level signal is input, and is switched off when a low level signal is input, and the P-type field effect transistor is switched off when a high level signal is input, and is switched on when a low level signal is input. For example, when the first fet 110 and the second fet 210 are both N-type fets or both P-type fets, the control circuit 300 may simultaneously output two level signals, i.e., a high level signal and a low level signal, which are respectively input to the gates of the first fet 110 and the second fet 210, and control one of the first fet 100 and the second fet 200 to be turned on and the other to be turned off. When one of the first fet 110 and the second fet 210 is an N-type fet and the other is a P-type fet, the control circuit 300 can simultaneously control the states of the first fet 110 and the second fet 210 by outputting a level signal, and maintain one of the first fet 100 and the second fet 200 in an on state and one in an off state. For example, when the first fet 110 is an N-type fet, the second fet 210 is a P-type fet, and the control signal is a high level signal, the first fet 100 is turned on, and the second fet 200 is turned off, so that the high voltage fet circuit 10 can bear a positive voltage impact. Conversely, when the control signal is a low level signal, the high voltage fet circuit 10 can take on the impact of a negative voltage.

The working principle of the high-voltage fet circuit 10 provided in this embodiment is as follows:

the high voltage fet circuit 10 provided in this embodiment includes the first fet device 100, the second fet device 200, and the control circuit 300, where the first fet device 100 includes m first fets 110 connected in series with each other, and the second fet device 200 includes m second fets 210 connected in series with each other, where m is a positive integer greater than or equal to 2. For example, each of the first fets 110 and each of the second fets 210 has a voltage withstanding capability of n V. In use, a powered device is electrically connected to a common terminal of the first fet assembly 100 and the second fet assembly 200. When the control circuit 300 controls the first fet device 100 to be turned on and the second fet device 200 to be turned off, the voltage across the first fet device 100 is mn V, and the voltage across the second fet device 200 is mn V when the second fet device 200 is connected in parallel with the first fet device 100. However, the first fet device 100 is connected to the positive terminal of the external power source 21, and the second fet device 200 is connected to the negative terminal of the external power source 21, so that the voltage across the first fet device is + mn V, and the voltage across the second fet device 200 is-mn V. Meanwhile, the control circuit 300 controls the first fet device 100 to be turned off, and the second fet device 200 to be turned on, so that the voltage across the first fet device 100 is + mn V. Therefore, the high voltage withstanding fet circuit 10 provided in this embodiment can bear an external pressure of ± mn V, and the voltage withstanding capability is greatly improved and is far greater than the voltage withstanding capability of ± n V of the original single fet.

The present embodiment provides a high withstand voltage fet circuit 10, which separates the first fet device 100 and the second fet device 200 by disposing the first fet device 100 and the second fet device 200 in parallel with each other. When in use, the control circuit 300 is only required to turn off the first fet assembly 100 and turn on the second fet assembly 200, that is, the negative voltage withstand capability of the original single fet is multiplied; similarly, the control circuit 300 only needs to turn on the first fet device 100 and turn off the second fet device 200, so that the voltage withstanding capability of the original single fet can be multiplied by the positive voltage. Therefore, in this embodiment, by providing the high voltage resistant fet circuit 10, the technical problem that the fet can only bear its rated operating voltage and cannot bear a voltage with higher strength once being fixed in the prior art is solved by separating the first fet component 100 and the second fet component 200, so as to achieve the technical effect of greatly improving the voltage resistance of the fet.

Referring to fig. 3, in an embodiment, the high voltage fet circuit 10 further includes: a first grounding switch 400.

A first end of the first grounding switch 400 is connected between two adjacent first fets 110, and a second end of the first grounding switch 400 is used for grounding. The first fets 110 in the first fet devices 100 are all the same, but in actual production, even if the internal resistances of the same batch and the same model are inconsistent, the voltages borne by each first fet 110 are inconsistent, and the first fet 110 with a higher pressure across the terminals is prone to be broken down. In the high voltage resistant fet circuit 10 of this embodiment, one first grounding switch 400 is added between two adjacent first fets 110, and when the first grounding switch 400 is turned off, the common terminal of two adjacent first fets 110 is grounded, and the voltage is 0, so that the voltages at two ends of each first fet 110 are equal, and the problem that an individual first fet 110 is broken down due to an excessive voltage is avoided. In this embodiment, the first grounding switch 400 may be an electronic switch, such as a mos transistor, and a control end of the electronic switch is in signal connection with the control circuit 300, so that the control circuit 300 can control the on/off of the first grounding switch 400. The first grounding switch 400 can also be a common mechanical switch, and can be operated manually without an additional controller, so that the grounding switch is simple and convenient. In this embodiment, the number, specific types, and the like of the first grounding switches 400 are not limited at all, and may be specifically set according to actual conditions, and only the function of grounding needs to be satisfied.

In an embodiment, the number of the first fets 110 may be even, and the number of the first fets 110 on both sides of the first grounding switch 400 is equal, so as to facilitate the balance of the voltages across the first grounding switch 400, thereby improving the safety and stability of the high-voltage mosfet circuit 10 of this embodiment. For example, when the number of the first fets 110 is two, the increase of the withstand voltage capability of the first fets 110 can be doubled, and the application is more extensive.

In one embodiment, the high voltage fet circuit 10 further includes: and a second grounding switch 500.

A first end of the second grounding switch 500 is connected between two adjacent second fets 210, and a second end of the second grounding switch 500 is used for grounding. The second fets 210 in the second fets 200 are all the same, but in actual production, even if the internal resistances of the same batch and the same model are also easily inconsistent, the voltages borne by each second fet 210 are easily inconsistent, and thus the second fets 210 with higher voltages at both ends are easily broken down. In the high voltage resistant fet circuit 10 of this embodiment, one second grounding switch 500 is added between two adjacent second fets 210, and when the second grounding switch 500 is turned off, the common terminal of two adjacent second fets 210 is grounded, and the voltage is 0, so that the voltages at two ends of each second fet 210 are equal, and the problem that an individual second fet 210 is broken down due to an excessive voltage is avoided. In this embodiment, the second grounding switch 500 may be an electronic switch, such as a mos transistor, and a control end of the electronic switch is in signal connection with the control circuit 300, so that the on/off of the second grounding switch 500 can be controlled by the control circuit 300. The second grounding switch 500 can also be a common mechanical switch, and can be operated manually without an additional controller, so that the grounding switch is simple and convenient. In this embodiment, the number, specific types, and the like of the second grounding switches 500 are not limited at all, and may be specifically set according to actual conditions, and only the function of grounding needs to be satisfied.

In an embodiment, the number of the second fets 210 may be even, and the number of the second fets 210 on both sides of the second ground switch 500 is equal, so as to facilitate the balance of the voltages across the second ground switch 500, thereby improving the safety and stability of the high-voltage mosfet circuit 10 of this embodiment. For example, when the number of the second fets 210 is two, the increase of the voltage endurance capacity of the second slave fet can be doubled, and the application is wider.

Referring to fig. 4, an embodiment of the present application provides a high voltage fet system 20, comprising: a high voltage fet circuit 10 and an external power supply 21.

The beneficial effects of the high voltage fet circuit 10 have been described in detail in the above embodiments, and are not described herein again.

The anode of the external power source 21 is electrically connected to the first end of the first fet assembly 100, the cathode of the external power source 21 is electrically connected to the first end of the first fet assembly 100, and the middle of the external power source 21 may be grounded, so that the anode and the cathode of the external power source 21 output positive and negative voltages having the same value, for example, the anode outputs +14V voltage and the cathode outputs-14V voltage. The external power source 21 is any direct current, such as a lithium battery, a lead-acid battery, etc., and the present embodiment is not particularly limited to the external power source 21, and may be specifically selected according to actual situations.

The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the claims. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims (10)

1. A high withstand voltage fet circuit, comprising:

the first field effect tube assembly comprises at least two first field effect tubes which are connected in series, and the first end of the first field effect tube assembly is used for connecting the anode of an external power supply;

the second field effect tube assembly comprises at least two second field effect tubes which are connected in series, the first end of the second field effect tube assembly is used for being connected with the negative electrode of the external power supply, the second end of the second field effect tube assembly is electrically connected with the second end of the first field effect tube assembly, and the second end of the second field effect tube assembly and the common end of the first field effect tube assembly are used for being connected with electric equipment;

the control circuit is respectively and electrically connected with the control ends of the first field effect tube assembly and the second field effect tube assembly and is used for controlling the on-off of the first field effect tube assembly and the first field effect tube assembly.

2. The high withstand voltage fet circuit according to claim 1, further comprising:

and a first end of the first grounding switch is connected between two adjacent first field effect transistors, and a second end of the first grounding switch is used for grounding.

3. The high voltage fet circuit of claim 2, wherein the number of first fets is even.

4. The high voltage fet circuit of claim 3, wherein the number of first fets on either side of the first ground switch is equal.

5. The high withstand voltage fet circuit according to claim 1, further comprising:

and a first end of the second grounding switch is connected between two adjacent second field effect transistors, and a second end of the second grounding switch is used for grounding.

6. The high voltage fet circuit of claim 5, wherein the number of second fets is even.

7. The high voltage fet circuit of claim 6, wherein the number of second fets on either side of the second ground switch is equal.

8. The high withstand voltage fet circuit according to claim 1, wherein the number of the first fets and the number of the second fets are two.

9. The high voltage fet circuit of claim 1, wherein the first fet is P-type and the second fet is N-type, or wherein the first fet is N-type and the second fet is P-type.

10. A high voltage tolerant field effect transistor system, comprising:

the high withstand voltage field effect transistor circuit according to any one of claims 1 to 8;

and the anode of the external power supply is electrically connected with the first end of the first field effect tube component, and the cathode of the external power supply is electrically connected with the first end of the first field effect tube component.

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