JP2008034406A - Switching semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reliably improve intermodulation distortion by reducing off capacity and suppressing nonlinearity in capacity reliably, in a switch semiconductor integrated circuit device where a plurality of FETs are connected in series. <P>SOLUTION: In a switching circuit in a stack configuration where a plurality of FETs are connected in series and allowable input power is increased, an electrode to which a substrate bias voltage is applied is arranged opposite to a source electrode S and/or a drain electrode D connected mutually in this configuration, Vgs between the gate and source in off-state is increased stably and fixedly for making off operation reliable in a source at least in partial stacked FETs, thus reducing off the off capacity and suppressing nonlinearly in capacity characteristics. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a switch semiconductor integrated circuit device suitable for use in, for example, a radio frequency (RF) antenna switch of a portable communication device.

FIG. 1A shows a basic circuit configuration of a minimum unit of an integrated circuit that constitutes an RF switch (SW) circuit by a field effect transistor (FET) used for an RF front end unit.
This switch circuit has a series FET between port 1 (Port 1) and port 2 (Port 2) that are turned on and off, and a shunt FET is inserted between the line of this series FET and the ground. When Port 1 and Port 2 are on, the equivalent circuit is a CR circuit as shown in FIG.
When the switch is turned on, the gate voltage Vc1 of the shunt FET is turned off, and the gate voltage Vc2 of the series FET is turned on, thereby turning on between Port1 and Port2. At this time, the shunt FET needs to have a low off-capacitance in order to avoid a high-frequency flow.

On the other hand, when the switch is turned off, the series FET is turned off, the shunt FET is turned on, and a high frequency signal leaking to the series FET is drawn to the ground by the shunt FET, and high isolation is performed.
The loss in this switch circuit is expressed as the sum of direct current (DC) resistance loss and alternating current (AC) capacity loss. Therefore, from the viewpoint of this loss, it is important to reduce the on-resistance of the series FET and to reduce the off-capacitance of the shunt FET.

  A circuit that can apply a bias to the connection middle point where multiple stages of FETs are connected in series so that the off state of the shunt FET can be maintained even when a large signal is input, or a circuit that connects the source and drain via a resistor Has been proposed (see Patent Documents 1 and 2).

On the other hand, not only insertion loss and isolation characteristics but also distortion characteristics have become important as systems change from 2nd generation to 3rd generation mobile phones.
In a system that selects transmitted and received signals by a duplexer, such as a W-CDMA system adopted in third-generation mobile phones, if a non-linear SW device is used, an interference wave and a transmitted wave that exist in the atmosphere are used. Are mixed to generate intermodulation distortion (IMD), which causes a problem of entering the reception path.
For example, it is assumed that the transmission wave (f _TX ) is 1.95 GHz and the reception wave (f _RX ) is 2.14 GHz. The duplexer passes only these two frequencies. Assume that a 190 MHz interference wave (f _block ) enters the SW from the antenna and a 1.95 GHz transmission wave (f _TX ) enters the SW (switch) from the transmission path. If the SW device is non-linear, frequency mixing occurs due to the non-linearity, and a second order IMD of f _TX + f _block = 1.95 GHz + 190 MHz = 2.14 GHz is generated.
Since the created frequency is the same frequency as the received wave, it is an IMD (Mutual Distortion) problem that it passes through the duplexer, enters the reception path, and becomes noise.
In addition, harmonics are generated by the non-linearity of the SW, and the problem of the harmonic distortion is listed as one of the problems of the second generation mobile phone system.

  In order to solve these distortion problems, it can be understood from the simulation results regarding the capacitance depending on the voltage and the capacitance not depending on the voltage that it is effective to suppress the non-linearity of the off capacitance of the Shunt FET. Therefore, the non-linearity of the off-capacitance of the Shunt FET is considered as one of the factors that cause the IMD and the harmonics.

Conventionally, to reduce the off-capacitance of the switch circuit described above, the off-capacitance can be reduced by reducing the ohmic electrode width, reducing the wiring capacitance, or optimizing the semiconductor structure of the FET formation part, that is, the epitaxy structure. There has been a contrivance to reduce this.
However, it is still insufficient to stably and satisfactorily improve the off-capacitance linearity.
JP 2000-277703 A JP 2004-320439 A

  In the Japanese Patent Application No. 2005-008551, the present applicant previously applied a positive voltage to the element isolation region of the semiconductor substrate and applied a positive voltage to the periphery of the field effect transistor, so that A semiconductor device has been proposed in which the effect of depleting a layer is enhanced, thereby reducing the off-capacitance and the intermodulation distortion.

  The present invention is a switch semiconductor integrated circuit device having a stack configuration in which a plurality of field effect transistors are connected in series in order to increase the allowable input power, and the off-capacitance can be reliably reduced. It is an object of the present invention to provide a switch semiconductor integrated circuit device in which the above-described intermodulation distortion can be more reliably improved by suppressing the nonlinearity of the capacitance.

  A switch semiconductor integrated circuit device according to the present invention is a semiconductor device in which a plurality of field effect transistors separated by an isolation region are connected in series on a semiconductor substrate, and at least some of the field effects connected in series to each other A surface bias electrode in contact with the surface of the isolation region is arranged so as to be able to apply a bias to the substrate so as to face the source electrode or the drain electrode of the transistor.

  In the above-described configuration, the surface bias electrode in contact with the surface of the isolation region is arranged to face the source electrodes of all the field effect transistors connected in series with each other.

  In the above-described configuration, the surface bias electrode in contact with the surface of the isolation region is arranged to face the drain electrodes of all the field effect transistors connected in series with each other.

  As described above, the present invention is a switch circuit having a stack configuration in which a plurality of FETs are connected in series to increase the allowable input power, and in this configuration, a source electrode and / or a drain electrode connected to each other On the other hand, since the electrodes to which the substrate bias is applied are arranged so as to face each other, the gate-source voltage Vgs in at least some of the FETs connected in a stack can be stably increased. In this way, by increasing Vgs, it is possible to suppress fluctuation of the capacity due to input power.

  The switch semiconductor integrated circuit device according to the present invention is characterized in that the substrate surface bias electrode is arranged in parallel to the gate electrode related to the source electrode and the drain electrode facing the substrate surface bias electrode.

Further, the present invention is characterized in that the opposing length of the substrate surface bias electrode to the source electrode and the drain electrode is selected to be longer than the opposing length of the source electrode and the drain electrode to the gate electrode. To do.
Further, the present invention is characterized in that the isolation region has a required distributed resistance by introducing impurities.

  Further, according to the present invention, the substrate surface bias electrode disposed to face the source electrode and the drain electrode is contacted with a contact region formed by selectively introducing impurities on the surface of the isolation region. It is characterized by.

  Further, the present invention is characterized in that the field effect transistor is a junction gate field effect transistor, a Schottky gate field effect transistor, or an insulated gate field effect transistor.

In the switch semiconductor integrated circuit device according to the present invention, a surface capable of applying a bias to the substrate opposite to the source electrode or drain electrode of at least a part of a plurality of field effect transistors (FETs) connected in series. Since the bias electrode is arranged on the surface of the isolation region, when a positive voltage is applied to the substrate surface bias electrode, the distributed resistance due to the isolation region is connected to the series-connected source / drain connection opposite to the substrate surface bias electrode. A positive voltage is applied via.
Here, assuming that a negative voltage of an off-voltage is applied to the gates of the plurality of FETs, a gate-source voltage (Vgs) is applied by a positive predetermined voltage applied to the source-drain connection portion. ) Is large, that is, the potential difference is large. Therefore, the channel immediately under the gate is completely depleted, so that the off-capacitance can be surely reduced.
Further, even when a large signal is input, it is possible to suppress the capacitance from fluctuating due to the voltage. That is, the linearity of the capacity is also increased. Therefore, the capacity loss can be reduced by reducing the off-capacitance, and the occurrence of IMD and harmonic distortion can be suppressed by improving the linearity of the capacity.

  When the above-mentioned predetermined substrate bias voltage is applied to all the source / drain connection portions of the FETs connected in series, the Vgs of all the stack FETs connected in series become large, and some FETs Since the off-capacitance can be further reduced and the linearity of the capacity is improved, it is possible to surely cut off the high frequency and prevent the occurrence of IMD and harmonic distortion.

An embodiment of a switch semiconductor integrated circuit device according to the present invention will be described. In these embodiment examples, four FETs (FET1 to FET4) are connected in series. Needless to say, the present invention is not limited to this example.
[First Embodiment]
The first embodiment will be described with reference to Examples 1 to 6.
(Example 1)
FIG. 2A is a schematic plan view of the main part of the switch semiconductor integrated circuit device, and FIG. 2B is an equivalent circuit diagram thereof.
3A and 3B are schematic cross-sectional views on the aa line and the bb line in FIG. 2A.
In this embodiment, each of the FET1 to FET4 is provided with two active regions 3 separated by an isolation region 2, and one FET element is disposed in each active region 3. .
And the gate electrode G which crosses each active region 3 is formed so that the stack direction of these FET1-FET4 may be followed.
In each of the FET1 to FET4, these gate electrodes G are continuously formed in a zigzag pattern with respect to each FET element by the gate electrode itself or wiring, and are connected to a common gate electrode terminal 4G.
In each active region 3, a source electrode S and a drain electrode D are formed facing each other in parallel with the gate electrode G interposed therebetween.

The isolation region 2 is a semiconductor layer having a required specific resistance by implanting a required impurity such as boron ions (B +) into the semiconductor substrate 1.
A substrate surface bias electrode 5 is disposed on the isolation region 2. The substrate surface bias electrode 5 has electrode portions 5a extending in parallel with the extending direction of the gate electrode G so as to face the drain electrodes D positioned between the active regions 3 and on the outermost left and right sides in FIG. Further, the substrate surface bias electrode 5 is connected to one end of these electrode portions 5a, and extends around the stack portion of the FET, a cross electrode portion 5b extending in a direction crossing the electrode portion 5a between the arrangement portions of the FET1 to FET4. The outer peripheral electrode portion 5c is disposed and connected to a terminal 4sub to which a substrate surface bias voltage is applied.
As shown in FIG. 3A, at least the electrode portion 5a of the substrate surface bias electrode 5 forms a p-type contact region 7 on the surface of the isolation region 2 by, for example, Zn diffusion, and the substrate surface bias electrode 5 is formed on this surface. The electrode portion 5a is contacted.

  In this embodiment, a source electrode S and a drain electrode D are formed on both sides of the gate electrode G arranged across the two active regions 3 of the four-stage FET1 to FET4 on both sides of the gate electrode G. Oppositely and parallel to each other, they are arranged in a comb shape. In this case, each source electrode S is disposed at a position on the side facing the electrode portion 5 a of the substrate surface bias electrode 5 in each active region 3.

Although not shown, the comb-like drain electrode D of the first stage FET 1 and the comb-like source electrode S of the final stage FET 4 have a drain connection wiring layer 6D and a source connection wiring layer connected to the drain terminal and the source terminal, respectively. Connected to 6S.
Further, the source electrode S of each FET1 to FET3 is connected to the drain electrode D of each next stage FET2 to FET4 by an intermediate wiring layer 9 formed between each stage. These intermediate wiring layers 9 are arranged between the FET1 to FET4 along the direction crossing the comb-like source electrode S and drain electrode D and the gate electrode G therebetween.
As shown in FIG. 3B, the intermediate wiring layer 9 is disposed on the intersecting electrode portion 5b of the bias electrode 5 disposed between the FET1 to FET4 via an insulating layer 8 made of, for example, SiN.

In the switch semiconductor integrated circuit device according to this embodiment, the electrode surface 5a of the substrate surface bias electrode 5 is arranged to face the entire source electrode S and drain electrode D.
Therefore, according to the switch semiconductor integrated circuit device having this configuration, as shown in FIG. 2B, the connection portions of the source electrode S and the drain electrode D of all the FET1 to FET4 are isolated from the positive substrate bias electrode terminal 4sub. A positive bias is applied via the distributed resistance of the modulation region 2. That is, it is set as a positive constant potential.

As described above, in this embodiment, since a constant positive voltage is applied to the connection portion of the source and drain in all the FETs 1 to 4 connected in series, all the FETs 1 to 4 are stably turned off. Made. In this OFF operation, each channel is pinched off by applying a negative voltage to the gate electrodes of FET1 to FET4, but the negative polarity of the negative gate voltage is applied to the source of each FET1 to FET4. Therefore, the potential difference between the gate and the source becomes large, and the voltage Vgs between them becomes large. That is, it deepens.
For this reason, channel depletion at the time of off is performed well, pinch-off is performed well, off-capacitance is reduced, and high-frequency cutoff at the time of off can be reliably performed. Since this phenomenon is performed for all FET1 to FET4, an extremely reliable off operation and reduction of off capacitance are achieved as the switch circuit.

Next, details of the switch semiconductor integrated circuit device having this configuration will be described together with a manufacturing method.
The FET in this embodiment is a case where it is constituted by a HEMT (High Electron Mobility Transistor) having a hetero structure.
FIG. 4 is a schematic cross-sectional view of the semiconductor substrate 1 constituting the switch semiconductor integrated circuit device having the HEMT.
The semiconductor substrate 1 includes, for example, a multi-buffer layer 102 formed by stacking layers of AlGaAs and GaAs on a substrate 101 formed of semi-insulating GaAs, an electron supply layer 103 formed of n ⁺ -AlGaAs, a spacer layer 104 formed of i-AlGaAs, i-InGaAs cap layer 109 by the channel layer 105, i-AlGaAs by spacer layer ^106, n + barrier layer ¹⁰⁸ by electron supply layer 107, i-AlGaAs by -AlGaAs, n + -GaAs, which are successively epitaxially grown by.

The semiconductor substrate 1 formed by epitaxially growing the respective semiconductor layers in this manner forms the isolation 2 that separates the active regions 3 constituting the FET1 to FET4 described with reference to FIGS. 2 and 3 by, for example, boron ion implantation. Is done.
Then, a contact region 7 by Zn diffusion is formed under the formation portion of the substrate bias electrode 5 in the isolation region 2.
Then, the substrate surface bias electrode 5 and the substrate surface bias electrode terminal 4sub are formed, the gate electrode G is formed, the source electrode S and the drain electrode D are formed, and the drain and source connection wiring layers 6D and 6S are formed.
The substrate surface bias electrode 5 is formed of, for example, a metal laminated film in which Ti, Pt, and Au are sequentially formed from the lower layer on the contact region 7.
The source electrode S and the drain electrode D can be formed by sequentially stacking and alloying AuGe, Ni, and Au layers from the lower layer in order to make contact with the channel layer 105.

  Wiring layers such as the drain connection wiring layer 6D, the intermediate wiring layer 9, and the source connection wiring layer 6S connected to the source electrode S in the final stage can be formed by forming and patterning a metal layer.

(Example 2)
5A and 5B are a schematic plan view and an equivalent circuit diagram of the switch semiconductor integrated circuit device according to this embodiment. In FIG. 5, parts corresponding to those in FIG.
In this example, with respect to all FET1 to FET4, drain electrodes D are arranged in the form of three comb teeth in the active region 3 on both sides of the electrode portion 5a of the substrate surface bias electrode 5, and two comb teeth are interposed therebetween. An FET element configuration in which the source electrode S is arranged via the gate electrode G is formed.

In this configuration, the drain electrodes D of the FET1 to FET4 are arranged opposite to each other on both sides of the electrode portion 5a of the substrate surface bias electrode 5 arranged between the active regions 3 (referred to as a DDDD pattern).
In this example, each drain electrode D adjacent to each electrode portion 5a of the second to fourth stage FET2 to FET4, that is, the drain electrode D to which the voltage Vsub is applied is respectively connected to the previous stage FET1 to FET3. The source electrode S is connected via the intermediate wiring layer 9.
Further, in FIG. 5A of each of the FET1 to FET4, the electrode portion 5a is disposed so as to face the electrode of the rightmost FET element, in this example, the drain D.
Therefore, in the configuration, as shown in FIG. 5B, a predetermined substrate bias voltage Vsub is applied to the connection portions of all the FETs 1 to 4 and the drain of the first-stage FET 1, and the drain electrode D of the FET 1 A positive voltage Vsub is also applied to.
Even in this case, as described in the first embodiment, the predetermined positive voltage Vsub is applied to the mutual connection portions of the sources and drains between all the FETs 1 to 4, so that reliable off operation and off capacitance can be achieved. Can be reduced.

(Example 3)
FIGS. 6A and 6B are a schematic plan view and an equivalent circuit diagram of the switch semiconductor integrated circuit device according to this embodiment. 6, parts corresponding to those in FIGS. 2 and 5 are denoted by the same reference numerals, and redundant description is omitted.
Also in this example, each of the FETs 1 to 4 has two active regions 3, and a plurality of gate portions are arranged in each active region 3.
In this case, with respect to all FET1 to FET4, the source electrode S is arranged in three comb teeth in each of the active regions 3 on both sides of the electrode portion 5a of the substrate surface bias electrode 5, and two comb teeth are interposed therebetween. Each drain electrode D is arranged via a gate electrode G.
And in this structure, when it is set as the pattern (referred to as SSSS pattern) in which the source electrodes S of the FET1 to FET4 are arranged opposite to each other on both sides of the electrode portion 5a of the substrate surface bias electrode 5 disposed between the active regions 3 It is.
Also in this example, the source electrodes S to which the positive voltage Vsub adjacent to the electrode portions 5a of all the FETs 1 to 4 are applied are respectively connected to the drain electrodes D of the FETs 2 to 4 of the next stage through the intermediate wiring layer 9. In this configuration, the voltage Vsub is also applied to the source electrode S of the final stage FET 4.
As described above, in this embodiment, as shown in FIG. 6B, a predetermined positive voltage Vsub is applied to the mutual connection portion of FET1 to FET4 and the source of the final stage FET4. As described above, all the FETs 1 to 4 can be reliably turned off, and the off-capacitance can be reduced.

Example 4
7A and 7B are a schematic plan view and an equivalent circuit diagram of the switch semiconductor integrated circuit device according to this embodiment. 7, parts corresponding to those in FIGS. 2, 5, and 6 are denoted by the same reference numerals, and redundant description is omitted.
In this example, only the FET 1 has the configuration of the third embodiment shown in FIG. 6, and the FETs 2 to 4 have the configuration of the second embodiment of FIG. That is, with respect to FET1, the source electrode S is disposed adjacent to both sides of the electrode portion 5a of the substrate surface bias electrode 5, and in the FET2 to FET4, the drain electrode D is disposed adjacent to both sides of the electrode portion 5a ( (Referred to as an SDDD pattern), and a predetermined fixed voltage is applied to them.
That is, also in this case, a fixed voltage is applied to at least one of the source and drain electrodes connected to each other of the FET1 to FET4 via the intermediate wiring layer 9. Therefore, as shown in FIG. 7B, a predetermined positive voltage Vsub is applied to the connection portions of the drain electrodes D and the source electrodes S of all FET1 to FET4. As a result, reliable off operation and reduction of off capacity can be achieved.

(Example 5)
8A and 8B are a schematic plan view and an equivalent circuit diagram of the switch semiconductor integrated circuit device according to this embodiment. 8, parts corresponding to those in FIGS. 2 and 5 to 7 are denoted by the same reference numerals, and redundant description is omitted.
In this example, the first and second stage FETs 1 and 2 take the form of the example 3 shown in FIG. 6, and the third and fourth stage FETs 3 and 4 have the example shown in FIG. This is a case where the pattern (SSDD) in the form of 2 is taken.

In this case, the source electrode S is disposed adjacent to both sides of the electrode portion 5a of the substrate surface bias electrode 5 in the FET1 and FET2, and the drain electrode is adjacent to both sides of the electrode portion 5a in the FET3 and FET4. D is arranged.
In this example, the source electrode S of FET1 and FET2 to which a predetermined positive voltage Vsub is applied adjacent to the electrode portion 5a is connected to the drain electrode D of the next stage via the intermediate wiring layer 9, respectively. The drain electrode D to which a predetermined positive voltage Vsub is applied adjacent to the electrode portion 5a of the FET 4 is connected to the source electrode S of the preceding FET 3 through the intermediate wiring layer 9.
Therefore, in this case as well, as shown in the equivalent circuit of FIG. 8B, the positive predetermined substrate bias voltage Vsub is applied to the mutual connection portions of all the FETs 1 to 4, which is similarly reliable. The off operation and the off capacity can be reduced.

(Example 6)
FIGS. 9A and 9B are a schematic plan view and an equivalent circuit diagram of the switch semiconductor integrated circuit device according to this embodiment. 9, parts corresponding to those in FIG. 2 and FIG. 5 to FIG.
In this example, the first to third stage FET1 to FET3 take the form of the embodiment 3 shown in FIG. 6, and the final stage FET4 has the pattern of the embodiment 2 shown in FIG. (Referred to as SSSD pattern).

Therefore, in this case, the source electrodes S in the FET1 to FET3 are disposed adjacent to both sides of the electrode portion 5a of the substrate surface bias electrode 5, and in the FET4, the drain electrode D is adjacent to both sides of the electrode portion 5a. Are arranged.
In this case, the source electrode S of the FET1 to FET3 adjacent to the electrode portion 5a and to which a predetermined positive voltage Vsub is applied passes through the intermediate wiring layer 9 to the drain electrode D of the next stage FET2 to FET4, respectively. Connected.
Therefore, in this case, as shown in the equivalent circuit of FIG. 9B, a predetermined substrate bias voltage Vsub is applied to the mutual connection portions of all the FETs 1 to 4, and the same as described in the first embodiment. In addition, reliable off operation and reduction of off-capacitance can be achieved.

  In the first embodiment described above, a predetermined positive voltage Vsub is applied to all the series-connected portions of FET1 to FET4. In this case, the most reliable off operation and off capacitance can be reduced. It is done.

FIG. 10 shows the off-capacitance Coff-drain voltage Vd characteristics using the gate voltage Vg in the FET as a parameter. The source is grounded. As is apparent from this, as the gate voltage Vg becomes deeper, the potential difference between the gate and the source becomes larger, and the potential difference Vgs between them (here, Vgs = | Vg | because the source is grounded) becomes larger. As a result, the off-capacitance Coff is reduced, and at the same time, non-linearity is suppressed and high linearity is exhibited. Here, the linearity of the capacity will be described. Assuming that the linearity of the capacitance is the Coff slope (ΔCoff / ΔVd) of the drain voltage Vd = −1 to + 1V, a small ΔCoff / ΔVd is defined as a high linearity of the off capacitance. At this time, ΔCoff / ΔVd becomes smaller as Vg becomes deeper. In other words, the off-capacitance linearity increases as Vg becomes deeper.
Therefore, as described above, by adopting a configuration in which a positive voltage is applied to the connection portion of each FET in which a plurality of FETs are connected in series, the potential difference between the gate and the source becomes large, and the potential difference between them becomes larger. It can be seen that an increase in Vgs can reduce off-capacitance and improve non-linearity.
In addition, when applied to the antenna switch circuit of the present invention in which the linearity with respect to the drain voltage is thus increased, the generation of intermodulation distortion IMD and harmonics can be improved.

  In the first embodiment described above, the predetermined voltage Vsub is applied to all the series connection portions of the stacked FETs. However, in the second embodiment, some connection portions are provided. In this configuration, a predetermined voltage Vsub is applied, and this is less effective than the first embodiment, but can be improved as compared with the prior art.

[Second Embodiment]
(Example 7)
FIGS. 11A and 11B are a schematic plan view and an equivalent circuit diagram of the switch semiconductor integrated circuit device according to this embodiment. 11, parts corresponding to those in FIG. 2 and FIGS.
This example also has a configuration in which the electrode portions 5a of the substrate surface bias electrode 5 are disposed between the two active regions 3 of the first to fourth stage FETs 1 to 4, respectively. The stage 1 and stage 3 FET 1 and FET 3 have the same configuration as the pattern of each stage in FIG. 6 (Embodiment 3) described above, and the second stage and fourth stage FET 2 and FET 4 in FIG. A pattern (referred to as an SDSD pattern) configuration is used as a configuration similar to the pattern of each stage in Example 2).
However, in this example, the source and drain connected to each other between the FETs 2 and 3 in the second and third stages are not adjacent to the electrode portion 5a.
Therefore, as shown in the circuit of FIG. 11B, the predetermined voltage Vsub is not applied to the mutual connection portion of the FET2 and the FET3.

(Example 8)
12A and 12B are a schematic plan view and an equivalent circuit diagram of the switch semiconductor integrated circuit device according to this embodiment. 12, parts corresponding to those in FIGS. 2, 5 to 9 and 11 are denoted by the same reference numerals, and redundant description is omitted.
Also in this example, the electrode portion 5a of the substrate surface bias electrode 5 is arranged between the active regions 3 of the first to fourth stage FET1 to FET4.
However, in this example, the first stage, the second stage, and the fourth stage FET1, FET2, and FET4 have the same configuration as the pattern of each stage in FIG. The FET 3 has an arrangement (referred to as an SDSD pattern) having a pattern similar to the pattern of each stage in FIG. 5 (Example 2) described above.
In this example, the source electrode S and the drain electrode D connected between the third stage and the fourth stage FET 3 and FET 4 are not adjacent to the electrode portion 5a.
Therefore, as shown in the circuit of FIG. 12B, the predetermined voltage Vsub is not applied to the connection portion of the FET3 and FET4.

Example 9
FIGS. 13A and 13B are a schematic plan view and an equivalent circuit diagram of the switch semiconductor integrated circuit device according to this embodiment. 12, parts corresponding to those in FIG. 2, FIG. 5 to FIG. 9, and FIG. 11 to FIG.
Also in this example, the electrode portion 5a of the substrate surface bias electrode 5 is arranged between the active regions 3 of the first to fourth stage FET1 to FET4.
However, in this example, the first-stage and fourth-stage FETs 1 and 4 have the same configuration as the pattern of each stage in FIG. 6 (Example 3) described above, and the second-stage and third-stage FETs 2 and The FET 3 has an arrangement (referred to as an SDDS pattern) having a pattern similar to the pattern of each stage in FIG. 5 (Example 2) described above.
In this example, the source electrode S and the drain electrode D connected between the third stage and the fourth stage FET 3 and FET 4 are not adjacent to the electrode portion 5a.
Therefore, as shown in the circuit of FIG. 12B, the predetermined voltage Vsub is not applied to the connection portion of the FET3 and FET4.

(Example 10)
14A and 14B are a schematic plan view and an equivalent circuit diagram of the switch semiconductor integrated circuit device according to this embodiment. 14, parts corresponding to those in FIG. 2, FIG. 5 to FIG. 9 and FIG. 11 to FIG.
Also in this example, the electrode portion 5a of the substrate surface bias electrode 5 is arranged between the active regions 3 of the first to fourth stage FET1 to FET4.
However, in this example, the first-stage and fourth-stage FETs 1 and 4 have the same configuration as the pattern of each stage in FIG. 5 (Example 2) described above, and the second-stage and third-stage FETs 2 and The FET 3 has an arrangement (referred to as a DSSD pattern) having a pattern similar to the pattern of each stage in FIG. 6 (Example 3) described above.
In this example, the source electrode S and the drain electrode D connected to each other between the first stage and the second stage FET1 and FET2 are not adjacent to the electrode portion 5a.
Therefore, in this embodiment, as shown in the circuit of FIG. 14B, the predetermined voltage Vsub is not applied to the connection part of the FET1 and FET2.

(Example 11)
FIGS. 15A and 15B are a schematic plan view and an equivalent circuit diagram of a switch semiconductor integrated circuit device according to this embodiment. 15, parts corresponding to those in FIG. 2, FIG. 5 to FIG. 9 and FIG. 11 to FIG.
Also in this example, the electrode portion 5a of the substrate surface bias electrode 5 is arranged between the active regions 3 of the first to fourth stage FET1 to FET4.
However, in this example, the first stage, the third stage, and the fourth stage FET1, FET3, and FET4 have the same configuration as the pattern of each stage in FIG. The FET 2 has an arrangement (referred to as a DSDD pattern) having a pattern similar to the pattern of each stage in FIG. 6 (Example 3) described above.
In this example, the source electrode S and the drain electrode D connected to each other between the first stage and the second stage FET1 and FET2 are not adjacent to the electrode portion 5a.
Therefore, in this embodiment, as shown in the circuit of FIG. 15B, the predetermined voltage Vsub is not applied to the connection part of the FET1 and FET2.

  As in the above-described second embodiment, even when a predetermined positive voltage Vsub is applied only between some stages of FETs connected in series, the FET of this stage is surely turned off. As a result, the off-capacitance can be reduced.

The actual experimental results of the stack structure according to each of the embodiments described above are shown in FIGS. In this case, the gate voltage Vg = −2V and Vsub = + 1V.
FIG. 16 is a curve showing the relationship between the drain voltage and the off-capacitance, in which each example according to the first embodiment is indicated by black plot points, and the example according to the second embodiment is indicated by white plot points. It was.
According to this, when the positive predetermined voltage Vsub is applied to the mutual connection portions of all FET1 to FET4 as in the first embodiment, the positive predetermined voltage Vsub is applied to some of the connection portions. Compared to the case of the second embodiment (the form in which the intermediate portion is not biased) with the above configuration, the off-capacitance is reduced and the linearity tends to be high. For example, when the linearity is defined as the Coff slope (ΔCoff / ΔVd) of the drain voltage Vd = −1 to + 1V, a small ΔCoff / ΔVd is defined as a high off-capacitance linearity. At this time, in the first embodiment, ΔCoff / ΔVd is smaller than that in the second embodiment. In other words, the linearity of the off capacitance is higher in the first embodiment than in the second embodiment.

In FIG. 17, it can be seen that ΔCoff / ΔVd is smaller in the pattern of the first embodiment than in the pattern of the second embodiment. That is, it can be seen that the pattern of the first embodiment has a higher capacitance linearity than the pattern of the second embodiment.
Based on this result, looking at the IMDs of the first and second exemplary embodiments in FIG. 18, the first embodiment has a lower IMD than the second embodiment, particularly a third-order IMD. You can see that

As described above, according to the configuration of the present invention, the off-capacitance is reduced by the configuration in which the gate voltage at the off time is deepened as a configuration in which a positive voltage is applied to the connection portion of each FET in which a plurality of FETs are connected in series. It can be seen that non-linearity is improved.
By reducing the off-capacitance as described above, AC-like capacity loss can be reduced, and the linearity of the off-capacitance can be increased to apply the intermodulation distortion (IMD) and the antenna switch circuit described at the beginning. Generation of harmonic distortion can be improved.

  As described above, the present invention constitutes a switch for increasing the input capacitance as a stack structure by connecting a plurality of FETs in series, that is, a circuit that is turned on / off. Furthermore, it is desirable to apply to a case where the shunt FET in the antenna switch circuit has a stack configuration. However, it can also be applied to the above-described series FET. Further, a stacked series FET and a shunt FET can be formed on the same semiconductor substrate 1 according to the configuration of the present invention to constitute an integrated circuit of, for example, an antenna switch.

In the above-described example, the field effect transistor constituting the switch circuit is a HEMT. However, for example, a junction gate field effect transistor, a Schottky gate field effect transistor, an insulated gate field effect transistor, or the like may be used. it can.
Further, the present invention is not limited to the above-described example. For example, the substrate surface bias electrode is contacted without forming the contact region 7, and various modifications and changes are made in the present invention described in the claims. Needless to say, you can.

(A) And (b) is a circuit diagram which shows the structure of switch SW basic circuit, and an equivalent circuit schematic. (A) And (b) is the schematic plan view of the principal part which shows the arrangement pattern of an example of the switch semiconductor integrated circuit device by this invention, and its equivalent circuit schematic. (A) And (b) is a schematic sectional drawing on the aa line of FIG. 2, and the bb line. It is a schematic sectional drawing which shows an example of the semiconductor substrate which comprises the switch semiconductor integrated circuit by this invention. (A) And (b) is a schematic sectional drawing of the principal part of an example of the switch semiconductor integrated circuit device by this invention, and its equivalent circuit schematic. (A) And (b) is a schematic sectional drawing of the principal part of an example of the switch semiconductor integrated circuit device by this invention, and its equivalent circuit schematic. (A) And (b) is a schematic sectional drawing of the principal part of an example of the switch semiconductor integrated circuit device by this invention, and its equivalent circuit schematic. (A) And (b) is a schematic sectional drawing of the principal part of an example of the switch semiconductor integrated circuit device by this invention, and its equivalent circuit schematic. (A) And (b) is a schematic sectional drawing of the principal part of an example of the switch semiconductor integrated circuit device by this invention, and its equivalent circuit schematic. It is the figure which showed the drain voltage-off capacity | capacitance which made the gate voltage the parameter. (A) And (b) is a schematic sectional drawing of the principal part of an example of the switch semiconductor integrated circuit device by this invention, and its equivalent circuit schematic. (A) And (b) is a schematic sectional drawing of the principal part of an example of the switch semiconductor integrated circuit device by this invention, and its equivalent circuit schematic. (A) And (b) is a schematic sectional drawing of the principal part of an example of the switch semiconductor integrated circuit device by this invention, and its equivalent circuit schematic. (A) And (b) is a schematic sectional drawing of the principal part of an example of the switch semiconductor integrated circuit device by this invention, and its equivalent circuit schematic. (A) And (b) is a schematic sectional drawing of the principal part of an example of the switch semiconductor integrated circuit device by this invention, and its equivalent circuit schematic. It is explanatory drawing of the drain voltage-off capacitance of the switch semiconductor integrated circuit by the 1st and 2nd embodiment of this invention. It is a figure which shows the relationship with the ratio of the change of the off capacitance with respect to the voltage change of the switch semiconductor integrated circuit by 1st and 2nd embodiment. It is a figure which shows the relationship with IMD of the switch semiconductor integrated circuit by 1st and 2nd embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... Isolation area, 3 ... Active area, 4G ... Gate electrode terminal, 4sub ... Substrate surface bias electrode terminal, 5 ... Substrate surface bias electrode, 5a ... Electrode part, 5b ...... Cross electrode part, 5c ... Peripheral electrode part, 6D ... Drain connection wiring layer, 6S ... Source connection wiring layer, 7 ... Contact region, 8 ... Insulating layer, 9 ... Intermediate wiring layer

Claims (8)

A semiconductor device in which a plurality of field effect transistors separated by an isolation region are connected in series on a semiconductor substrate,
A surface bias electrode in contact with the surface of the isolation region is disposed so as to be able to apply a bias to the substrate so as to face a source electrode or a drain electrode of at least some of the field effect transistors connected in series with each other. A switch semiconductor integrated circuit device characterized by that.   2. The switch semiconductor integrated circuit device according to claim 1, wherein a surface bias electrode in contact with the surface of the isolation region is disposed to face source electrodes of all the field effect transistors connected in series to each other. .   2. The switch semiconductor integrated circuit device according to claim 1, wherein a surface bias electrode in contact with the surface of the isolation region is disposed opposite to drain electrodes of all field effect transistors connected in series to each other. .   2. The switch semiconductor integrated circuit device according to claim 1, wherein the substrate surface bias electrode is disposed in parallel to a gate electrode related to the source electrode and the drain electrode opposed to the substrate surface bias electrode.   2. The switch semiconductor according to claim 1, wherein a length of the substrate surface bias electrode opposed to the source electrode and the drain electrode is selected to be equal to or longer than a length of the source electrode and drain electrode opposed to the gate electrode. Integrated circuit device.   2. The switch semiconductor integrated circuit device according to claim 1, wherein the isolation region has a required distributed resistance by introducing impurities.   2. The switch semiconductor integrated circuit device according to claim 1, wherein the substrate surface bias electrode is in contact with a contact region formed by selectively introducing impurities into the surface of the isolation region.   2. The switch semiconductor integrated circuit according to claim 1, wherein the field effect transistor is a junction gate field effect transistor, a Schottky gate field effect transistor, an insulated gate field effect transistor, or a field effect transistor having a heterojunction. Circuit device.

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