JPH0710678A - Wafer of compound semiconductor single crystal, its production process and epitaxial growth - Google Patents

Abstract

PURPOSE:To produce single crystal wafer of compound semiconductor which can form uniform membrane on the epitaxial growth by the boat method. CONSTITUTION:The concentration deviation of contaminants added to the crystal is made large, namely + or -6% or higher in the wafer face cut out of the single crystal of the compound semiconductor produced by the boat method. Further, the crystal is allowed to grow so that the angle theta between the face of the wafer 2 to be cut out and the crystal growth interface 1a, 1b is set over 30 deg..

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for producing a compound semiconductor crystal wafer by a boat method such as a horizontal Brissigman method (HB method), a temperature gradient method (GF method), a zone melt method, and the like. The present invention relates to an epitaxial growth method such as liquid phase epitaxial growth, vapor phase epitaxial growth, molecular beam epitaxial growth, etc., using the wafer prepared in 1. as a substrate.

[0002]

2. Description of the Related Art Applications of compound semiconductor single crystal wafers include substrates for electronic devices such as ICs and substrates for optical devices such as semiconductor lasers. Some IC substrates do not perform epitaxial growth, but in most cases they do. Here, GaAs will be described as the most typical example.

Substrates for electronic devices include non-doped semi-insulating wafers manufactured by the LEC method and Cr-doped semi-insulating wafers manufactured by the boat method. Further, a wafer doped with Si or Zn is generally used as a substrate for an optical device. Also,
The (100) plane is generally used as the crystal orientation of the wafer.

In the wafer, Cr, S as impurities
When a device is formed using a wafer doped with i, Zn, etc., it is common to grow epitaxially on a wafer substrate.

Conventionally, it has been considered that the deviation of the impurity concentration of the substrate adversely affects the production of these devices. Therefore, a method of manufacturing a wafer in which the impurity concentration distribution in the wafer is made as uniform as possible has been developed.

[0006] As a typical example conventionally developed to reduce this impurity concentration deviation, Japanese Patent Laid-Open No. 54-141388.
There is an issue. As shown in this, when growing a GaAs single crystal by the boat method, the direction equivalent to the <111> direction of the crystal is made parallel to the longitudinal direction of the boat, and
> It is a wafer cutting surface that is inclined 54.7 ° with respect to the direction (1
(00) The crystal growth solid-liquid interface shape was maintained so as to be substantially parallel to the equivalent plane. Since the solid-liquid interface of the (100) plane wafer obtained by this method is substantially parallel to this (100) wafer plane, the variation deviation of the impurity concentration within the wafer plane can be reduced to ± 3% or less. ing.

However, when epitaxial growth is carried out on such a wafer substrate, minute fluctuations may occur in the in-plane distribution of the epitaxially grown film thickness. In recent years, due to the reduction in element size, the increase in output of semiconductor lasers, etc., and the progress of technology for integrating many elements in a chip,
This small fluctuation in the film thickness distribution often causes a problem in variations in device characteristics.

[0008]

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks of the prior art, that is, the fluctuation of the film thickness distribution of the epitaxially grown film which has occurred in the conventional wafer substrate.

[0009]

The present invention has been made to solve the above-mentioned problems, and as a first invention,
In the wafer manufactured from the compound semiconductor single crystal manufactured by the boat method, the concentration deviation of the impurities in the plane of the wafer cut out from the compound semiconductor single crystal grown using the impurity-added raw material melt is ± A compound semiconductor single crystal wafer having a content of 6% or more is provided.

In the first invention, in a wafer manufactured from a compound semiconductor single crystal manufactured by the boat method, from a crystal grown using a raw material melt added with an impurity having a segregation coefficient of 1 or less, in the crystal longitudinal direction. From the vertical 30
It is preferable that the wafer is cut out at an angle within a range of ± 6% or more and ± 40% or less in the impurity concentration within the wafer surface cut out from the vicinity of the tail of the straight body of the grown crystal.

As a second invention, in a wafer manufactured from a compound semiconductor single crystal manufactured by a boat method, a compound semiconductor single crystal grown so that a growth interface of the crystal is not parallel to a (111) equivalent plane. The angle between the crystal growth interface and the wafer surface cut out is substantially 30 in at least half of the wafer surface cut out from the wafer.
Provided is a compound semiconductor single crystal wafer characterized by having a degree of rotation of not less than 100 degrees.

As a third invention, in a method of manufacturing a wafer from a compound semiconductor single crystal manufactured by a boat method, in the furnace of a crystal growing apparatus, temperature gradients in the longitudinal direction of the crystal growth interface and in the vertical direction of the furnace are respectively present. The method for manufacturing a compound semiconductor single crystal wafer is characterized in that the impurity concentration in the wafer plane cut out from the grown crystal is prevented from largely changing depending on the wafer cut-out position by changing the solidification rate depending on the solidification rate. provide.

In the third invention, in the method for producing a wafer from a compound semiconductor single crystal produced by the boat method, the compound semiconductor single crystal to be grown has a zinc blende type crystal structure and is grown. Single crystal <10
It is preferable that one direction equivalent to the 0> direction is within 30 degrees from the longitudinal direction of the boat.

Further provided is an epitaxial growth method characterized in that a compound semiconductor single crystal wafer manufactured by these methods is used as a substrate and a semiconductor layer is laminated on the substrate by epitaxial growth.

The structure of the present invention will be described in detail below. As a method of manufacturing a compound semiconductor, the boat method and the pulling method are well known. In general, the boat method has a feature that a single crystal having a smaller temperature gradient and less crystal defects can be grown as compared with the pulling method.

The boat method includes a horizontal Brissigman method (HB
Method), zone melt method, etc., in which the position of the crystal growth interface is fixed relatively to the crystal growth furnace heater, and a temperature gradient method in which the position of the crystal growth interface moves relatively to the crystal growth furnace. (GF method). In either method, the raw material melt is put in a long boat and the single crystal is grown by crystallizing from one end of the boat in a horizontal furnace having a temperature gradient in the longitudinal direction of the boat.

The concentration C of the impurity doped in the crystal in the crystal is calculated by the following equation (1) according to the crystal solidification rate g at each crystal position, the segregation coefficient k, and the average impurity concentration C ₀ in the initial raw material melt. It is determined. C = k × C ₀ × (1-g) ^k-1 ··· (1)

Here, C ₀ is determined by the amount of impurities to be doped in the crystal, and k is an amount determined by the type of the crystal to be grown and the type of impurities. Therefore, the concentration distribution in the crystal is controlled by the solidification rate g. There is a need to. It can be seen that in order to create the impurity concentration deviation in the wafer to be cut out, the effective solidification rate in the wafer needs to be distributed.

C at each of two points on the wafer surface to be cut out
_In order to obtain the impurity concentrations of ₁ and C ₂ , from the formula (1), C ₁ = k × C ₀ × (1-g ₁ ) ^k−1 ·· (2) C ₂ = k × C ₀ × ( 1-g ₂ ) ^k-1 ··· (3). Here, g ₁ and g ₂ represent the solidification rate at each point. In addition, the above-mentioned impurity concentration deviation d _c in the wafer surface
(%), When expressed as _{d c = (C 2 -C 1} ) / (C 1 + C 2) × 100 ·· (4), (4) expression (2) and (3), d _c = (1-Δg) / (1 + Δg) × 100 · (5) where Δg = {(1-g ₁ ) / (1-g ₂ )} ^k−1 , and C ₂ is an in-plane impurity on the wafer. The maximum density value, C ₁ , corresponds to the minimum value.

As described above, in order to provide a certain predetermined impurity concentration deviation within the wafer surface, it is sufficient to provide a distribution of the solidification rate as shown in equation (5) within the wafer surface.

Next, a method for creating a solidification rate distribution in a wafer will be described. The solidification rate g of the crystal is the weight W _s of the crystallized crystal during growth with respect to the weight W _m of the melt during seeding.
(G = W _s / W _m ), of course, the solidification rate is the same on the growing solid-liquid interface at a certain point during crystal growth. Providing a solidification rate distribution within a certain wafer surface causes a time difference when solidifying within the wafer surface to be cut out. Therefore, a solidification rate distribution can be created in the wafer by making the solid-liquid interface during growth and the wafer surface to be cut out not parallel to each other but intersect at a certain angle θ.

For simplicity, let us consider the case as shown in FIG. When a wafer is cut out perpendicularly to the longitudinal direction of the boat, the crystal growth interface shape and the cut out wafer intersect at an angle θ. The solidification rate is g when the total length of the crystal to be grown is L (mm) and the growth distance when the growth interface is near the free surface of the wafer position to be cut out like the growth interface position 1a is d ₁ (mm). _Set to ₁ .

Further, the solidification rate is g ₂ when the free surface growth distance is d ₂ (mm) when the growth interface position is near the bottom of the boat at the wafer position to be cut out like the growth interface position 1b. At this time, the relationship between the impurity concentration in the wafer, the solidification rate of these, and the growth distance can be approximated as g ₁ = d ₁ / L and g ₂ = d ₂ / L ··· (6).

When the crystal height is H (mm) and the angle between the growth interface shape and the cut wafer is θ, the relationship between d ₁ and d ₂ is: d ₂ = d ₁ + H × tan θ, g ₂ = g ₁ + (H × tan θ) / L · · (7)

Equations (2), (3), (4), (6),
From (7), the impurity concentration deviation d _c (%) can be obtained from the angle θ between the growth interface and the wafer to be cut and the solidification rate g ₁ . As described above, it is understood that the impurity concentration distribution in the wafer can be controlled by controlling the crystal growth interface shape and the wafer cutting angle. Here, some assumptions have been described for simplification, but to adapt to the actual boat shape and the like, the above concept can be basically used although it is slightly complicated. Further, when actually growing a crystal, it is difficult to make the growth interface completely flat, and it is common that the crystal has a certain curvature, but even in such a case, substantially no problem occurs.

In FIG. 3, when the segregation coefficient k = 0.15, the in-wafer impurity concentration deviation d _c (%) is ±.
According to the solidification rate g ₁ , the inclination θ of the growth interface is large in the small solidification area and gradually small in the small solidification area according to the solidification ratio g ₁ so as to be constant at 6, ± 10, ± 20%. An example is shown in the case of changing to. By changing θ in this way, the impurity concentration deviation d _c in the wafer can be controlled to be constant over almost the entire crystal, which is preferable.

As described above, it was found that the impurity concentration in the wafer can be controlled by controlling the crystal growth interface shape and the wafer cutting angle. Here, some assumptions are described for simplification, but to adapt to the actual boat shape, etc., the above concept can be basically used although it is slightly complicated. Further, when actually growing a crystal, it is difficult to make the growth interface completely flat and generally has a certain curvature, but even in such a case, there is substantially no problem.

Next, a method of controlling the growth interface shape will be described. The solid-liquid interface shape is determined almost perpendicular to the direction of the synthetic temperature gradient vector formed by the temperature gradient in the furnace longitudinal direction and the vertical direction near the solid-liquid interface in the crystal manufacturing furnace. That is, it is possible to make the solid-liquid interface shape close to vertical by increasing the temperature gradient in the longitudinal direction and decreasing the temperature gradient in the vertical direction.

As described above, by controlling the shape of the solid-liquid interface by the temperature gradient in the furnace, the angle θ with the wafer to be cut can be determined, and the solidification rate distribution in the wafer surface is generated, which is substantially the same. It is possible to create an impurity concentration gradient within the wafer.

Regarding the solid-liquid interface shape, it is better to let the upper part of the crystal grow above the melt side so that the solidification of the crystal starts from the free surface of the raw material melt and progresses toward the bottom of the boat. It is preferable because a crystal with few crystal defects can be obtained.

The impurity concentration deviation d _c within the wafer surface in the first aspect of the present invention is preferably d _c ≧ ± 6%, more preferably ± 8% or more, preferably ± 8, although it varies depending on the added impurities. It is preferably 10% or more. Furthermore, a large density deviation of ± 20% or more is more preferable. However, if there is a concentration deviation of ± 100% or more, problems such as variations in element resistance of the created device become remarkable, which is not so preferable from the viewpoint of homogenizing device characteristics. When Si is added to GaAs, the above concentration deviation is preferable, but when Zn is added, d
_{Even if c} ≧ ± 5%, there is some effect.

FIG. 2 shows the case where the growth interface inclination θ = 60 ° and the segregation coefficients k = 0.15, 0.3, and 0.8 with respect to the solidification rate g ₁ at the upper part of each wafer. , And the calculation results of the concentration deviation d _c (%) within each wafer surface are shown.
As can be seen from the figure, the concentration deviation d _c can be increased as the solidification rate approaches 1. To obtain a wafer with an impurity concentration deviation within the wafer of ± 6% or more, k =
Taking the case of 0.15 as an example, the solidification rate g at θ = 60 °
It can be obtained by cutting out a portion where ₁ is about 0.5 or more.

FIG. 3 shows an example of the segregation coefficient k = 0.15.
In-wafer impurity concentration deviation d _c (%) is ± 6%,
The inclination θ of the growth interface with respect to the solidification rate g ₁ which is constant in the crystal of ± 10% and ± 20% is shown. For example, d _c = ± 10
In order to obtain a wafer of not less than 10% from the whole crystal, θ can be obtained by making θ larger than θ shown by the curve of d _c = 10% shown in FIG. 3 with respect to the crystal solidification rate. That is, several methods are conceivable, such as a method of setting θ = 70 ° over the entire crystal.

However, the range of impurity concentration in the wafer is
There is a predetermined range that is tolerated by the device being made, and almost every point within the wafer needs to fall within this impurity concentration range. It is preferable that a wafer having a predetermined impurity concentration can be efficiently cut out by designing so that almost all of the region where the wafer can be cut out from the grown crystal is within the predetermined impurity concentration range.

As a method for designing the maximum impurity concentration in the wafer cut out from the vicinity of the tail of the crystal within a predetermined range, it is necessary to set C ₀ in the equation (1) to an appropriate size. However, considering the case where the inclination θ of the growth interface shape near the tail is large and the case where it is small, the effective solidification rate at the point where the impurity concentration in the wafer is maximum is closer to 1 when θ is large. Therefore, when θ becomes large, it becomes necessary to make C ₀ very small, and it is necessary to make the impurity concentration of the portion close to the seed crystal very small.
It becomes difficult to achieve a predetermined impurity concentration in the entire region where the wafer can be cut out.

Therefore, as in the first aspect of the invention, the growth interface is controlled so that θ becomes small in the vicinity of the tail (at least when the wafer cutting position of the straight body portion closest to the tail is solidified), and impurities in the wafer are controlled. The concentration distribution is preferably ± 40% or less. Further ± 30% or less, ± 20%
Hereinafter, it is preferable that the content is ± 10% or less for the same reason.

Further, as shown in FIG. 2, when the crystal is grown with a constant θ, the deviation of the impurity concentration in the seed-side wafer and the deviation of the impurity concentration in the tail-side wafer of the obtained crystal are about 10 times. The above may be different.
As described above, when the difference in the d _c in the wafer between the wafers is as large as 10 times or more, it is necessary to change the epitaxial conditions. Therefore, as in the third aspect of the invention, it is preferable that the difference in the wafer d _c between the wafers is within 5 times. Further, it is preferably 4 times or less and 2 times or less.

Specifically, by changing the inclination θ of the growth interface with respect to the solidification rate g ₁ so as to be substantially parallel to the curve having the same d _c shown in FIG. 3, d _c between the wafers is changed. The difference between can be reduced. Therefore, it can be realized by increasing the temperature gradient in the furnace longitudinal direction near the growth interface in the crystal growth furnace relative to the temperature gradient in the furnace up-down direction and gradually decreasing θ along with the crystal growth.

Further, this impurity concentration deviation is not a mere variation of the impurity concentration distribution in the wafer, but a more uniform concentration gradient from one side to the other side in the wafer improves the homogeneity of the epitaxial growth film. Is preferable.

The method of analyzing the impurity concentration is SI
In addition to the direct analysis of MS and the like, it is also possible to substitute by electric carrier concentration distribution measurement. At this time, it is more preferable to determine the impurity concentration distribution in consideration of the electrical activation rate of the impurities.

In order to increase the concentration deviation, it is desired to increase the difference θ between the crystal solid-liquid interface and the cut wafer angle. For this reason, in order to cut out a (100) plane-oriented wafer, the wafer <100> is almost parallel to the longitudinal direction of the boat.
It is preferable to select a direction equivalent to the direction and incline the solid-liquid interface from the vertical because a large impurity concentration gradient can be created in the wafer.

The range of θ is preferably 30 ° or more, more preferably 40 ° or more, 50 ° or more, 60 ° or more, 7
A larger angle of 0 ° or more is preferable because the impurity concentration deviation d _c can be increased and a large number of growth fringes are formed in the cut wafer surface.

However, crystal habit (facet) may occur in the crystal. It has been found that the appearance of this facet in the majority of the wafer adversely affects the device characteristics because the growth mechanism is different from other parts. In the case of zinc blende type crystals,
This facet generally appears in the (111) equivalent plane. Therefore, when the growth interface is almost parallel to the (111) equivalent plane, the (111) equivalent plane is a facet which is likely to be a facet.
It is preferable that the growth interface shape is deviated to some extent from the (111) equivalent plane because facets are incorporated into many portions in the wafer, which is not preferable.

In order to increase the deviation of the solidification rate in the plane of the wafer, the crystal length should be within 1 m, preferably 8 m.
It is preferable to shorten the length to 00 mm or less, and further to 600 mm or less because the change in the solidification rate with respect to the crystal growth distance becomes large.

[0045]

In the past, it was generally believed that the smaller the impurity concentration deviation, the smaller the variation in device characteristics. However, in the present invention, since there is an impurity concentration deviation within the wafer surface, liquid phase epitaxial growth, It has been experimentally confirmed that the small fluctuations that have conventionally occurred in the epitaxially grown film thickness distribution become extremely small when performing phase epitaxial growth or molecular beam epitaxial growth. The mechanism is not known in detail, but we speculate as follows.

The phenomenon of epitaxial growth on a substrate is as follows: (1) generation of two-dimensional nuclei (steps) to serve as nuclei for growth on the substrate surface, (2) substrate surface of atoms and molecules from the environmental phase, which is the source of raw materials. Epitaxial growth can be performed as a general result of diffusion, (3) in-plane direction growth of steps by incorporating atoms and molecules into the steps, and the three processes.

One of the most important conditions for controlling these phenomena is the supercooled state of the raw material atoms or molecules supplied onto the substrate. In the case of liquid phase epitaxial,
This supercooled state can be controlled by controlling the composition and temperature of the raw material melt, and in the case of vapor phase epitaxial growth, controlling the substrate wafer temperature and gas pressure.

Generally, the smaller the supercooling degree is, the smaller the growth rate is, but it is easy to obtain a good epitaxial crystal. However, if the degree of supercooling is too small, the generation of steps is less likely to occur. Therefore, generate a step with an appropriate probability,
Further, it is necessary to control the growth rate to an appropriate rate so that a good crystal can be obtained, but the appropriate supercooling degree range is narrow.

If there are many dislocation defects in the substrate wafer, the strain of surface energy generated around the dislocation defects easily traps the atoms and molecules diffusing on the wafer surface around the dislocations. Dimensional nucleation is likely to occur at a relatively low degree of supercooling. However, many dislocation defects are not preferable because they adversely affect the electrical characteristics and reliability of the device.

An appropriate surface energy fluctuation occurs in a wafer having a large impurity concentration deviation according to the present invention or a wafer cut out at an angle of 30 degrees or more with a crystal growth interface so as to have many growth stripes in the wafer. It is believed that Atoms and molecules diffusing on the wafer surface during epitaxial growth can be selectively trapped in the portion where the surface energy fluctuates, and two-dimensional nucleation can be stably generated even at a relatively low supercooling degree. Therefore, it is considered that epitaxial growth with a flat film thickness distribution can be achieved.

On the other hand, when performing epitaxial growth on a conventional wafer substrate having a small impurity concentration deviation,
The fluctuation of the surface energy is very small, and the two-dimensional nucleation is unlikely to occur under the condition that the degree of supercooling is low. Further, when the degree of supercooling is increased to some extent, the surface energies in the wafer surface are substantially equal, and therefore, when the threshold degree of supercooling is exceeded, a large number of two-dimensional nuclei are generated everywhere in the wafer surface. Then, rapid crystal growth occurs around each nucleus, which is considered to be the cause of minute fluctuations in the film thickness distribution.

For the above reasons, the film thickness distribution of the epitaxial growth film, which has become a problem in recent years due to the reduction in device size, the increase in output of semiconductor lasers, etc., or the progress in the technology of integrating many devices in a chip. It is possible to solve the occurrence of the minute fluctuation of the above by increasing the impurity concentration deviation of the wafer substrate as in the present invention.

[0053]

【Example】

(Embodiment 1) An embodiment for producing a GaAs single crystal will be described below. A cross-sectional shape of the boat for crystal growth perpendicular to the longitudinal direction was about 80% circular, and the boat was <10 with respect to the longitudinal direction of the crystal to be grown.
The seed crystal was placed so that one direction equivalent to the 0> direction was parallel.

As shown in FIG. 4, about 4000 g is put in the boat 3.
Ga (reference numeral 4) and a small amount of Si are put therein, and about 4400 g of As (reference numeral 6) is put into the other end of the reaction vessel 7, and the inside of the reaction vessel 7 is depressurized to a vacuum state and sealed. Next, the reaction vessel 7 is placed in a crystal growth furnace to raise the temperature, and Ga and As vapor are reacted to synthesize GaAs. After that, the seed crystal 5 and the GaAs melt are brought into contact with each other.

After that, the temperature of the melt is gradually lowered and cooled to grow crystals. The temperature gradient in the longitudinal direction and the temperature gradient in the vertical direction in the growing furnace were adjusted so that the growth interface at this time was inclined by about 60 degrees from the vertical direction. Further, after completely solidifying, the temperature was further lowered to room temperature and the crystal was taken out to obtain about 8300 g of a GaAs single crystal.

By cutting the obtained crystal perpendicularly to the longitudinal direction, a (100) equivalent plane circular wafer could be prepared. The carrier concentration deviation in the wafer was ± 5% on the seed side where the solidification rate was small, and ± 60% on the tail side where the solidification rate was close to 1. The surfaces of these wafers were mirror-polished to obtain substrates for epitaxial growth.

Epitaxial growth was performed by MOCVD, which is a type of vapor phase growth. As a source gas, T
MG (trimethyl gallium), arsine (AsH _3: Hydrogenation arsenic), were grown AlGaAs using TMA (trimethylaluminum). As the dopant gas,
DEZn (diethyl zinc) and hydrogen selenide were used. These gases were introduced into the reaction vessel at a predetermined partial pressure using hydrogen gas as a carrier gas, and epitaxial growth was performed at a reaction pressure of about 0.1 atm and a substrate wafer temperature of about 700 ° C.

There was almost no minute fluctuation in the film thickness distribution of the epitaxial film of the obtained wafer, and it was very flat. Further, as a result of forming a semiconductor laser from this epitaxially grown wafer, the variation in brightness was about 1/3 of the case of using the conventional wafer, which was very good.

Example 2 Using the same boat as in Example 1, Ga and As vapor are reacted in the same manner in the crystal growth furnace to synthesize GaAs. After that, seed crystal and GaAs
Contact the melt. Then, the temperature of the melt is gradually lowered and cooled to grow crystals. At this time, on the seed side having a small solidification rate, the longitudinal temperature gradient and the vertical temperature gradient in the growing furnace were adjusted so that the growth interface shape was inclined by about 80 degrees from the vertical direction. Further, the angle was decreased as the crystal grew, and the temperature gradient was adjusted so that the angle was about 50 degrees near the tail. Furthermore, after completely solidifying, the temperature was further lowered to room temperature and the crystal was taken out to obtain about 8300 g of a GaAs single crystal.

By cutting the obtained crystal perpendicularly to the longitudinal direction, a (100) equivalent plane circular wafer could be prepared. The carrier concentration deviation within the wafer was ± 20% on the seed side where the solidification rate was small, and ± 25% on the tail side where the solidification rate was close to 1. As compared with Example 1, it was possible to obtain a crystal in which the carrier deviation in the wafer did not change much on the seed side and the tail side. The surfaces of these wafers were mirror-polished to obtain substrates for epitaxial growth.

Epitaxial growth was performed using TMG, arsine, and TMA as source gases as in Example 1.
lGaAs was grown. The obtained wafer was extremely flat with almost no fluctuation in the film thickness distribution of the epitaxial film. Further, as a result of producing a semiconductor laser from this epitaxially grown wafer, the variation in brightness was about 1/4 of that in the case of using the conventional wafer, which was very good as compared with Example 1. This is considered to be because the magnitude of the carrier deviation in each wafer did not change much depending on the position where the wafer was cut out from the grown crystal.

[0062]

As described above, according to the present invention, by increasing the deviation of the impurity concentration in the wafer, the homogeneity of the epitaxial growth film is improved, and variations in device characteristics are reduced and characteristics are improved. effective.

[Brief description of drawings]

FIG. 1 is a schematic crystal side sectional view showing a relationship between a crystal growth interface shape and a wafer cut surface.

FIG. 2 is a graph showing the relationship between the in-plane impurity concentration deviation d _c and the solidification rate g ₁ when the inclination of the crystal growth interface is constant.

FIG. 3 is a graph showing the inclination θ of the crystal growth interface with respect to the solidification rate g ₁ such that the in-plane impurity concentration deviation d _c becomes constant.

FIG. 4 is a side sectional view in the longitudinal direction of a reaction container when a crystal is grown by the boat method.

[Explanation of symbols]

 1a: crystal growth interface 1b: crystal growth interface 2: wafer to be cut out 3: boat 4: Ga 5: seed crystal 6: As 7: reaction vessel

Claims (6)

[Claims] 1. A wafer produced from a compound semiconductor single crystal produced by the boat method, wherein the impurities are present in the plane of the wafer cut out from the compound semiconductor single crystal grown by using an impurity-added raw material melt. A compound semiconductor single crystal wafer having a concentration deviation of ± 6% or more. 2. A wafer manufactured from a compound semiconductor single crystal manufactured by the boat method, from a crystal grown by using a raw material melt to which impurities having a segregation coefficient of 1 or less are grown, from a direction perpendicular to the longitudinal direction of the crystal. 2. The compound semiconductor single crystal according to claim 1, wherein the wafer is cut at an angle of less than 60 degrees, and the impurity concentration deviation in the plane of the wafer cut from the vicinity of the tail of the grown crystal is ± 6% or more and ± 40% or less. Crystal wafer. 3. A wafer produced from a compound semiconductor single crystal produced by the boat method, which is cut out from a compound semiconductor single crystal grown so that a growth interface of the crystal is not parallel to a (111) equivalent plane. The compound semiconductor single crystal wafer, wherein the angle between the crystal growth interface and the wafer surface to be cut is substantially 30 degrees or more in at least half of the in-plane. 4. A method for producing a wafer from a compound semiconductor single crystal produced by the boat method, wherein temperature gradients in the furnace longitudinal direction and the furnace up-down direction near the crystal growth interface in the crystal growing apparatus furnace are controlled by the solidification rate. A method for producing a compound semiconductor single crystal wafer, which is characterized in that the impurity concentration distribution in the plane of the wafer cut out from the grown crystal is not changed largely by changing the wafer cutting position. 5. A method for producing a wafer from a compound semiconductor single crystal produced by the boat method, wherein the compound semiconductor single crystal to be grown has a zinc blende type crystal structure, and The method for producing a compound semiconductor single crystal wafer according to claim 4, wherein one direction equivalent to the 100> direction is within 30 degrees from the longitudinal direction of the boat. 6. An epitaxial growth method, which comprises using the compound semiconductor single crystal wafer according to claim 1 as a substrate and stacking semiconductor layers on the substrate by epitaxial growth.