JPH07106518A - Semiconductor integrated circuit and its manufacture - Google Patents

Abstract

PURPOSE:To provide a semiconductor integrated circuit capable of being made without considerably increasing steps, and having a power source bypass capacitor of high breakdown strength and large capacitance. CONSTITUTION:As a memory cell capacitor and a power source bypass capacitor, a composite insulated film 7 composed of a dielectric film having specific breakdown strength and a dielectric film having a higher dielectric constant than this dielectric film is interposed between an upper electrode 8 and a lower electrode 6. Such structure is formed on a same semiconductor substrate. Each electrode and dielectric film constituting these memory cell capacitor and power source bypass capacitor are formed respectively in the same steps.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DRAM (Dynamic Random Access Memo) equipped with both a capacitor for retaining information and a capacitor for removing power supply noise.
ry) and other semiconductor integrated circuits.

[0002]

2. Description of the Related Art Conventionally, as a capacitor formed in a semiconductor integrated circuit, a MOS structure capacitor in which a SiO ₂ film is interposed between a substrate and electrodes made of polysilicon has been known. In this MOS structure capacitor, a SiO ₂ film is formed on the surface of a Si substrate as a lower electrode by thermal oxidation, and a conductor layer such as polysilicon as an upper electrode is laminated on the SiO ₂ film. It is obtained by

A capacitor of this type is a DRAM.
Etc., it is used as a memory cell capacitor for holding a voltage corresponding to information to be stored.

[0004]

By the way, in a semiconductor integrated circuit, noise is generated between a power supply and a ground as transistors and the like inside the semiconductor integrated circuit perform a switching operation. Particularly in a DRAM or the like, this noise is absorbed. A power supply bypass capacitor is required. Here, if the polysilicon layer as the upper electrode is connected to the power supply Vcc and the Si substrate as the lower electrode is connected to the ground Vss, MO
A power supply bypass capacitor can be formed by an S-structure capacitor.

However, in the above-described MOS structure capacitor, since the Si substrate which is the lower electrode is the inversion layer of the MOS transistor, the sheet resistance is generally several K.
It is as high as Ω / □. Therefore, in this type of capacitor, the resistance of the electrode itself is relatively high, so that there is a problem that noise cannot be sufficiently removed when used as a power supply bypass capacitor.

As the dielectric film of the MOS structure capacitor, a SiO ₂ film obtained by thermally oxidizing a Si substrate as described above is generally used. The SiO ₂ film thus obtained is used. _{The two} films usually have defects at a rate of about 2 / cm ² . Therefore, when forming a capacitor having a large electrode area to obtain a relatively large capacity such as a power supply bypass capacitor, or when forming a large number of capacitors such as a memory cell capacitor of DRAM on a Si substrate, defects are included. The probability that a capacitor will be formed becomes extremely high, and the formation of defective capacitors in this manner causes a problem that the manufacturing yield of semiconductor integrated circuits is reduced.

In particular, the power supply bypass capacitor is required to have a high withstand voltage because the power supply voltage is directly applied to it. However, it cannot be said that a capacitor having a MOS structure used as a memory cell capacitor is not suitable as a power supply bypass capacitor because its withstand voltage is not so high.

If the thickness of the dielectric film inserted between the electrodes is increased, the breakdown voltage of the MOS structure capacitor can be increased. However, when the MOS structure capacitor is used as the power supply bypass capacitor, it is necessary to increase the capacitance thereof in order to remove the abrupt switching noise, and for that purpose, the area of the capacitor electrode must be increased. However, as described above, MOS
Since the insulating film in a structural capacitor has a high defect rate, it has a large capacity M that can be used as a power supply bypass capacitor
It is difficult to form an OS structure capacitor, and it has not yet been put into practical use.

The present invention has been made in view of the above circumstances, and provides a semiconductor integrated circuit including a large-capacity and high-voltage power supply bypass capacitor and a memory cell capacitor without significantly increasing the number of steps. Is intended.

[0010]

The invention according to claim 1 is
A memory upper electrode and a memory lower electrode to which a voltage corresponding to information to be stored is applied, and a memory insulating film including a high dielectric film laminated between the memory upper electrode and the memory lower electrode. And a bypass capacitor upper electrode and a bypass capacitor lower electrode, each of which is connected to one of a power supply and a ground, and a bypass capacitor stacked between the upper electrode and the lower electrode. A power supply bypass capacitor composed of an insulating film and a dielectric film for bypass capacitor added to the upper layer thereof is formed on the same semiconductor substrate, and the upper electrode for bypass capacitor and the lower electrode for bypass capacitor are A conductor containing at least polysilicon, which is used as the memory upper electrode and the memory. SUMMARY OF THE INVENTION A semiconductor integrated circuit is characterized in that it is formed in the same step as that of a lower electrode for a capacitor, and the insulating film for a bypass capacitor and the insulating film for a memory are formed in the same step. . A second aspect of the present invention provides a semiconductor integrated circuit according to the first aspect, wherein the memory insulating film and the bypass capacitor insulating film are composite insulating films. According to a third aspect of the present invention, an electrode made of a conductive film containing at least polysilicon is provided on a semiconductor substrate on which a memory cell transistor is formed, and a memory lower electrode connected to the memory cell transistor. A step of forming a bypass capacitor lower electrode connected to one of a power source or a ground, and a step of forming an insulating film including a high dielectric film on the memory lower electrode and the bypass capacitor lower electrode, Forming a bypass capacitor dielectric film in a region of the insulating film corresponding to the bypass capacitor lower electrode;
An electrode formed of a conductor film each containing at least polysilicon, the memory upper electrode facing the memory lower electrode with the insulating film sandwiched therebetween, and the insulating film and the bypass capacitor dielectric film sandwiched with each other. And a step of forming a bypass capacitor upper electrode facing the bypass capacitor lower electrode and being connected to the other of the power supply and the ground, and a method for manufacturing a semiconductor integrated circuit.

[0011]

The semiconductor integrated circuit according to claim 1 or 2 can be manufactured without adding a large process to the process required to form the memory cell capacitor, and moreover, it can be manufactured as a high-performance power supply bypass capacitor. Capacitors with high withstand voltage can be obtained with high reliability. Claim 1
The semiconductor integrated circuit according to the second and second aspects can be manufactured by the manufacturing method according to the third aspect.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view of a stack type memory cell of a DRAM to which the present invention is applied. In the figure, a MOS transistor for controlling writing / reading of information to be stored is shown in the left part from the center, and a memory cell in which charging / discharging is performed via this MOS transistor is shown in the right part. A capacitor is shown.
First, the configuration of the MOS transistor will be described. In FIG. 1, 1 is S doped with a low concentration of P-type impurities.
i substrate. 2 is the source of the MOS transistor,
A high-concentration N-type impurity diffusion region formed as a drain,
Reference numeral 3 is an element isolation SiO ₂ film, and 4 is an interlayer insulating film. 5
Is a polysilicon layer. Among these polysilicon layers, a polysilicon layer located between the source and drain of the MOS transistor constitutes a gate electrode of the MOS transistor, and serves as a word line of the memory cell. Used. Reference numeral 9 is a data line of a memory cell made of a conductor film such as Al (aluminum), and a part of the data line is connected to one of the high-concentration N-type impurity diffusion layers 2.

Next, the structure of the memory cell capacitor will be described. In FIG. 1, reference numeral 6 denotes a lower electrode, which is composed of a conductor layer obtained by doping polysilicon with phosphorus or arsenic. A part of the lower electrode 6 is connected to the high concentration N-type impurity diffusion region 2. Reference numeral 7 is an insulating film of the memory cell capacitor, which is laminated so as to cover the lower electrode 6. The insulating film 7 has a multi-layer structure in which at least a high dielectric film is interposed, and details thereof are shown in FIG. Reference numeral 8 is an upper electrode of the memory cell capacitor laminated on the insulating film 7, and is composed of polysilicon doped with phosphorus or arsenic.

In such a structure, when the positive voltage is applied to the word line 5, the Si substrate 1 immediately below the word line 5 is applied.
When an inversion layer is formed on the surface of, the voltage applied to one high-concentration N-type impurity diffusion region 2 via the data line 9 is applied to the other high-concentration N-type impurity diffusion region 2 via the inversion layer. As a result, the memory cell capacitor including the lower electrode 6, the insulating film 7 and the upper electrode 8 is charged to the voltage level corresponding to the information to be stored. Information is written in this way. Information is also read by applying a positive voltage to the word line 5 in the same manner as described above, but in this case, the voltage charged in the memory cell capacitor goes through the route opposite to the above and the data line 9 is read. Read out.

Next, the detailed structure of the memory cell capacitor will be described with reference to FIG. As shown in the figure, the memory cell capacitor has a lower SiO ₂ film 71, a high dielectric film 72 and an upper S film between the lower electrode 6 and the upper electrode 8.
The structure is such that the composite insulating film 7 formed by stacking the iO ₂ film 73 is interposed. Here, the lower SiO ₂ film 71 is formed by exposing the surface of the lower electrode 6 to an atmosphere containing oxygen and naturally oxidizing it, and has a thickness of about 20Å. The high dielectric film 72 is a film made of Si ₃ N ₄ or the like having a thickness of about 80Å deposited on the lower SiO ₂ film 71 by the CVD (Chemical Vapor Deposition) method or the like. The upper SiO ₂ film 73 is obtained by oxidizing the high dielectric film 72 and has a thickness of about 20Å.

The withstand voltage of about 7 V is obtained in the memory cell capacitor having this structure. On the other hand, since half the power supply voltage Vcc is normally applied to the upper electrode 8, when the power supply voltage Vcc is 5V, the maximum applied voltage to the memory cell capacitor is 2.5V. Therefore, it can be said that the memory cell capacitor of this structure has a withstand voltage sufficiently higher than the maximum applied voltage, and a highly reliable DRAM can be configured.

FIG. 3 is a sectional view showing the structure of the power supply bypass capacitor of the DRAM to which the present invention is applied. Figure 1 above
In order to clarify the correspondence with the constituent elements in the memory cell shown in FIG. 3, in FIG. 3, the elements corresponding to the elements shown in FIG. Has been done.

As shown in FIG. 3, this power supply bypass capacitor has the same process as the lower electrode 6 formed on the element isolation SiO ₂ film 3 in the same process as that of the memory cell capacitor. Lower SiO formed by
_A composite insulating film 7 including a ₂ film 71, a high-dielectric film 72 and an upper SiO ₂ film 73, and an upper SiO ₂ film 74 for improving the withstand voltage formed by a process particularly added to the power supply bypass capacitor. The upper electrode 8 formed in the same step as that of the memory cell capacitor is laminated. An insulating film made of SiO ₂ or the like is formed on the upper electrode 8, and wiring electrodes 10 for the lower electrode 6 and the upper electrode 8 are made of Al (aluminum) or the like. The lower electrode 6 and the upper electrode 8 are each connected to either the power supply Vcc or the ground.

Here, the lower SiO 2 in the composite insulating film 7
_{The 2nd} film 71 is a SiO ₂ film having a thickness of about 10 to 20Å formed by spontaneously oxidizing the surface of the lower electrode 6, and is the lower SiO ₂ film 71 of the memory cell capacitor.
Are simultaneously formed in the process of forming. Further, the high dielectric film 72 in the composite insulating film 7 is 40 to 120Å
The Si ₃ N ₄ film having a thickness in the range is deposited at the same time when the high dielectric film 72 in the memory cell capacitor is deposited by the CVD method or the like. Similarly, the upper SiO ₂ film 73 is also the upper SiO ₂ film 7 in the memory cell capacitor.
It is formed at the same time as 3.

The SiO ₂ film 74 on the composite insulating film 7 is CV
By the D method or the like, it is deposited so that the total film thickness together with the upper SiO ₂ film 73 is 50 to 600 Å. This SiO ₂
The film 74 is particularly laminated in order to obtain the withstand voltage required for the power supply bypass capacitor. Where Si
When the combined thickness of the O ₂ films 73 and 74 is 50 Å, the breakdown voltage is 3 V or higher. On the other hand, if the film thickness is set to 600 Å or more, the capacity of the power supply bypass capacitor itself is lowered. Therefore, as described above, the SiO ₂ film 74 is
Lamination is performed so that the total thickness of the iO ₂ film 73 and the iO ₂ film 73 is in the range of 50 to 600 Å.

<Manufacturing Method> The manufacturing method of the portion corresponding to the memory cell capacitor and the power supply bypass capacitor of the DRAM according to this embodiment will be described below. (1) After forming a MOS transistor for a memory cell on a Si substrate 1 as shown in FIG. 1, a conductor film containing polysilicon is laminated, and its patterning is performed.
Lower electrode 6 for memory cell capacitor connected to high-concentration N-type impurity diffusion region 2 of S transistor (see FIG. 1)
And the lower electrode 6 (see FIG. 3) for the power supply bypass capacitor are formed. (2) Next, a lower SiO ₂ film 71 having a thickness of about 10 to 20Å is formed on the surface of the lower electrode 6 for the memory cell capacitor and the surface of the lower electrode 6 for the bypass capacitor by natural oxidation. A high dielectric film 72 such as a Si ₃ N ₄ film is deposited by the CVD method or the like. And
An upper SiO ₂ film 73 is formed on the high dielectric film 72.
Thus, the composite insulating film 7 is formed as a part of the interelectrode insulating film of the memory cell capacitor and the interelectrode insulating film of the power supply bypass capacitor. (3) Next, after depositing SiO ₂ by a CVD method or the like, patterning is performed, and the SiO ₂ film 74 is formed in a region corresponding to above the lower electrode 6 for the power supply bypass capacitor.
To form. (4) Then, after laminating a conductor film containing polysilicon, patterning is performed to form an upper electrode 8 facing the lower electrode 6 for the memory cell capacitor and an upper electrode facing the lower electrode 6 for the power supply bypass capacitor. The electrode 8 is formed.

<Effects of this Embodiment> As described above, the power supply bypass capacitor in this embodiment includes the lower electrode 6, the composite insulating film 7 made of a high dielectric film, and the upper electrode 8.
Can be formed by sharing the step of forming each layer in the memory cell capacitor and adding only the step of forming the SiO2 film 74 for improving the withstand voltage, without causing a large increase in steps. High capacity and high withstand voltage can be manufactured with high reliability.

Further, in the capacitors such as the memory cell capacitor and the power supply bypass capacitor adopted in the above-mentioned embodiments, the electrodes have polysilicon as a part thereof, and the sheet resistance is 2 to 60 Ω / □. On the other hand, in the conventionally used MOS structure capacitor, one electrode is the surface of the Si substrate on which the inversion channel of the MOS transistor is formed, and the sheet resistance is several 100 to several KΩ / □. Therefore, the capacitor adopted in this embodiment has an improved frequency response as compared with the conventional MOS structure capacitor, and is particularly useful for noise reduction. In addition, especially when a composite insulating film is formed as the insulating film, the defect rate can be extremely reduced,
In recent years, it is useful as a power supply bypass capacitor provided in a semiconductor integrated circuit which has been speeded up.

<Other Embodiments> (1) In the capacitor according to the present invention, various insulating films can be used. For example, instead of Si ₃ N ₄ , Ta ₂ O ₅ , SrTiO ₃ or You may use PZT etc. (2) Si ₃ N ₄ is not formed by the CVD method, but the lower electrode 6 is formed by N ₂
It can also be formed by a thermal nitriding method of exposing to high temperature in an atmosphere. In the above practical example, the composite insulating film between the electrodes of the capacitor had a three-layer structure of SiO ₂ —Si ₃ N ₄ —SiO ₂ , but in this case, the insulating film is Si ₃ N ₄ —SiO ₂ . (3) In the above embodiment, S is used as the insulating film for improving the breakdown voltage.
Although the iO ₂ film 74 is formed, the material of the insulating film is Si.
The material is not limited to O ₂ , but any material having a high breakdown voltage such as Si ₃ N ₄ can be applied.

[0025]

As described above, according to the present invention, a semiconductor integrated circuit having a power supply bypass capacitor can be manufactured without adding a large process to the process required to form a memory cell capacitor. There is an effect that can be. Further, the semiconductor integrated circuit according to the present invention has a high capacity and a high withstand voltage as a power supply bypass capacitor, and therefore has an advantage of high performance and high reliability.

[Brief description of drawings]

FIG. 1 is a sectional view showing a configuration of a memory cell portion in an embodiment in which the invention is applied to a DRAM.

FIG. 2 is a cross-sectional view showing a detailed configuration of a memory cell capacitor in a memory cell portion of the DRAM.

FIG. 3 is a sectional view showing a configuration of a power supply bypass capacitor portion of the DRAM.

[Explanation of symbols]

1 ... Si substrate, 2 ... High-concentration N-type impurity diffusion region, 3 ... Element isolation SiO ₂ film, 4 ... Interlayer insulating film, 5 ... Word line,
6 ... Lower electrode, 7 ... Composite insulating film including high dielectric film, 71
... Lower SiO ₂ film 72 ... High dielectric film, 73 ... Upper SiO ₂ film, 74 ... Si
O ₂ film, 8 ... Upper electrode.

Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI Technical display location H01L 27/108 7210-4M H01L 27/10 325 C

Claims (3)

[Claims] 1. A memory upper electrode and a memory lower electrode to which a voltage corresponding to information to be stored is applied, and a high dielectric film laminated between the memory upper electrode and the memory lower electrode. A memory cell capacitor composed of a memory insulating film, an upper electrode for a bypass capacitor and a lower electrode for a bypass capacitor, each of which is connected to either a power supply or a ground, and a stack between the upper electrode and the lower electrode. A bypass capacitor insulating film and a bypass capacitor dielectric film added to the bypass capacitor insulating film, and a power supply bypass capacitor formed on the same semiconductor substrate. The lower electrode for memory is a conductor containing at least polysilicon and is used for the memory. Electrodes and has been formed by the lower electrode and the respective same process memory, the bypass capacitor insulating film and the memory insulating film semiconductor integrated circuit, characterized in that formed in the same step. 2. The semiconductor integrated circuit according to claim 1, wherein the memory insulating film and the bypass capacitor insulating film are composite insulating films. 3. A lower electrode for a memory, which is an electrode made of a conductor film containing at least polysilicon and is connected to the memory cell transistor, and a power source or a power source on a semiconductor substrate on which the memory cell transistor is formed. Forming a bypass capacitor lower electrode connected to one of the grounds; forming an insulating film including a high-dielectric film on the memory lower electrode and the bypass capacitor lower electrode; A step of forming a dielectric film for a bypass capacitor in a region corresponding to the lower electrode for a bypass capacitor in, and an electrode made of a conductive film containing at least polysilicon, the lower electrode for a memory sandwiching the insulating film. Between the memory upper electrode facing the memory cell and the insulating film and the bypass capacitor dielectric film. And a step of forming a bypass capacitor upper electrode facing the bypass capacitor lower electrode and connected to the other of the power supply and the ground, the method for manufacturing a semiconductor integrated circuit.