JPH07106496A - Semiconductor device - Google Patents

Abstract

PURPOSE:To easily increase the number of terminals of a semiconductor device by a method wherein both ends of a second lead terminal part provided with a plurality of lead terminals which are piled up in the thickness direction so as to be insulated electrically are branched and installed so as to correspond to a pitch between electrodes and a pitch at a first lead terminal part. CONSTITUTION:Many lead terminals 26 constituting a first lead terminal part 23 are arranged in a row and in parallel at every piece of a semiconductor element 22, and end parts 27 are extended rectlinearly and arranged nearly uniformly at a pitch E and on nearly the same plane. In addition, two lead terminals 31, 32, for a second lead terminal part 30, which are composed of a conductive material are stacked by sandwiching a double-sided tape, they are bonded in such a way that an interval between end parts on one side coincides nearly with a pitch D between electrodes 25a, 25b, and end parts on the other side are bonded so as to coincide nearly with the pitch E between the lead terminals 26. Since the electrodes 25a, 25b can be connected to the lead terminals 26 without using any metal thin wire, the pitch D between the electrodes and the pitch E between the lead terminals can be set to be narrow.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a large number of leads are formed at a narrow pitch.

[0002]

2. Description of the Related Art For example, the SOP (Small Out) shown in FIG.
line Package) 1 or QFP (Quad Flat P) shown in FIG.
Semiconductor devices such as ackage) 2 are known. In the QFP 2 among these, the semiconductor element 3 is bonded to the island 4 as shown in FIG. 12, and the bump electrode 5 of the semiconductor element is connected to the corresponding lead via the metal thin wire 6 as shown in FIG. It is connected to the base end of the terminal 7. Further, the semiconductor element 3 is sealed in a rectangular resin package 8, and a large number of lead terminals 7 partially project from the four side surfaces of the package 8.

Here, the lead terminal 7 is punched together with the island 4 from a lead frame (not shown). The end of the lead terminal 7 on the side to which the thin metal wire 6 is connected is the inner lead 9, and the tip of the portion protruding from the package 8 is the outer lead 10.

When the semiconductor element 3 is sealed, the lead frame on which the semiconductor element 3 is mounted is loaded into a mold, and a thermosetting resin such as an epoxy resin is supplied to the mold to package the package. The die 8 is transfer molded.

A similar connection structure and sealing method can be applied to the SOP1 shown in FIG.
As represented by QFP2 described above, the number of lead terminals 7 is extremely large in a high-performance semiconductor device. on the other hand,
The semiconductor device is required to be miniaturized for the purpose of increasing the packaging density. In order to achieve both multi-terminals and miniaturization, the lead terminals 7 are being narrowed in pitch.

[0006]

By the way, as the pitch of the lead terminals 7 is made narrower, the width of each inner lead 9 becomes smaller and the connecting space of the fine metal wires 6 becomes narrower. Therefore, the connection space of the inner lead 9 is secured by increasing the inner lead pitch A by increasing the distance between the inner lead 9 and the semiconductor element 3. Along with this, the fine metal wire 6 is made into a long loop (the length of the fine metal wire 6 is increased).

However, if the metal thin wire 6 is made into a long loop,
Since the force exerted by the resin on the metal thin wire 6 during the resin sealing increases, the metal thin wire 6 is easily deformed. When the deformation is excessively large, the thin metal wire 6 may short-circuit with the semiconductor element 3 or the adjacent thin metal wire 6.

Further, since the connection pitch of the fine metal wires 6 is limited, the electrode pitch B and the inner lead pitch A cannot be set smaller than the minimum pitch at which the fine metal wires 6 can be connected. Therefore, the semiconductor element 3 and the package
It is difficult to increase the number of terminals without increasing the area of the gate 8.

Further, in recent years, the degree of integration of semiconductors has been increasing, but since the power consumption increases as the degree of integration increases,
There is an increasing demand for lower thermal resistance of semiconductor devices. An object of the present invention is to provide a semiconductor device that can be easily made multi-terminal.

[0010]

In order to achieve the above object, the invention of claim 1 is a semiconductor device having a large number of electrodes arranged at a predetermined pitch along an edge portion,
The package encapsulating the semiconductor element and one end of the package which is led out from the package and the other end of which is located inside the package close to the outer wall of the package and arranged at a pitch larger than that of the electrodes of the semiconductor element. A first lead portion having a large number of leads, and a second lead electrically connecting the electrode of the semiconductor element and the first lead portion.
The second lead portion has a plurality of leads that are electrically insulated and are stacked in the thickness direction, and both ends have the electrode pitch and the first lead. It is provided so as to branch according to the lead pitch of the lead portion.

According to a sixth aspect of the present invention, a semiconductor element having a large number of electrodes arranged at a predetermined pitch along the edge, a package encapsulating the semiconductor element, and one end A first lead portion having a large number of leads which are led out of the package and whose other end is located in the vicinity of the outer wall of the package and arranged at a pitch larger than the electrodes of the semiconductor element; An insulative internal substrate for supporting the semiconductor element in the package, and a thin film formed on the internal substrate, one end of which is electrically connected to the electrode and the other end of which is radial to the outer edge of the internal substrate. A second lead portion having a plurality of leads extending to the upper end and extending at a pitch larger than the electrode, and a wire connecting the first lead portion and the second lead portion. . And these inventions made it possible to easily make a semiconductor device multi-terminal.

[0012]

Embodiments of the present invention will be described below with reference to FIGS. 1 to 4 show an essential part of a first embodiment of the present invention, in which reference numeral 21 is QFP (Quad Flat P
ackage) type semiconductor device. This semiconductor device 21
Has a semiconductor element 22 and a first lead portion 23. Here, FIG. 1 shows only about 1/4 of the semiconductor device 21, and the other parts are omitted.

Bump electrodes (hereinafter referred to as electrodes) 25 as a large number of electrodes are formed on the element formation surface 24 of the semiconductor element 22.
a, 25b are formed, and these electrodes 25a, 25b
b are staggered in two rows along the edge of the semiconductor element 22. Here, reference numeral D in FIG. 1 indicates electrodes 25a, 25
The pitch of b is shown. An insulating material is coated on the portion other than the electrodes 25a and 25b on the element forming surface 24. The semiconductor element 22 may be mounted on the island.

The first lead portion 23 has a large number of lead terminals 26.
It is composed by. The lead terminals 26 are arranged in a line and in parallel for each piece of the semiconductor element 22. Further, the end portion (inner lead) 27 of the lead terminal 26 on the semiconductor element 22 side extends linearly, and the lead terminal 26
Pitch E is set to be substantially uniform. The ends 27 of the leads 23 are substantially flush with each other.

The end portion 2 of the semiconductor element 22 and the lead terminal 26
7 is sealed by a rectangular package 28, and the lead 23 projects substantially vertically from the four side surfaces 29 (outer wall) of the package 28. That is, the end portion 27 of the lead terminal 26 is located inside the package 28 adjacent to the side surface 29. It is possible to use an epoxy resin as the material of the package 28 and adopt transfer molding as a molding method. In FIG. 1, the package is
The di 26 is schematically indicated by a chain double-dashed line.

Reference numeral 30 in FIG. 1 denotes a plurality of second lead portions. As shown in FIGS. 2 and 3, each second lead portion 30 has two leads 31 and 32 both made of a conductive material and a double-sided tape made of an insulating material.
And 33. The widths of the leads 31 and 32 and the double-sided tape 33 are set to be substantially equal to each other.
2 are laminated with a double-sided tape 33 sandwiched therebetween. Second Lee
The cord portions 30 are radially arranged around the semiconductor element 22. The length of the second lead portion 30 is longer from the center of each piece of the semiconductor device 22 (and the package 28) to both ends.

At both ends of each second lead portion 30, as shown in FIGS. 3 (a) and 4 (a), leads 3 are provided.
1, 32 extend in different directions and are branched. The double-sided tape 33 is not attached to the leads 31 and 32 at the branched portion. Furthermore, both ends of the upper lead 32 are
As shown in FIGS. 3 (b) and 4 (b), it is bent so as to be located at the same height as the end portion of the lower lead 31.

At one end of the second lead portion 30,
The distance between the leads 31 and 32 is substantially equal to the pitch D of the electrodes 25a and 25b, and this portion corresponds to the electrodes 25a and 25b.
Is joined to. The lead 3 at the other end
The interval between 1 and 32 is substantially equal to the pitch E of the lead terminal 26, and this portion is joined to the lead terminal 26.

Here, the leads 31, 32 and the electrodes 25a,
It is possible to employ thermocompression bonding as a method of joining the lead terminals 25b and the lead terminals 26. Further, in this embodiment, the leads 31 and 32 are laminated after molding.

In the semiconductor device 21 as described above,
The electrodes 25a and 25b of the semiconductor element 22 and the first lead portion 2
The three lead terminals 26 are connected via the second lead portion 30. Further, in the second lead section 30, the lead is
The leads 31 and 32 are laminated, and these leads 31 and 3 are provided.
2 is branched and joined to the electrodes 25a and 25b and the lead terminal 26.

Therefore, the electrodes 25a and 25b can be connected to the lead terminal 26 without using a thin metal wire. Therefore, the electrode pitch D and the lead terminal pitch E can be set narrow without being limited by the connection pitch of the thin metal wires. Then, the semiconductor element 22
The number of terminals can be increased without increasing the area of the package 24 and the package 24.

Further, since the loop-shaped thin metal wire is not used, deformation of the thin metal wire is less likely to occur during resin sealing. Therefore, it becomes possible to prevent disconnection and short circuit. Furthermore, since the connection is made without using the thin metal wires, the degree of freedom in arranging the electrodes 25a and 25b is increased. Therefore, the degree of freedom in designing the semiconductor element 22 also increases.

The present invention can be variously modified without departing from the scope of the invention. For example, in the present embodiment, the leads 31 and 32 of the second lead portion 30 are laminated via the double-sided tape 33, but the present invention is not limited to this and, for example, insulation. It is possible to utilize a protective coating. As the insulating film, paints and adhesives made of polymer materials are considered.

Further, in this embodiment, both leads 31, 32 are provided.
Although the end portions of the electrodes are aligned on the same plane, for example, if a height difference is provided between the electrodes 25a and 25b as shown in FIG.
The bending of the cord 32 is unnecessary. In this case, the electrodes 25a, 2
Since 5b can be arranged right next to each other, the pitch of the electrodes can be further narrowed. The amount of height difference is approximately equal to the amount of the thicknesses of the lead 31 and the double-sided tape 33 added together, for example. Although not shown, the adjacent lead terminals 2
6 may be provided with a height difference.

Although the electrodes 25a and 25b are arranged in two rows in this embodiment, the electrodes 25 may be arranged in one row at the same pitch E as in the above-described embodiments, as shown in FIG. 6, for example.

Further, as shown in FIG. 7, the package 4
Alternatively, a heat sink 43 made of a highly heat conductive material such as an aluminum alloy may be inserted. In FIG. 7, a plate-shaped heat sink 43 is joined to a surface 44 of the semiconductor element 22 opposite to the element forming surface 24 via a heat conductive adhesive. The heat dissipation surface 45 is exposed flush with the surface 47 of the package 42. The heat generated in the semiconductor element 22 is transmitted to the heat sink 43,
It is discharged from the tosink 43 to the outside of the package 42. The side surface 46 of the heat sink 43 is undercut, and is inclined while expanding toward the semiconductor element 22 side. The side surface 46 prevents the heat sink 43 from falling off.

According to such a semiconductor device 41, the number of terminals can be increased and the thermal resistance can be reduced. Therefore, this structure is suitable for a semiconductor device including a highly integrated semiconductor element. In addition, the heat sink 43 is installed in the package 4
You may make it project from 2.

The present invention is applicable not only to QFP but also to other various types of semiconductor devices. Next,
A second embodiment of the present invention will be described based on FIGS. 8 and 9.

FIG. 8 shows an essential part of the second embodiment of the present invention partially broken away, and the reference numeral 51 in the drawing denotes a semiconductor device 51. This semiconductor device 51 is a QFP (Quad Flat Packag).
It is of the e) type and has a semiconductor element 52, an internal substrate 53, a rectangular package 54, and a first lead portion 55. The first lead portion 55 has a large number of lead terminals 56 as leads.

Among these, the semiconductor element 52 includes a large number (only two are shown) of bump electrodes (hereinafter referred to as electrodes) 57.
The electrodes 57 are arranged in a line at substantially equal pitches along each of the four sides of the semiconductor element 52.

The internal substrate 53 is made of an insulating material and is processed into a square frame shape. Further, a second lead portion 59 is formed on one plate surface 58 of the internal substrate 53. The second lead portion 59 has a large number of thin film leads 60, and these leads 60 are the internal substrate 53.
Are arranged radially around the through-hole 61. The pitch of the outer end of the lead 60 is wider than the pitch of the inner end.

The semiconductor element 52 is mounted in the center of the internal substrate 53. The semiconductor element 52 is mounted face down on the internal substrate 53, and the electrode 57 of the semiconductor element 52 is thermocompression bonded to the inner end of the lead 60.

The lead terminals 56 are arranged around the internal substrate 53, and are arranged in a line along each side of the internal substrate 53. Further, the inner portion (inner lead) of the lead terminal 56 extends radially with respect to the internal substrate 53,
The outer portion (outer lead) extends substantially perpendicular to each side of the internal substrate 53. The pitch of the outer portion of the lead terminal 56 is wider than the pitch of the inner portion. The inner end of the lead terminal 56 is located at substantially the same height as the internal board 53.

The outer end of the lead 60 of the internal substrate 53 and the inner end of the lead terminal 56 are connected via a bonding wire (metal thin wire) 62 as a wire. The electrode 59 of the semiconductor element 52, the lead 60 of the internal substrate 53, the bonding wire 62, and the lead terminal 56 constitute a signal transmission path.

The package 54 seals the semiconductor element 52, the internal substrate 53, the bonding wires 62, and the inner ends of the lead terminals 56. Further, the outer portions of the lead terminals 56 project substantially vertically from the four side surfaces of the package 54 and in parallel with each other. Epoxy resin or the like can be used as the material of the package 54, and transfer molding can be adopted as the molding method.

A heat sink 63 is incorporated in the package 54. The heat sink 63 is made of a highly heat conductive material such as aluminum alloy, and is processed into a flat plate shape. Further, one plate surface of the heat sink 63 is bonded to the surface of the semiconductor element 52 opposite to the surface bonded to the internal substrate 53.
It is possible to use an adhesive having sufficient heat conductivity for joining the heat sink 63 and the semiconductor element 52.

The other plate surface 64 of the heat sink 63 is exposed flush with the surface 65 of the package 54. Further, the side surface 66 of the heat sink 63 is undercut, and is inclined so as to spread toward the semiconductor element 52 side. The heat sink 63 is inserted when the package 54 is molded. The inclined side surface 66 prevents the heat sink 63 from falling off.

The heat generated in the semiconductor element 52 is transmitted to the heat sink 63, and the exposed plate surface 6 of the heat sink 63.
4 is discharged to the outside of the package 54. In the semiconductor device 51 as described above, the electrode 56 of the semiconductor element 52 is included.
Since the lead 60 of the internal substrate 53 is interposed between the bonding wire 61 and the bonding wire 62, the bonding wire 61
Can be shorter than before. As a result, the bonding wire 62 can be made to have a lower loop, and the bonding wire 62 is less likely to be deformed during sealing. And
The reliability of the semiconductor device 51 is improved.

Further, between the electrode 56 of the semiconductor element 52 and the bonding wire 62, the lead 60 of the internal substrate 53 is provided.
, The pitch of the electrodes 56 of the semiconductor element 52 is smaller than the connection pitch of the bonding wires 62 on the semiconductor element side. That is, the bonding wire 62
The pitch of the electrodes 56 can be narrowed without being limited to the minimum connectable pitch of. Then, the semiconductor device 51 can have a narrow pitch and a large number of terminals. In addition, since the bonding wires 62 are connected to the outer ends of the radially extending leads 60, the connection pitch is widened and wire bonding is facilitated.

Further, since the heat sink 63 is provided, it is possible to reduce the pitch and the number of terminals, and it is possible to reduce the thermal resistance. Therefore, high integration of the semiconductor element becomes possible. Further, in manufacturing the semiconductor device 51 of the present embodiment, general techniques such as thermocompression bonding, wire bonding, and transfer molding can be applied. Therefore, there is no need to make new capital investment or technological development.

The present invention can be variously modified without departing from the scope of the invention. For example, although the QFP is given as an example in the present embodiment, it can be applied to various general semiconductor devices other than this. Further, the heat sink 63 may be omitted if necessary.

[0042]

As described above, the invention of claim 1 is
A semiconductor element having a large number of electrodes arranged at a predetermined pitch along the edge, a package encapsulating the semiconductor element, one end of which is led out of the package and the other end of which is the package. A first lead portion having a large number of leads located inside the outer wall of the semiconductor element and arranged at a pitch larger than that of the electrodes of the semiconductor element; an electrode of the semiconductor element and a first lead portion; A second lead portion for electrically connecting to each other, and the second lead portion has a plurality of leads that are electrically insulated and are stacked in the thickness direction, and both ends thereof. Corresponding to the pitch of the electrodes and the pitch of the leads of the first lead portion.

According to a sixth aspect of the invention, a semiconductor element having a large number of electrodes arranged at a predetermined pitch along the edge, a package encapsulating the semiconductor element, and one end A first lead portion having a large number of leads which are led out of the package and whose other end is located in the vicinity of the outer wall of the package and arranged at a pitch larger than the electrodes of the semiconductor element; An insulative internal substrate for supporting the semiconductor element in the package, and a thin film formed on the internal substrate, one end of which is electrically connected to the electrode and the other end of which is radial to the outer edge of the internal substrate. A second lead portion having a plurality of leads extending to the upper end and extending at a pitch larger than the electrode, and a wire connecting the first lead portion and the second lead portion. . Further, according to these inventions, there is an effect that the semiconductor device can be easily multi-terminaled.

[Brief description of drawings]

FIG. 1 is a plan view showing a semiconductor device of a first embodiment of the present invention with a part thereof omitted.

FIG. 2 is an enlarged side view showing a connection state between a second lead portion and a semiconductor element.

3 (a) is an enlarged view of a portion surrounded by a circle IV in FIG. 1,
(B) is an arrow view of the direction shown by arrow V in (a).

4 (a) is an enlarged view of a portion surrounded by a circle VI in FIG. 1,
7B is a view in the direction of the arrow VII in FIG.

5A and 5B show a modified example, in which FIG. 5A is a plan view and FIG.
Is a side view.

FIG. 6 is a plan view showing another modification.

FIG. 7 is a side sectional view showing another modification.

FIG. 8 is a side sectional view showing a main part of a semiconductor device according to a second embodiment of the present invention.

FIG. 9 is a plan view showing a semiconductor device according to a second embodiment of the present invention with a part thereof omitted.

FIG. 10 is a perspective view showing a general SOP.

FIG. 11 is a perspective view showing a general QFP.

FIG. 12 is a plan view showing a general QFP with a part thereof omitted.

FIG. 13 is a side view showing a connection state between a lead of a QFP and a semiconductor element with a part thereof omitted.

[Explanation of symbols]

21 ... Semiconductor device, 22 ... Semiconductor element, 23 ... First reel
Lead portion, 26 ... Lead terminal (lead), 25a, 25b ...
Bump electrode (electrode), 28 ... package, 30 ... second lead portion, 31, 32 ... lead, 41 ... semiconductor device, 43
... heat sink, 51 ... semiconductor device, 52 ... semiconductor element, 53 ... internal substrate, 54 ... package, 55 ... first lead portion, 56 ... lead terminal, 57 ... bump electrode (electrode), 59 ... Second lead section, 60 ... Lead, 62 ... Wire, 63 ... Heat sink.

Claims (7)

[Claims] 1. A semiconductor element having a large number of electrodes arranged at a predetermined pitch along an edge, a package encapsulating the semiconductor element, and one end of which is led out from the package. A first lead portion having a large number of leads, the other end portion of which is located in the vicinity of the outer wall of the package and is arranged at a pitch larger than the electrodes of the semiconductor element; A second lead portion electrically connecting the electrode and the first lead portion, wherein the second lead portion is a plurality of electrically insulated layers stacked in the thickness direction. With a lead of
Further, the semiconductor device is characterized in that both ends are provided so as to be branched corresponding to the pitch of the electrodes and the pitch of the leads of the first lead portion. 2. The semiconductor device according to claim 1, wherein the electrodes are arranged in a plurality of rows. 3. The semiconductor device according to claim 2, wherein the leads branched at the end of the second lead portion on the side of the semiconductor element are arranged on the same plane. 4. The leads branched at the end of the second lead portion on the semiconductor element side have a height difference, and the electrodes have a height difference according to the lead for each row. The semiconductor device according to claim 2, wherein the semiconductor device is a semiconductor device. 5. The semiconductor device according to claim 4, wherein the height difference of the electrodes is formed by bumps. 6. A semiconductor element having a large number of electrodes arranged along an edge portion at a predetermined pitch, a package encapsulating the semiconductor element, and one end of which is led out from the package. A first lead portion having a large number of leads arranged inside the other end portion of the package close to the outer wall of the package and having a pitch larger than the electrodes of the semiconductor element; and the package. An insulating internal substrate for supporting the semiconductor element therein, a thin film formed on the internal substrate, one end of which is electrically connected to the electrode, and the other end of which is radial to the outer edge of the internal substrate. A second lead portion having a plurality of leads extending to the first electrode portion and extending at a pitch larger than that of the electrode; and a wire connecting the first lead portion and the second lead portion. A semiconductor device comprising: 7. A heat sink incorporated in a package and joined to a semiconductor element so as to be able to transfer heat, and a heat sink exposed from the package.
Alternatively, the semiconductor device according to claim 6.