JPH07106495A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH07106495A
JPH07106495A JP24703293A JP24703293A JPH07106495A JP H07106495 A JPH07106495 A JP H07106495A JP 24703293 A JP24703293 A JP 24703293A JP 24703293 A JP24703293 A JP 24703293A JP H07106495 A JPH07106495 A JP H07106495A
Authority
JP
Japan
Prior art keywords
semiconductor element
semiconductor device
sheet
package
lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP24703293A
Other languages
Japanese (ja)
Inventor
Satoshi Honda
智 本田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP24703293A priority Critical patent/JPH07106495A/en
Publication of JPH07106495A publication Critical patent/JPH07106495A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

Abstract

PURPOSE:To make a semiconductor device thin by a method wherein a semiconductor element is mounted on, and attached to, an insulating sheet and an electrode is connected electrically to a lead terminal by using an auxiliary lead terminal. CONSTITUTION:A semiconductor element 12 is mounted on, and attached to, according to a facedown system, the center of a sheet face 17 on one side of a wiring sheet 16 composed of an insulating material. In addition, many auxiliary lead terminals 18 formed of a conductive thin film are formed radially on the sheet face 17 on one side of the wiring sheet 16, end parts on one side come into contact with bump electrodes for the semiconductor element 12, and end parts on the other side come into contact with base end parts of lead terminals 14. In addition, base end parts of the lead terminals 18 are sealed with a package 13 together with the semiconductor element 12 and the wiring sheet 16, and other parts of the leads protrude nearly vertically from the package 13 and molded to be a gull wing shape. Metal thin wires can be omitted, and a semiconductor device can be made thin without lowering the mechanical strength of the lead terminals for the semiconductor element.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は、例えば、ＱＦＰ(Quad
Flat Package) やＤＩＰ(Dual InlinePackage) 等のよ
うに、パッケ−ジからリ−ドを突出させた半導体装置に
関する。BACKGROUND OF THE INVENTION The present invention is, for example, a QFP (Quad
The present invention relates to a semiconductor device such as a Flat Package) or a DIP (Dual Inline Package) in which a lead is projected from a package.

【０００２】[0002]

【従来の技術】例えば、図９及び図１０に示すような半
導体装置１が知られている。この半導体装置１において
は、半導体素子２がアイランド３に接着されており、半
導体素子２に形成された多数のバンプ電極４と各バンプ
電極４に対応したリ−ド端子５とが、金属細線６によっ
て接続されている。アイランド３とリ−ド端子５とは共
通のリ−ドフレ−ムから打抜かれており、打抜きに伴っ
て図中に示すように互いに分離される。そして、半導体
素子２、アイランド３、金属細線６、及び、リ−ド端子
５の一部が、合成樹脂製のパッケ−ジ７によって封止さ
れている。2. Description of the Related Art For example, a semiconductor device 1 as shown in FIGS. 9 and 10 is known. In this semiconductor device 1, a semiconductor element 2 is bonded to an island 3, and a large number of bump electrodes 4 formed on the semiconductor element 2 and a lead terminal 5 corresponding to each bump electrode 4 are connected to a thin metal wire 6. Connected by. The island 3 and the lead terminal 5 are punched from a common lead frame, and are separated from each other as shown in the drawing along with the punching. Then, the semiconductor element 2, the island 3, the thin metal wire 6, and part of the lead terminal 5 are sealed by a package 7 made of synthetic resin.

【０００３】一般に、電子機器や情報機器等には小型化
が要求されており、これらの小型化のための一つの手段
として、使用される半導体装置１の薄型化が有効であ
る。そして、従来は半導体装置１の薄型化のための手段
として、半導体素子２、アイランド３、及び、リ−ド端
子５を薄くすること、更に、パッケ−ジ７を薄肉化する
こと等が行われている。ここで、パッケ−ジ７の薄肉化
とは、パッケ−ジ７の薄型化とは異なり、半導体素子２
或いはアイランド３の周りを覆った樹脂の肉厚を薄くす
ることを意味している。Generally, electronic devices and information devices are required to be miniaturized, and as one means for miniaturizing these, it is effective to thin the semiconductor device 1 used. Conventionally, as means for reducing the thickness of the semiconductor device 1, thinning the semiconductor element 2, the island 3, and the lead terminal 5, and further reducing the thickness of the package 7 have been performed. ing. Here, the thinning of the package 7 is different from the thinning of the package 7, and the semiconductor element 2
Alternatively, it means that the thickness of the resin covering the island 3 is reduced.

【０００４】[0004]

【発明が解決しようとする課題】ところで、半導体装置
１の薄型化を図るための従来の技術には以下の各項のよ
うな不具合がある。 (1) 半導体素子２を薄くした場合、半導体素子２の機械
的強度が低下し、半導体装置の信頼性試験時に発生する
熱応力を原因として、半導体素子２にクラックが生じる
ことがある。 (2) アイランド３及びリ−ド端子５を薄くした場合、こ
れらの機械的強度が低下し、樹脂封止の際に、流動する
樹脂の圧力を原因として、アイランド３やリ−ド端子５
が変形することがある。また、アイランド３やリ−ド端
子５の変形を原因として、金属細線６が変形或いは断線
することがある。 (3) パッケ−ジ７の薄肉化した場合、樹脂封止の際に、
樹脂が流れにくくなり、充填不良が発生することがあ
る。また、金属細線６に加わる圧力が大となり、金属細
線６が変形或いは断線し易くなる。 (4) パッケ−ジ７には半導体素子２、アイランド３、及
び、金属細線６が封止されるため、パッケ−ジ７の厚さ
は、これらの厚さ（及び高さ）によって制限される。つ
まり、パッケ−ジ７の薄肉化を進めても、パッケ−ジ７
の厚さをこれらの和よりも小さくすることはできない。 本発明の目的とするところは、薄型化が可能な半導体装
置を提供することにある。By the way, the conventional techniques for reducing the thickness of the semiconductor device 1 have the following problems. (1) When the semiconductor element 2 is made thin, the mechanical strength of the semiconductor element 2 is lowered, and cracks may occur in the semiconductor element 2 due to thermal stress generated during a reliability test of the semiconductor device. (2) When the island 3 and the lead terminal 5 are thinned, the mechanical strength of the island 3 and the lead terminal 5 is deteriorated, and the pressure of the flowing resin causes the island 3 and the lead terminal 5 during resin sealing.
May be deformed. Further, the metal thin wire 6 may be deformed or broken due to the deformation of the island 3 and the lead terminal 5. (3) When the package 7 is thinned, when it is sealed with resin,
The resin becomes difficult to flow, and filling failure may occur. Further, the pressure applied to the thin metal wire 6 becomes large, and the thin metal wire 6 is easily deformed or broken. (4) Since the semiconductor element 2, the island 3, and the thin metal wire 6 are sealed in the package 7, the thickness of the package 7 is limited by these thicknesses (and heights). . In other words, even if the thickness of the package 7 is reduced, the package 7
Cannot be less than the sum of these. An object of the present invention is to provide a semiconductor device that can be thinned.

【０００５】[0005]

【課題を解決するための手段および作用】上記目的を達
成するために本発明は、半導体素子と、この半導体素子
を封止したパッケ−ジと、半導体素子の周囲に配設され
パッケ−ジから突出したリ−ド端子と、半導体素子を電
気的に絶縁して支持するシ−ト体と、このシ−ト体に形
成され半導体素子の電極とリ−ド端子とを電気的に接続
する補助リ−ドとを具備したことにある。In order to achieve the above object, the present invention comprises a semiconductor device, a package encapsulating the semiconductor device, and a package arranged around the semiconductor device. A protruding lead terminal, a sheet body for electrically insulating and supporting the semiconductor element, and an auxiliary for electrically connecting the electrode of the semiconductor element and the lead terminal formed on the sheet body. It is equipped with a lead.

【０００６】こうすることによって本発明は、金属細線
を省略し、半導体素子やリ−ド端子の機械的強度を低下
させることなく、半導体装置を薄型化できるようにした
ことにある。In this way, the present invention aims at omitting the thin metal wires and making it possible to reduce the thickness of the semiconductor device without lowering the mechanical strength of the semiconductor element and the lead terminal.

【０００７】[0007]

【実施例】以下、本発明の各実施例を図１〜図８に基づ
いて説明する。図１は本発明の第１実施例を示すもの
で、図中の符号１１はＱＦＰ(Quad FlatPackage) 型の
半導体装置である。この半導体装置１１は、半導体素子
１２、矩形なパッケ−ジ１３、及び、多数のリ−ド端子
（以下、リ−ドと称する）１４を有している。これらの
うち半導体素子１２は、図３中に一部を示すように、多
数のバンプ電極（以下、電極と称する）１５を有してお
り、電極１５は半導体素子１２の四つの辺のそれぞれに
沿って略等ピッチで一列に並んでいる。ここで、電極１
５の作製のために、一般的な種々の技術を利用すること
が可能である。Embodiments of the present invention will be described below with reference to FIGS. FIG. 1 shows a first embodiment of the present invention. Reference numeral 11 in the drawing is a QFP (Quad Flat Package) type semiconductor device. This semiconductor device 11 has a semiconductor element 12, a rectangular package 13, and a large number of lead terminals (hereinafter referred to as leads) 14. Of these, the semiconductor element 12 has a large number of bump electrodes (hereinafter referred to as electrodes) 15, as shown in part in FIG. 3, and the electrodes 15 are provided on each of the four sides of the semiconductor element 12. They are lined up in a row at a substantially equal pitch. Where electrode 1
Various general techniques can be used for the production of 5.

【０００８】また、図１中に符号１６で示すのはシ−ト
体としての配線シ−トである。この配線シ−ト１６は絶
縁性材料からなるもので、正方形状に加工されている。
さらに、配線シ−ト１６の一方のシ−ト面１７の中央に
は半導体素子１１が接着されている。半導体素子１１は
配線シ−ト１６にフェイスダウン式に装着されており、
電極１５や回路パタ−ンが形成された素子形成面を配線
シ−ト１６に向けている。Further, reference numeral 16 in FIG. 1 denotes a wiring sheet as a sheet body. The wiring sheet 16 is made of an insulating material and is processed into a square shape.
Further, the semiconductor element 11 is bonded to the center of one sheet surface 17 of the wiring sheet 16. The semiconductor element 11 is mounted on the wiring sheet 16 in a face-down manner.
The element forming surface on which the electrodes 15 and the circuit patterns are formed faces the wiring sheet 16.

【０００９】図１、図３、及び、図４中に示すように、
配線シ−ト１６の一方のシ−ト面１７には多数の補助リ
−ド１８が放射状に形成されている。各補助リ−ド１８
は導電性の材質からなる薄膜であり、略一定の幅の直線
状に加工されている。さらに、補助リ−ド１８は配線シ
−ト１６の縁部に沿って配設されており、補助リ−ド１
８の一端部は、半導体素子１１の電極１５に接触してい
る。また、補助リ−ド１８の他端部は互いの間隔を拡げ
ながら配線シ−ト１６の外側に向っている。つまり、補
助リ−ド１８の外側の端部のピッチは、内側の端部のピ
ッチに比べて大きく設定されている。As shown in FIGS. 1, 3 and 4,
A large number of auxiliary leads 18 are radially formed on one sheet surface 17 of the wiring sheet 16. Each auxiliary lead 18
Is a thin film made of a conductive material and is processed into a linear shape having a substantially constant width. Further, the auxiliary lead 18 is arranged along the edge of the wiring sheet 16, and the auxiliary lead 1
One end of 8 is in contact with the electrode 15 of the semiconductor element 11. Further, the other ends of the auxiliary leads 18 are directed toward the outside of the wiring sheet 16 while expanding the distance between them. That is, the pitch of the outer end of the auxiliary lead 18 is set larger than the pitch of the inner end.

【００１０】前記リ−ド１４は、半導体素子１２の周囲
に配設されており、半導体素子１２の各辺毎に略等ピッ
チで一列に並んでいる。さらに、リ−ド１４の基端部
（半導体素子１１側の端部）は配線シ−ト１６のシ−ト
面１７に重なっており、補助リ−ド１８に接触してい
る。さらに、リ−ド１８の基端部は、半導体素子１１及
び配線シ−ト１６とともにパッケ−ジ１３によって封止
されている。また、リ−ド１４のその他の部分は、リ−
ド１４はパッケ−ジ１３から略垂直に突出するととも
に、ガルウイング型に成形されている。The leads 14 are arranged around the semiconductor element 12, and are arranged in a line on each side of the semiconductor element 12 at a substantially equal pitch. Further, the base end portion of the lead 14 (end portion on the semiconductor element 11 side) overlaps the sheet surface 17 of the wiring sheet 16 and is in contact with the auxiliary lead 18. Further, the base end portion of the lead 18 is sealed by the package 13 together with the semiconductor element 11 and the wiring sheet 16. The other parts of the lead 14 are
The door 14 projects substantially vertically from the package 13 and is formed into a gull wing type.

【００１１】つぎに、上述の半導体装置１１の製造方法
を図５に基づいて説明する。まず、ポリイミド等の材質
からなるテ−プに補助リ−ド１８を形成し、配線シ−ト
１６を得る。補助リ−ド１８の材質としてはＣｕやＡｌ
を採用できる。さらに、補助リ−ド１８の形成方法とし
て接着やめっき、或いは、エッチング等が考えられる。
また、配線シ−ト１６を同時に多数個取りしてもよい。Next, a method of manufacturing the above semiconductor device 11 will be described with reference to FIG. First, the auxiliary lead 18 is formed on the tape made of a material such as polyimide to obtain the wiring sheet 16. The material of the auxiliary lead 18 is Cu or Al
Can be adopted. Further, as a method of forming the auxiliary lead 18, adhesion, plating, etching or the like can be considered.
Further, a large number of wiring sheets 16 may be taken at the same time.

【００１２】つぎに、配線シ−ト１６をリ−ド１４に接
着する。この際、配線シ−ト１６とリ−ド１４とは、補
助リ−ド１８がリ−ド１４に接触するように位置合せさ
れる。さらに、半導体素子１２を、電極１５と補助リ−
ド１８とを位置合せして、配線シ−ト１６に接着する。
この後、半導体素子１２、配線シ−ト１６、及び、リ−
ド１４の基端部を、エポキシ樹脂等を用いて封止する。Next, the wiring sheet 16 is bonded to the lead 14. At this time, the wiring sheet 16 and the lead 14 are aligned so that the auxiliary lead 18 contacts the lead 14. Further, the semiconductor element 12 is connected to the electrode 15 and the auxiliary lead.
The wiring sheet 16 is aligned and bonded to the wiring sheet 16.
After this, the semiconductor element 12, the wiring sheet 16, and the lead
The base end of the cord 14 is sealed with epoxy resin or the like.

【００１３】上述のような半導体装置１１においては、
補助リ−ド１８が形成された配線シ−ト１６が備えられ
ているので、ボンディングワイヤを用いることなく、半
導体素子１２の電極１５とリ−ド１４とを接続すること
ができる。したがって、ボンディングワイヤのル−プの
高さによって制限されることなく、半導体装置１１を薄
型化することが可能になる。In the semiconductor device 11 as described above,
Since the wiring sheet 16 in which the auxiliary lead 18 is formed is provided, the electrode 15 of the semiconductor element 12 and the lead 14 can be connected without using a bonding wire. Therefore, the semiconductor device 11 can be thinned without being limited by the height of the loop of the bonding wire.

【００１４】また、ボンディングワイヤやアイランドを
省略して半導体装置１１を薄型化できるので、半導体素
子１２やリ−ド１４の厚さを薄く設定する必要がない。
したがって、半導体素子１１やリ−ド１４の機械的強度
を低下させずに済む。Further, since the semiconductor device 11 can be made thin by omitting the bonding wires and islands, it is not necessary to set the thickness of the semiconductor element 12 and the lead 14 to be thin.
Therefore, it is not necessary to reduce the mechanical strength of the semiconductor element 11 and the lead 14.

【００１５】さらに、ボンディングワイヤが不要である
ので、封止の際のボンディングワイヤの変形や断線の心
配がなくなり、半導体装置１１の信頼性が向上する。な
お、本発明は、要旨を逸脱しない範囲で種々に変形する
ことが可能である。Further, since the bonding wire is not required, there is no fear of deformation or disconnection of the bonding wire at the time of sealing, and the reliability of the semiconductor device 11 is improved. The present invention can be variously modified without departing from the spirit of the invention.

【００１６】例えば、本実施例では、配線シ−ト１６が
リ−ド１４に接着されたのちに、半導体素子１２が配線
シ−ト１６に接着されるが、この順番を逆に替えてもよ
く、また、半導体素子１２とリ−ド１４とを同時に配線
シ−ト１６に接着してもよい。 また、配線シ−ト１６
が粘着テ−プであってもよい。For example, in the present embodiment, the semiconductor element 12 is adhered to the wiring sheet 16 after the wiring sheet 16 is adhered to the lead 14, but the order may be reversed. Alternatively, the semiconductor element 12 and the lead 14 may be bonded to the wiring sheet 16 at the same time. Also, the wiring sheet 16
May be an adhesive tape.

【００１７】さらに、本実施例では、配線シ−ト１６の
材質が絶縁性材料であるが、本発明はこれに限定される
ものではなく、例えば図６に示すように、配線シ−ト２
１に導電性の材質を用い、絶縁膜２２を介して、補助リ
−ド１８を形成してもよい。Further, in the present embodiment, the material of the wiring sheet 16 is an insulating material, but the present invention is not limited to this. For example, as shown in FIG.
The auxiliary lead 18 may be formed by using a conductive material for the first layer and the insulating film 22.

【００１８】つぎに、本発明の第２実施例を図７及び図
８に基づいて説明する。なお、第１実施例と同様の部分
については同一番号を付し、その説明は省略する。図７
において、符号３２は配線シ−トを示しており、この配
線シ−ト３２の、半導体素子１２が接着されたシ−ト面
１７に対して逆側のシ−ト面３３が、パッケ−ジ１３の
表面３４から面一に露出している。配線シ−ト３２の側
面には断差３５が形成されており、配線シ−ト３２は側
面の断差３５をパッケ−ジ１３に係止させている。Next, a second embodiment of the present invention will be described with reference to FIGS. 7 and 8. The same parts as those in the first embodiment are designated by the same reference numerals and the description thereof will be omitted. Figure 7
In the figure, reference numeral 32 indicates a wiring sheet, and a sheet surface 33 of the wiring sheet 32 opposite to the sheet surface 17 to which the semiconductor element 12 is adhered is packaged. It is exposed flush with the surface 34 of 13. A gap 35 is formed on the side surface of the wiring sheet 32, and the wiring sheet 32 locks the gap 35 on the side surface to the package 13.

【００１９】配線シ−ト３２の材質は充分な放熱性を有
する金属であり、配線シ−ト３２の半導体素子１２側の
シ−ト面１７には、図８中に示すように絶縁膜３６が形
成されている。そして、この絶縁膜３６の上に補助リ−
ド１８が形成されている。The material of the wiring sheet 32 is a metal having sufficient heat dissipation, and the insulating sheet 36 is formed on the sheet surface 17 of the wiring sheet 32 on the semiconductor element 12 side as shown in FIG. Are formed. Then, an auxiliary reel is formed on the insulating film 36.
Do 18 is formed.

【００２０】半導体素子１２に発生した熱は、配線シ−
ト３２に伝わり、配線シ−ト３２の露出したシ−ト面３
３から外気中に放出される。つまり、本実施例において
は、配線シ−ト３２が放熱板を兼ねており、配線シ−ト
３２を利用して熱抵抗が軽減されている。The heat generated in the semiconductor element 12 is applied to the wiring sheet.
Exposed sheet surface 3 of the wiring sheet 32.
It is released from 3 into the outside air. That is, in this embodiment, the wiring sheet 32 also serves as a heat dissipation plate, and the thermal resistance is reduced by using the wiring sheet 32.

【００２１】このような半導体装置３１においては、第
１実施例と同様な効果を奏することができ上に、熱抵抗
を軽減することが可能になる。なお、配線シ−ト３２を
パッケ−ジ１３の表面３４から突出させてもよい。In such a semiconductor device 31, the same effects as those of the first embodiment can be obtained, and the thermal resistance can be reduced. The wiring sheet 32 may be projected from the surface 34 of the package 13.

【００２２】[0022]

【発明の効果】以上説明したように本発明は、半導体素
子と、この半導体素子を封止したパッケ−ジと、半導体
素子の周囲に配設されパッケ−ジから突出したリ−ド端
子と、半導体素子を電気的に絶縁して支持するシ−ト体
と、このシ−ト体に形成され半導体素子の電極とリ−ド
端子とを電気的に接続する補助リ−ドとを具備したもの
である。したがって本発明は、半導体装置を容易に薄型
化できるという効果がある。As described above, according to the present invention, a semiconductor element, a package encapsulating the semiconductor element, a lead terminal disposed around the semiconductor element and protruding from the package, A sheet body which electrically insulates and supports a semiconductor element, and an auxiliary lead which is formed on the sheet body and electrically connects the electrode of the semiconductor element and a lead terminal Is. Therefore, the present invention has an effect that the semiconductor device can be easily thinned.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明の第１実施例の半導体装置を一部省略し
て示す平面図。FIG. 1 is a plan view showing a semiconductor device of a first embodiment of the present invention with a part thereof omitted.

【図２】本発明の第１実施例の半導体装置を一部省略し
て示す側断面図。FIG. 2 is a side sectional view showing the semiconductor device according to the first embodiment of the present invention with a part thereof omitted.

【図３】図１中の円IVで囲った部分の拡大図。FIG. 3 is an enlarged view of a portion surrounded by a circle IV in FIG.

【図４】図３中のＶ−Ｖ線に沿った断面図。FIG. 4 is a sectional view taken along line VV in FIG.

【図５】本発明の第１実施例の半導体装置の製造方法を
示す工程図。FIG. 5 is a process drawing showing the method of manufacturing the semiconductor device according to the first embodiment of the present invention.

【図６】第１実施例の変形例を示す説明図。FIG. 6 is an explanatory diagram showing a modification of the first embodiment.

【図７】本発明の第２実施例の半導体装置を一部省略し
て示す側面図。FIG. 7 is a side view showing a semiconductor device according to a second embodiment of the present invention with a part thereof omitted.

【図８】図７中に円VIで囲った部分の拡大図。FIG. 8 is an enlarged view of a portion surrounded by a circle VI in FIG. 7.

【図９】一般の半導体装置を一部省略して示す平面図。FIG. 9 is a plan view showing a general semiconductor device with a part thereof omitted.

【図１０】一般の半導体装置を一部省略して示す側面
図。FIG. 10 is a side view showing a general semiconductor device with a part thereof omitted.

【符号の説明】[Explanation of symbols]

１１…半導体装置、１２…半導体素子、１３…パッケ−
ジ、１４…リ−ド端子、１５…バンプ電極（電極）、１
６…配線シ−ト（シ−ト体）、１７…シ−ト面、３１…
半導体装置、３３…シ−ト面。11 ... Semiconductor device, 12 ... Semiconductor element, 13 ... Package
J, 14 ... Lead terminal, 15 ... Bump electrode (electrode), 1
6 ... Wiring sheet (sheet body), 17 ... Sheet surface, 31 ...
Semiconductor device, 33 ... Sheet surface.

Claims (5)

【特許請求の範囲】[Claims] 【請求項１】 半導体素子と、この半導体素子を封止し
たパッケ−ジと、上記半導体素子の周囲に配設され上記
パッケ−ジから突出したリ−ド端子と、上記半導体素子
を電気的に絶縁して支持するシ−ト体と、このシ−ト体
に形成され上記半導体素子の電極と上記リ−ド端子とを
電気的に接続する補助リ−ドとを具備することを特徴と
する半導体装置。1. A semiconductor element, a package encapsulating the semiconductor element, a lead terminal disposed around the semiconductor element and protruding from the package, and the semiconductor element electrically connected to each other. It is characterized by comprising a sheet body which is insulated and supported, and an auxiliary lead which is formed on the sheet body and electrically connects the electrode of the semiconductor element and the lead terminal. Semiconductor device. 【請求項２】 補助リ−ドが薄膜であることを特徴とす
る上記請求項１記載の半導体装置。2. The semiconductor device according to claim 1, wherein the auxiliary lead is a thin film. 【請求項３】 半導体素子の電極がバンプ電極であるこ
とを特徴とする上記請求項１記載の半導体装置。3. The semiconductor device according to claim 1, wherein the electrode of the semiconductor element is a bump electrode. 【請求項４】 シ−ト体の一方のシ−ト面に半導体素子
が接合され、他方のシ−ト面がパッケ−ジから露出して
いることを特徴とする上記請求項１記載の半導体装置。4. The semiconductor device according to claim 1, wherein the semiconductor element is bonded to one of the sheet surfaces of the sheet body, and the other sheet surface is exposed from the package. apparatus. 【請求項５】 シ−ト体が金属材料からなる放熱板から
なり絶縁膜を介して半導体素子を支持することを特徴と
する上記請求項４記載の半導体装置。5. The semiconductor device according to claim 4, wherein the sheet body is a heat dissipation plate made of a metal material and supports the semiconductor element through an insulating film.
JP24703293A 1993-10-01 1993-10-01 Semiconductor device Pending JPH07106495A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24703293A JPH07106495A (en) 1993-10-01 1993-10-01 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24703293A JPH07106495A (en) 1993-10-01 1993-10-01 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH07106495A true JPH07106495A (en) 1995-04-21

Family

ID=17157401

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24703293A Pending JPH07106495A (en) 1993-10-01 1993-10-01 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH07106495A (en)

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