JPH07105770B2 - Digital drop adder - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital add / drop device capable of adding / dropping arbitrary channel information in a PCM signal and digitally adding the same, and particularly to failure processing when an input signal becomes a failure. The present invention relates to a digital add / drop multiplexer having a function.

[Conventional technology]

When the conventional digital add / drop multiplexer detects an input signal failure of the device such as input PCM signal loss or loss of synchronization, it judges that the PCM signal is unusable and the input signal is uniquely AIS regardless of the mode used. It was replaced with a fixed pattern represented by (Alarm Indication Signal).

[Problems to be solved by the invention]

The above-described conventional digital add / drop multiplexer is configured to uniquely replace the input signal with a fixed pattern typified by AIS when an input signal failure occurs.
Usage mode of channel information in a signal, for example, a voice signal, a data signal, which are transmitted on a transmission line and have a different code form
Depending on the various modes of the exchange signal, there is a drawback that communication using digital addition cannot be performed between the device that has detected the failure and the same digital add / drop multiplexer that is connected in a chain.

It is an object of the present invention to provide a digital add / drop multiplexer that eliminates such drawbacks.

[Means for solving problems]

The present invention establishes frame synchronization and multi-frame synchronization for an input PCM signal, and at the same time, performs synchronization / fault detection means for performing fault monitoring, and the input PC based on the fault information of the synchronization / fault detection means.
Failure determination means for determining the unavailability of the M signal, a timing counter that operates in synchronization with the input PCM signal with the information that synchronization has been established by the synchronization / failure detection means, and channel information of the input PCM signal in advance Is a voice signal, a data signal, or a switch signal, and stores the use mode setting means for storing the use mode, and the use mode is set at a position corresponding to the time slot sequence of the input PCM signal by the output of the timing counter. Fixed pattern generating means for generating a fixed pattern corresponding to the mode set by the setting means, and switching between the output of the synchronization / failure detecting means and the output of the fixed pattern generating means based on the output of the failure determining means, No. 1 selecting means, and add / drop means for branching the PCM signal from the first selecting means and inserting a new PCM signal from the outside , A selection signal generating means for generating a selection signal for selecting one of a sum of voice signals, a sum of data signals, and a sum of exchange signals according to a usage mode of channel information, and a selection signal from the selection signal generating means, First
PCM signal from the selecting means and the PCM signal from the add / drop means
A digital addition means for summing signals, a PCM signal from the first selection means, a PCM signal from the add / drop means, or a signal from the digital addition means obtained by summing the time slots It is characterized in that it is provided with a second selecting means for selecting each.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings. In the following description, the primary group PCM signal of 2048 kbit / s system is targeted, but the effectiveness of the present invention is not limited to this.

FIG. 3 is a diagram showing a 2048 kbit / s system primary group PCM multiplexed frame structure. One frame is composed of 32 time slots (one time slot is composed of 8 bits), time slot 0 is a frame synchronization information time slot, and time slots 1 to 15 and 17 to 31 are voice signals or data signals. Is assigned as a time slot for the channel information of. Time slot for each frame
16 is used to carry switch signaling information corresponding to voice signals. Such PCM multiplex frames are 16 frames, and one multiframe is configured.

The digital add / drop multiplexer arbitrarily drops and adds these channel information, and digitally adds the arbitrary channel information in the PCM signals of the two systems.

FIG. 4 is a diagram showing an embodiment of the digital add / drop multiplexer of the present invention. This digital add / drop multiplexer has a PCM
There are three systems for signal input / output. In the figure, signals S11 and S41 are main transmission line (A direction) PCM input / output signals, signals S31 and S21 are main transmission line (B direction) PCM input / output signals, and signals S51 and S61 are This is a PCM input / output signal for the add / drop path (C direction). In the figure 1,3,5 are A,
The receiving units that process the input PCM signals in the B and C directions have the same configuration, and the reference numbers 2, 4, and 6 are the transmitting units that process the transmission PCM signals. In addition, 7,8,9,10 in the figure
Is a time slot rearrangement circuit for converting to the position of the desired time slot number on the time slot sequence in the branch direction. Further, 11, 21, 31, 41, 51, 61 respectively indicate terminals.

The A-direction input PCM signal passes through the receiving unit 1, one to the B-direction transmitting unit 2, and the other through the time slot rearrangement circuit 7 to C.
It is sent to the direction transmission unit 6. Similarly, the B-direction input PCM signal is sent to the A-direction transmitting unit 4 via the receiving unit 3 and the other to the C-direction transmitting unit 6 via the time slot rearrangement circuit 8. The C direction input PCM signal passes through the receiving unit 5, the time slot rearranging circuits 9 and 10 in the A direction and the B direction, and then to the transmitting units 4,
Sent to 2. Here, the time slot rearrangement circuit 7,8,
9 and 10 can be configured using a RAM (Random Access Memory) or the like, but since they are not directly related to the content of the present invention, detailed description thereof will be omitted.

FIG. 1 is a diagram showing a configuration of a receiving unit and a transmitting unit of the present embodiment. In order to explain the flow of an output PCM signal in the B direction as an example, FIG. ing. The flow of the PCM signal in the B direction will be described below,
The same can be considered for the A direction and the C direction.

In FIG. 1, the receiving unit 1 establishes frame synchronization and multi-frame synchronization, and at the same time, performs synchronization / fault detection circuit 101 for performing fault monitoring such as loss of synchronization, deterioration of error rate, input PCM interruption, and the synchronization / fault detection. A failure determination circuit 103 that determines whether the input PCM signal cannot be used based on the failure information of the circuit 101
And a timing counter 1 that operates in synchronization with the input PCM signal with the information that synchronization has been established by the synchronization / fault detection circuit 101.
02, a use mode setting circuit 105 that stores in advance whether each channel information of the input PCM signal is a voice signal, a data signal, or a switch signal, and the output of the timing counter 102. Use mode setting circuit 105 at the position that matches the time slot sequence of
The fixed pattern generation circuit 106 that generates a fixed pattern corresponding to the mode set in step 1 and the output of the synchronization / fault detection circuit 101 and the output of the fixed pattern generation circuit 106 are switched based on the output of the fault determination circuit 103 2 To-one selection circuit 107
And in the digital addition in the transmitting unit 2 which will be described later, the sum of the audio signals according to the channel information use mode,
A selection signal generation circuit 104 for generating a selection signal for selecting either the sum of data signals or the sum of exchange signals is provided.

On the other hand, the transmitting unit 2 receives the A direction input PCM signal and the C direction input PCM.
Digital adder circuit 201 for summing signals and B direction output P
As the CM signal, a signal from the A direction, a signal from the C direction, or a digital addition circuit 20 that sums them.
3 to 1 to select the signal from 1 for each time slot
And a selection circuit 202.

FIG. 2 is a diagram showing an example of the use mode setting circuit 105 and the fixed pattern generation circuit 106. Usage mode setting circuit 105
Uses ROM (Read Only Memory) and stores the usage mode in advance. On the other hand, fixed pattern generation circuit
106 is a fixed pattern for audio signal 106 based on the selection signal corresponding to the usage mode from the usage mode setting circuit 105.
Three-to-one selection circuit 1064 for selecting one of 1, a fixed pattern for data signal 1062, and a fixed pattern for exchange signal 1063
And a parallel / serial conversion circuit 1065 for converting the selected 8-bit parallel signal into a serial signal.

Although a ROM is used for the use mode setting circuit 10 here, it is possible to replace it with a RAM so that the use mode can be easily changed.

The operation of this embodiment will be described below.

In FIG. 1, A-direction input PCM input from terminal 11
The signal is subjected to frame synchronization and multi-frame synchronization by the synchronization / fault detection circuit 101, and at the same time, loss of synchronization, deterioration of error rate, fault monitoring of the input PCM stage, etc. are performed, and then the 2-to-1 selection circuit 107 Sent to. 2-to-1 selection circuit 107
Is normally transmitted through the A direction input PCM signal, and when the failure determination circuit 103 determines that the input PCM signal cannot be used based on the failure information of the synchronization / failure detection circuit 101, the signal from the fixed pattern generation circuit 106. Switch to. The fixed pattern generation circuit 106 is used at a position that coincides with the time slot sequence of the input PCM signal by the output of the timing counter 102 that operates in synchronization with the input PCM signal with the information that synchronization has been established by the synchronization / fault detection circuit 101. A fixed pattern corresponding to the mode set by the mode setting circuit 105 is generated. The ROM, which is the use mode setting circuit 105, stores in advance whether the channel information of the input PCM signal is a voice signal, a data signal, or a switch signal as a use mode.

As shown in FIG. 2, the output of the timing counter 102 is input to the address input A of the ROM, and as the address input A changes, a selection signal corresponding to the use mode is output from the data output D of the ROM. The output switches the 3-to-1 selection circuit 1064 of the fixed pattern generation circuit 106. A fixed pattern 10 for audio signals is input to the input of the 3-to-1 selection circuit 1064.
61, a data signal fixed pattern 1062, and an exchange signal fixed pattern 1063 are sent. These fixed patterns are 8-bit parallel signals. 8 bits of fixed pattern switched by the 3 to 1 selection circuit 1064 is a parallel / serial conversion circuit.
It is sent to 1065 and converted from a parallel signal to a serial signal at the output of the timing counter 102, and a fixed pattern of 2: 1
It is output to the selection circuit 107.

The output fixed pattern is selected by the 2-to-1 selection circuit 107 as described above and sent to the transmission unit 2.

In the transmitter 2, the output of the 2-to-1 selection circuit 107 is sent to the 3-to-1 selection circuit 202 and the digital addition circuit 201. The C-direction input PCM signal from the receiver 5 is also sent to the 3-to-1 selection circuit 202 and the digital addition circuit 201 via the time slot rearrangement circuit 9. The digital adder circuit 201 takes the sum of the A-direction input PCM signal and the C-direction input PCM signal, and sends the result to the 3-to-1 selection circuit 202. The digital addition includes a sum of voice signals, a sum of data signals, and a sum of exchange signals depending on the channel information use mode, and the selection is performed by the output from the selection signal generation circuit 104 of the receiving unit 1. The 3-to-1 selection circuit 202 selects, as the B-direction output PCM signal, a signal from the A direction, a signal from the C direction, or a signal obtained by adding the signals for each time slot and outputs the selected signal from the terminal 21. .

〔The invention's effect〕

As described above, the present invention stabilizes the operation of the terminal device connected to the digital add / drop multiplexer by replacing the channel information with the fixed pattern corresponding to the use mode when the input signal fails, and detects the failure. There is an effect that communication using digital addition can be ensured between the same device and the same digital add / drop multiplexer connected in a chain.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing an example of a use mode setting circuit and a fixed pattern generation circuit of FIG. 1, and FIG. 3 is an embodiment of the present invention. FIG. 4 is a diagram showing a 2048 kbit / s PCM multiplexed frame, and FIG. 4 is a block diagram showing the overall configuration of a digital add / drop multiplexer which is an embodiment of the present invention. 1,3,5 …… Reception unit 2,4,6 …… Transmission unit 7,8,9,10 …… Time slot rearrangement circuit 101 …… Synchronization / fault detection circuit 102 …… Timing counter 103 …… Fault judgment Circuit 104 …… Selection signal generation circuit 105 …… Use mode setting circuit 106 …… Fixed pattern generation circuit 107 …… 2: 1 selection circuit 201 …… Digital addition circuit 202 …… 3: 1 selection circuit 1061 …… For voice signals Fixed pattern 1062 …… Fixed pattern for data signal 1063 …… Fixed pattern for exchange signal 1064 …… 3 to 1 selection circuit 1065 …… Parallel / serial conversion circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Sadayoshi Takahashi, 2nd Raijin, Yoshioka, Yamato-cho, Kurokawa-gun, Miyagi Miyagi NEC Corporation (56) Reference JP-A-62-31229 (JP, A)

Claims (1)

[Claims] 1. A synchronization / synchronization for monitoring a failure at the same time as synchronizing a frame and a multiframe with respect to an input PCM signal.
The failure detection means and the input PC based on the failure information of the synchronization / failure detection means
Failure determination means for determining the unavailability of the M signal, a timing counter that operates in synchronization with the input PCM signal with the information that synchronization has been established by the synchronization / failure detection means, and channel information of the input PCM signal in advance Is a voice signal, a data signal, or a switch signal, and stores the use mode setting means for storing the use mode, and the use mode is set at a position corresponding to the time slot sequence of the input PCM signal by the output of the timing counter. Fixed pattern generating means for generating a fixed pattern corresponding to the mode set by the setting means, and switching between the output of the synchronization / failure detecting means and the output of the fixed pattern generating means based on the output of the failure determining means, No. 1 selecting means, and add / drop means for branching the PCM signal from the first selecting means and inserting a new PCM signal from the outside , A selection signal generating means for generating a selection signal for selecting one of a sum of voice signals, a sum of data signals, and a sum of exchange signals according to a usage mode of channel information, and a selection signal from the selection signal generating means, First
PCM signal from the selecting means and the PCM signal from the add / drop means
A digital addition means for summing signals, a PCM signal from the first selection means, a PCM signal from the add / drop means, or a signal from the digital addition means obtained by summing the time slots And a second selecting means for selecting each of them.