JPH07105765B2 - Phase-modulated signal grouping demodulator - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention, for example, converts a frequency-division-multiplexed digital phase-modulated signal provided in a satellite device for satellite communication into a baseband signal for each channel and separates the baseband signal. The present invention relates to a grouped demodulation device for phase-modulated signals in which the carrier frequency is automatically corrected by a carrier correction circuit for each signal and the signal is demodulated.

[0002]

2. Description of the Related Art FIG. 3 shows a conventional demodulator of this type.
For example, a received radio wave signal of a satellite station in satellite communication, which has been converted to an intermediate frequency from the input terminal 11, is quadrature detected by the quadrature detector 12, that is, the local signal from the local oscillator 13 and the input signal are multiplied by the multiplier 14. At the same time, the local signal shifted by π / 2 in the phase shifter 15 and the input signal are multiplied in the multiplier 16 to obtain the in-phase detection component and the quadrature detection component of the input signal. Both of these detected components are converted into digital signals by the AD converters 17 and 18, respectively, and these digital signals are separated into respective channel components by the separation / conversion unit 19 and converted into baseband signals to be extracted. The baseband signals of the first to m-th channels are complex signals of the in-phase component and the quadrature component, and are supplied to the carrier correction circuits 22 _{1 to} 22 _m , respectively.

In the carrier correction circuit 22 ₁ , the complex signal of the cos signal and the sin signal of the local signal from the local oscillator 23 is complex-multiplied in the multiplier 24 by the input baseband signal of the first channel. The output of the multiplier 24 is supplied to the root cosine filter 25, and the impulse response is subjected to convolutional calculation so that there is no intersymbol interference and the low frequency component is extracted. The output of the filter 25 is supplied to the clock reproduction circuit 26 to reproduce the clock. The reproduction of this clock is performed by detecting the 0 point, that is, detecting the point where 0 crosses. Using the reproduced clock, the output of the filter 25 is supplied to the decoding circuit (not shown) for each symbol period, and is also supplied to the phase error detection unit 28.

The phase error detector 28 detects the deviation of the carrier wave in the input baseband signal from the reference frequency. In other words, the frequency of the input signal fluctuates due to fading and deviates from the reference frequency, or radio waves from individual ground stations are received as signals of different channels, but the deviation of the transmission frequency from the ground station from the normal value Causes a deviation from the reference frequency. In order to detect and correct this frequency shift, a so-called frequency offset, the phase error detection unit 28 detects the phase shift of the carrier wave with respect to the reference. In this phase error detection, for example, the phase θ of the carrier wave is first detected. The phase θ is, for example, the square root of the sum of squares of the input in-phase component I and quadrature component Q, and I
Calculated by taking the arc cosine of the value obtained by dividing. The original phase of this carrier wave is, for example, π / 4, 3π / 4, 5π / 4, 7π / 4 in a 4-phase PSK modulated wave,
This is divided by the maximum phase deviation π / 2, and the rest is obtained to convert the phase θ of each detected carrier wave into a phase θ ′ within the range of 0 to π / 2. This phase θ'and 1 / maximum phase deviation
In the case of 2, that is, four-phase PSK, the difference Δθ from π / 4 is taken as the detected phase error. If the carrier wave has no deviation in frequency or phase, the θ′−π / 4 = Δθ becomes zero.

The phase error Δθ detected in this way is given as a control signal to the local oscillator 23 through the low pass filter 29. In the low-pass filter 29, the variation of the phase error is integrated, that is, smoothed, and the local oscillator 23 is controlled by the smoothed phase error. That is, if the output phase of the low-pass filter 25 is θ ′,
The value obtained by adding θ ′ (n) −θ ′ (n−1) from n = 0 to n and dividing the value by n is detected as the frequency deviation Δω, and Σθ ′ (n) (Σ is n -N to n)
A value obtained by dividing by is obtained as a phase error ω ₀ , and a signal of exp (jΔωt + ω ₀ ) is generated from the local oscillator 23. This signal is supplied to the multiplier 24. As a result, the frequency shift and phase shift of the input signal with respect to the reference frequency are removed, the value of the filter 25 can be output at the correct clock timing, and correct decoding can be performed.

The carrier correction circuits 22 _{2 to} 22 _m are similarly constructed.

[0007]

The deviation of each channel with respect to the reference frequency becomes relatively large or relatively quickly fluctuates.
In other words, in order to be able to apply so-called AFC, it is necessary for the carrier correction circuit to perform a relatively accurate and high-speed operation, which results in a large circuit scale and an expensive price. When there are many channels, a carrier correction circuit is provided for each channel, which makes the overall expensive and large, and consumes a lot of power.
Especially, it is not preferable to be mounted on a satellite.

An object of the present invention is to provide a phase reception grouping demodulation device which operates for a large number of channels, operates at high speed, and can be reduced in size, weight, power consumption and cost. It is in.

[0009]

According to the present invention, each baseband signal is stored in the memory in the first proper amount, and the symbol period is divided into equal intervals for each of the stored baseband signals. The point is reproduced using an interpolation filter, and P = ^z √ (| a (t) | ^x + | b of the instantaneous in-phase component a (t) and the instantaneous quadrature component b (t) of the reproduced signal.
(T) | ^y ) (x, y, z are real numbers that are not 0)
The symbol timing is calculated for each point divided at equal intervals, the clock timing is obtained from the change state of P, and the obtained clock timing is used to generate the carrier wave of the baseband signal from the phase angle at the clock timing of the reproduction signal. The frequency and phase shift from the reference of are obtained. The frequency and phase shift thus obtained are corrected and set in the local oscillator in the carrier correction circuit of the corresponding channel, and the clock timing obtained is the clock in the clock recovery circuit in the carrier correction circuit of the corresponding channel. It is set as timing.

[0010]

Since the clock timing of the channel is set in the carrier correction circuit of each channel, and the large frequency error and phase error with respect to the reference of the carrier wave are set, the carrier correction circuit of each channel determines from the demodulated symbol value. The phase error is detected, and the set frequency error and phase error are finely adjusted. As described above, the processing commonly used for each channel is processed in a time-divisional manner, and each channel is controlled in real time.
All functions will be efficiently shared.

[0011]

FIG. 1 shows an embodiment of the present invention. Figure 1 Smell
The parts corresponding to those in FIG. 3 are designated by the same reference numerals. Tsuma
Carrier correction circuit 2 for each channel as before
Two ₁Through 22_mIs also provided, but in addition to this, it is common in the present invention
An arithmetic unit 31 is provided, and each channel is provided in the common arithmetic unit 31.
The baseband signal of is acquired. That is, the separation conversion unit
Each baseband signal from 19 is sequentially selected by the selector 32.
Selected, the data of about 30 to 100 samples is time-divided.
Data is captured for each channel and recorded in the memory 33.
Remembered After loading to this memory 33 is completed
In addition, each baseband signal in the memory 33 is assigned to each channel
Read each time and divide the clock into 25 equal parts, and the value of that point
Is reproduced using the interpolation filter 30, and the clock reproduction unit 3
4 to detect the clock timing. Croot
For example, the reproduction unit 34 may include the I and Q signals for each sample.
The square of the pull value is detected by the instantaneous power detector 35.
It The instantaneous power detected by this instantaneous power detector 35 is
In the lock timing detection unit 36, the clock timing
Are detected.

That is, when the instantaneous power value and the waveform of the data of the baseband signal are repeatedly displayed for each symbol period so as to be displayed on the cathode ray tube, the waveform becomes as shown in FIG. 2A, and the eye pattern is most converged. The sampling point is the clock timing. Therefore, when the variance of each sampling point in this eye pattern is obtained, the curve 37 in FIG. 2B is obtained, and the sampling point having the minimum value of this variance curve 37 is obtained as the clock timing ts. The detection of the clock timing ts is
If the average value of the instantaneous power is calculated in addition to the dispersion, FIG.
Curve 37, and the sampling point at which the average value curve 38 has the maximum value is the clock timing ts. The clock recovery unit 34 may obtain the clock timing using a conventional clock recovery method. As a method for obtaining the minimum variance using the value of I ² + Q ² described above, ^z √ (| I | ^x + | Q | ^y ) is generally used, in which case z = x = y = 2 is generally used. However, each value may be different as long as it is a real number other than 0. (A point with a small variance value is required even if x = y is not satisfied. In particular, when x and y are changed, weighting is added to set according to the characteristics.

Next, the baseband signal of the corresponding channel is sampled by using the obtained clock timing, that is, the data at the sampling point ts is taken out by the sampling unit 41, and the sampled value taken out by the sampling unit 41 is obtained. It is input to the phase error detector 42 to detect the phase error of the carrier of the corresponding channel with respect to the reference. The phase error detection in the phase error detection unit 42 may be the same as the conventional one. First, the phase θ of the carrier wave is detected by the phase detection unit 43, and the detected phase θ is π / 2, generally 2 ⁿ phase PSK ( When n is an integer of 1 or more), the maximum phase deviation angle θ _M is divided, and the remainder θ ′ is detected by the division unit 44. In this way, the detected phase θ is converted into a phase θ ^′ within 0 to π / 2, and the converted phase θ ′ and half of the maximum deviation angle θ _M
Is calculated, that is, θ′−π / in 4-phase PSK
4 = Δθ is calculated in the subtraction unit 45 and the phase error Δθ
Is detected.

In this way, the division unit 44 converts the detected phase within the angle range of 0 to π / 2 and further takes the difference from π / 4. Therefore, if the frequency or phase changes significantly,
For example, as shown in FIG. 2C, the phase error Δθ detected by the subtraction unit 45 sequentially increases, and when it exceeds π / 2 (θ _M ), it suddenly becomes a large negative value, resulting in an erroneous phase error. Therefore, when the phase error that has increased in this way suddenly decreases to a large negative value, π / 2, that is, the maximum phase deviation angle θ _M, must be added to prevent this from occurring. Is preferred. If a similar phenomenon occurs when the phase error decreases, π / 2 is subtracted to correct. That is, Δθ detected by the phase error detection unit 42 is the absolute value of the difference between the previously corrected phase error θ ″ and the currently detected phase error θ ′ in the phase error correction unit 45, which is π / 4 (=
θ _M / 2) is exceeded, the detected phase error Δθ becomes π.
/ 2 (θ _M ) is added or subtracted so that the absolute value of the difference is π
Do not exceed / 4 (θ _M / 2).

The phase error θ ″ corrected in this way is supplied to the frequency shift detector 47. In the frequency shift detector 47, the calculation of (1 / N) Σθ ″ (n) −θ ″ (n−1) is performed. From n = 1 to N to obtain the frequency deviation Δω,
Further, the calculation of (1 / N) Σθ ″ (n) is performed from n = 1 to N to obtain the phase shift ω _{0. In} this way, the clock timing ts of the baseband signal of each channel is detected, Based on this, the angular frequency shift Δω and the phase shift ω ₀ with respect to the reference are respectively detected.

The clock timings detected in this way are set in the clock recovery circuits 26 of the carrier correction circuits 22 _{1 to} 22 _m in the corresponding channels, respectively, and the clock timings are set by the clock recovery circuits 26 at the set clock timings. Each part is sampled. Further, the angular frequency shift Δω and the phase shift ω ₀ detected corresponding to each channel are set in the local oscillator 23 of the corresponding carrier correction circuits 22 _{1 to} 22 _m . The above operation is performed in a time division manner for each channel. Therefore, after setting these clock timings, frequencies, and phase shifts, the carrier correction circuits 22 _{1 to} 22 ₁
Each 2 _m can start from that state and correct the frequency shift and phase shift for the corresponding input baseband signal.

Further, in the state in which the frequency shift and the phase shift are corrected in this way, there is only a slight fluctuation. In other words, it takes a relatively long time to detect the clock timing, frequency deviation, etc. of each channel that is input first and put them in the synchronized state, but once the synchronized state is reached, the tracking of input signal fluctuations is very fast. It doesn't have to work. Therefore, it is not necessary to operate each carrier correction circuit 22 _{1 to} 22 _m at high speed and with high accuracy, and it is possible to simply configure.
That is, although it takes a relatively long time to synchronize the signal of the input channel when the signal is input, it is relatively easy to follow the synchronization once synchronized. In general, communication occurs in bursts, and it is necessary to synchronize and relay the generated communication. For common clock timing and frequency deviation for each initial synchronization, the common arithmetic unit 31 can speed up the communication. In addition, it is possible to detect with high accuracy and to make the carrier correction unit follow up even if there is a change thereafter, so that the carrier correction unit can be easily configured. Further, once the carrier correction section is set to the substantially synchronous state as described above, the carrier correction section can sufficiently perform tracking. Therefore, in the carrier correction circuit, only the phase error of the local oscillator 23 needs to be tracked and corrected. The correction may be omitted. In the present invention, the carrier correction circuits 22 _{1 to} 22
The carrier deviation of 2 _m may be controlled, for example, on the order of 10 ² Hz. The detection of the deviation by the common calculation unit 31 is
If the conventional technique is used, it is about ± 3 KHz, and it is necessary to detect such a shift. When the instantaneous power is detected and the clock timing is detected as in the above-described example, it is possible to correctly detect and follow even a deviation of ± 7 KHz.

In the instantaneous power detector 35 shown in FIG. 1, the sum of the absolute value of the instantaneous in-phase component a (t) to the s-th power (s is a non-zero real number) and the absolute value of the instantaneous quadrature component b (t) to the s-th power. P _x or its r
The power root P _y = ^r √P _x (r is a non-zero real number) is calculated at each point obtained by dividing the symbol period into equal intervals, and the clock timing detection unit 36 changes the state of P _x or P _y , for example, as described above. Alternatively, the clock timing may be detected from the variance value (or standard deviation), the average value, or the like.

[0019]

As described above, according to the present invention, the common arithmetic unit is provided, and the clock timing and the deviation of the carrier wave with respect to the reference are calculated first when the signal is input to a certain channel. However, even if the frequency deviation of the carrier wave is relatively large,
Moreover, it is possible to calculate at high speed, and the calculated clock timing, frequency, and phase shift are set in each carrier correction circuit of the corresponding channel. Therefore, the configuration of the carrier correction circuit of each channel is, for example, within ± 50 Hz. It is only necessary to make corrections, and the operation speed is slow, so the circuit can be made small and compact, inexpensive and lightweight, and overall it is extremely small when the number of channels is large. Light weight, economical and low power consumption.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

2A is a diagram showing an eye pattern of instantaneous power, FIG. 2B is a diagram showing a dispersion curve and an average value curve of instantaneous power, and FIG. 2C is a diagram showing a state in which a deviation error occurs with respect to a large frequency change.

FIG. 3 is a block diagram showing a conventional AFC device of this type.

Claims (1)

[Claims] 1. A frequency division multiplex phase modulation wave signal is supplied to each channel.
Each channel is converted into baseband signals and separated, and each
Carrier correction circuit for carrier frequency for each band signal
Of the phase-modulated signal which is corrected by
In the grouping demodulator, input and store the baseband signal of each channel.
Means for dividing the symbol period into equal intervals from the stored signal.
Means for reproducing the above-mentioned points by using an interpolation filter, and the instantaneous in-phase component a (t) of the reproduced signal,
P of cross component b (t) = ^z√ (| a (t) |^x+ | B
(T) |^y) (However, x, y, and z are not zero
Number) is calculated for each point obtained by dividing the symbol period at equal intervals.
And a change state of the calculated P for each baseband signal
Means for calculating the clock timing from the above, and using the calculated clock timing,
Is it the phase angle at the clock timing of the regenerated signal?
Frequency and position relative to the reference of the carrier of the corresponding channel
The means for calculating the phase shift and the frequency and phase shift obtained above are respectively calculated.
Local in the carrier correction circuit of the corresponding channel of
Means to set each oscillator and clock timing obtained for each baseband signal
In the carrier correction circuit of the corresponding channel above.
Grouping of phase-modulated signals, characterized by comprising:
Demodulator.