JPH07105395B2 - Semiconductor device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for increasing the effective input impedance of an integrated circuit, and to a means for increasing the input impedance of an input circuit connecting the base of a transistor to an input terminal. .

2. Description of the Related Art A case where an input signal is input to the base of an NPN transistor in an integrated circuit (hereinafter referred to as an IC) from the outside of the IC is described as an example for convenience. 3 and 4 are perspective cross-sectional views of a conventional semiconductor device showing a configuration around a pad to which an input signal is input from the outside of the IC.

In FIG. 3, 101 is a P-type semiconductor substrate, 102 is an N-type epitaxial layer formed on the semiconductor substrate 101, 103 is an insulating layer covering the epitaxial layer 102, and 105 is a signal input line from the outside of the IC. The pad 105 is composed of a large-area conductor layer. The conductor layer led out from the pad 105 is connected to the base of the NPN transistor 120 in the IC. In a normal operation state, the semiconductor substrate 101 is connected to the ground potential, and the epitaxial layer 102 is connected to the DC power source having the highest potential during operation.

In the conventional example shown in FIG. 3, an insulating layer 1 is provided between the conductor layer including the pad 105 and the DC power source (epitaxial layer 102).
The parasitic capacitance 111 exists via 03, and the parasitic capacitance 111 is added to the capacitance existing at the base of the transistor 120 to reduce the input impedance seen from the outside.

The perspective sectional view of FIG. 4 shows a conventional configuration for reducing the parasitic capacitance as much as possible as in the conventional example of FIG. Fourth
In the figure, the N-type epitaxial layer immediately below the pad 105 is indicated by P.
It is surrounded by a shape separation region 104 to form an island shape, and is separated from another epitaxial layer 102 connected to a DC power supply. In this case, the parasitic capacitance between the pad 105 and the P-type semiconductor substrate 101 at the ground potential is the parasitic capacitance 111 between the pad 105 and the epitaxial island immediately below the insulating layer 103, and the epitaxial island and the semiconductor substrate. It becomes a combined capacitance value with the parasitic capacitance 112 between 101 and 101. That is, in the conventional example of FIG. 4, two parasitic capacitances 111 and 112 are connected in series to reduce the capacitance value.

Problems to be Solved by the Invention In the above-described conventional configuration, the parasitic capacitance of the pad cannot be said to be sufficiently small, and particularly AC input impedance is lowered at high frequencies.

The present invention solves such a problem and provides means for effectively reducing the parasitic capacitance related to the pad.

Means for Solving the Problems A semiconductor device of the present invention comprises an epitaxial layer of opposite conductivity type formed on a semiconductor substrate of one conductivity type, an epitaxial island formed by surrounding a predetermined region of the epitaxial layer with an isolation region, and An insulating layer covering the epitaxial island, a pad formed on the insulating layer in the epitaxial island, an input signal from the pad is input to the base, and a signal in phase with the input signal is input to the emitter. A transistor for outputting, and biasing the epitaxial island with the potential of the emitter.

Operation With this configuration, when the inside is viewed from the outside through the pad, the parasitic capacitance between the pad and the epitaxial island is equivalent to the ratio of the difference between the input signal amplitude and the emitter signal amplitude divided by the input signal amplitude. The input capacitance of the IC is reduced. On the other hand, since the parasitic capacitance between the epitaxial island and the semiconductor substrate is charged and discharged by the emitter circuit having a low output impedance, it does not become a factor that lowers the input impedance, and the input impedance of the IC can be increased.

Example A semiconductor device of an example according to the present invention will be described below with reference to FIG.

FIG. 1 is a diagram showing a perspective cross-sectional view of a main part of a semiconductor device and an equivalent circuit. In FIG. 1, 101 is a P-type semiconductor substrate, and 102 (and 106) are N formed on the semiconductor substrate 101. -Shaped epitaxial layer, 103 is an insulating layer covering the epitaxial layer 102, 104 is a P-type isolation region, 105 is a pad for bonding a signal input line from the outside of the IC, and the pad 105 is a large-area conductor. Composed of layers. And
A predetermined region of the epitaxial layer immediately below the pad 105 is surrounded by an isolation region 104 to form an epitaxial island 106 electrically isolated from another epitaxial layer 102. In addition, pad 1
The conductor layer derived from 05 is connected to the base of the NPN transistor 120 in the IC and the resistor R _E is connected to the emitter of the transistor 120.
And the resistor R _C is connected to the collector to form an input circuit. The potential A1 of the emitter of the transistor 120 is the first
As shown in the figure, if the AC signal is not grounded, a signal in phase with the input signal input to the base is output. And
This emitter potential A1 is biased to the epitaxial island 106.

Then, the parasitic capacitance 111 between the pad 105 and the epitaxial island 106 is equivalently reduced by the ratio of the difference between the input signal amplitude and the emitter signal amplitude divided by the input signal amplitude. On the other hand, since the parasitic capacitance 112 between the epitaxial island 106 and the semiconductor substrate 101 is charged and discharged by the emitter circuit having a low output impedance, it hardly contributes to the input impedance.

According to the configuration of the embodiment shown in FIG.
A, the resistance RE connected to the emitter is 50 KΩ, the plan shape of the pad 105 is 120 μm square, and the prototype is evaluated. When the prototype is evaluated, the input capacitance seen from the outside of the IC is 0.2 pF. It was possible to significantly reduce the capacitance value of about 0.7 pF obtained in the conventional example of FIG.

Next, another embodiment will be described with reference to FIG. FIG. 2 is a conceptual diagram showing an example in which the circuit connected to the pad 105 is modified, and FIG. 2 (a) shows the gate of an N-channel junction field effect transistor whose source is connected to the resistor R _S. In the example of connecting to the pad 105, the epitaxial island 106 is biased by the source potential A2a.

FIG. 2 (b) is a high input impedance circuit using a Darlington-connected bipolar transistor,
The epitaxial island 106 is biased with the emitter output potential A2b to which R _E is connected. In any of the above examples, it is possible to reduce the parasitic capacitance related to the pad viewed from the outside of the IC and increase the input impedance of the IC.

The same effect can be obtained not only with the epitaxial islands but also with other conductor layers as the layers that face the pads under the insulator.

EFFECTS OF THE INVENTION As described above, according to the present invention, it is possible to reduce the parasitic capacitance related to the pad seen from the outside of the IC and increase the input impedance of the IC.

[Brief description of drawings]

FIG. 1 is a diagram showing a perspective sectional view and an equivalent circuit of a semiconductor device according to one embodiment of the present invention, FIG. 2 is a circuit diagram for explaining another embodiment, and FIGS. It is a perspective sectional view of a semiconductor device. 101 ... P-type semiconductor substrate, 102 ... N-type epitaxial layer, 103 ... Insulator layer, 104 ... P-type isolation region, 105
... Pads, 106 ... N-type epitaxial islands, 111, 112
...... Parasitic capacitance, 120 to 122 ...... Input transistor, A
1, A2a, A2b ... Points connected to the epitaxial island 106.

Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 29/73

Claims (1)

[Claims] 1. An opposite conductivity type epitaxial layer formed on a one conductivity type semiconductor substrate, and an epitaxial island formed by surrounding a predetermined region of the epitaxial layer with an isolation region.
An insulator layer covering the epitaxial island, a pad formed on the insulator layer in the epitaxial island, an input signal from the pad is input to the base, and a signal in phase with the input signal is emitted from the emitter. And a transistor for outputting to the semiconductor device, and biasing the epitaxial island with the potential of the emitter.