JPH07105033A - Multiplex system - Google Patents

Abstract

PURPOSE:To prevent the output of a system switching signal owing to the runaway of a standby system even if it occurs so as to secure the stable operation of a selector. CONSTITUTION:The switching of the selector 15 is controlled only by the system switching signal CO which an. operation system computer 10 outputs. Even if the standby system computer 11 runs away and the system switching signal Cl is outputted, the signal is prevented by the operation of a mask circuit 21, and it is prevented from being inputted to the selector 15. The operation system computer 10 periodically transmits an operation system notifying signal AO to a selection control part 18, a mask control signal M1 is accordingly outputted and the mask circuit 21 operates.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiplexing system in which control parts are multiplexed so that the system can be continuously operated even if a failure occurs.

[0002]

2. Description of the Related Art For example, in a system for searching a database, a computer searches the database according to a request, executes a necessary search process, and outputs a result. When a failure occurs in the computer in such a system, the database search operation is stopped. However, if this is a very important task, multiple computers are used so that the task can be continued even if a failure occurs. Not limited to database systems, there are many systems that require this kind of reliability.

Such a multiplexing system is constructed as follows. FIG. 2 shows a block diagram of a conventional multiplexing system. In the system shown in the figure, an active computer 10 and a standby computer 11 are connected to a target device 16 via a selector 15. The target device 16 includes a hard disk (HDD) and other input / output devices. The selector 15 is a device that selects one of the input / output bus 12 of the active computer 10 and the input / output bus 13 of the standby computer 11 and connects it to the input / output bus 14 of the target device 16. The selector 15 is controlled by a system switching signal C0 or C1 input from the operating computer 10 or the standby computer 11 to switch the connection.

That is, for example, when the active computer 10 is connected to the target device 16 via the selector 15 and controls the target device 16, the active computer 1
When a failure occurs in 0, the system switching signal C0 is input from the operating computer 10 to the selector 15. As a result, the selector 15 disconnects the input / output bus 12 of the active computer 10 from the input / output bus 14 of the target device 16, and instead connects the input / output bus 13 of the standby computer 11 to the input / output bus 14 of the target device 16. To do. In this way, the conventional multiplexing system has ensured reliability.

[0005]

The conventional multiplexing system as described above has the following problems to be solved. For example, the operational computer 10 shown in FIG.
Is connected to the target device 16 and controls it,
The standby computer 11 malfunctions for some reason,
There may be a runaway. In such a case, the system switching signal C1 may be input to the selector 15 from the standby computer 11 while the operating computer 10 is operating.

As described above, the selector 15 receives the system switching signal C0 or C1 from the operating computer 10 or the standby computer 11 and switches the connection of the input / output bus. Therefore, for example, when the input / output bus 12 is connected to the input / output bus 14 of the target device 16, when the system switching signal C1 is input from the standby system computer 11, the switching operation is executed and the input / output bus 13 is connected to the target device 1
6 input / output bus 14 may be connected. With this, while the operational computer 10 is executing some processing, the processing is interrupted.

For example, when the target device 16 is a hard disk, the operating system computer 10 uses the target device 16 as the target device 16.
If a connection switch is executed while accessing the
There is also a risk of causing a disk crash. The present invention has been made paying attention to the above points. Even when the standby system runs out of control and a system switching signal is output as described above, it is possible to prevent this and ensure stable operation of the selector. It is an object of the present invention to provide such a multiplexed system.

[0008]

SUMMARY OF THE INVENTION A multiplexing system of the present invention includes an active system that is currently controlling a target device and a standby system that controls the target device on behalf of the active system when a failure occurs in this active system. When a system switching signal is input, a selector for switching control of the target device from control by the operating system to control by the standby system, and a system switching signal output from the standby system during control of the target device by the operating system. A mask circuit for masking and blocking an input to the selector is provided.

[0009]

In this system, selector switching control is performed only by the system switching signal output from the operating computer. That is, even if the standby computer runs out of control and outputs the system switching signal, this signal is blocked by the operation of the mask circuit and is not input to the selector. Therefore, the active computer periodically sends the active notification signal to the selection control unit 18, whereby the mask control signal is output and the mask circuit 21 operates.

[0010]

The present invention will be described in detail below with reference to the embodiments shown in the drawings. FIG. 1 is a block diagram showing an embodiment of a multiplexing system of the present invention. The device shown has two computers,
That is, the operating computer 10 and the standby computer 11
Is connected to the target device 16 via the selector 15 and controls the target device 16. The selector 15 is a circuit that operates to connect either one of the input / output bus 12 of the active computer 10 and the input / output bus 13 of the standby computer 11 to the input / output bus 14 of the target device 16. The circuit configuration and operation of the selector 15 are the same as those of the conventional device.

The system switching signal C0 output from the operating computer 10 is input to the selector 15 via the mask circuit 20 to control the connection switching. Further, the system switching signal C1 output from the standby computer 11 is input to the selector 15 via the mask circuit 21 to control the connection switching. In addition, the active computer 10 and the standby computer 11 are configured to input the active system notification signal A0 and the active system notification signal A1 to the selection control unit 18, respectively, and the mask control signal output from the selection control unit 18 M0
Is inputted to the mask circuit 20, and the mask control signal M1 is inputted to the mask circuit 21.

The system switching signals C0 and C1 are signals for controlling the switching of the connection by operating the selector 15 when the operating computer 10 or the standby computer 11 has a failure. For example, when the system switching signals C0 and C1 are low level, the selector 15
When the input / output bus 12 and the input / output bus 14 of the target device 16 are connected and the system switching signals C0 and C1 are at high level,
It operates to connect the I / O bus 13 to the I / O bus 14 of the target device 16.

The system switching signals C0 and C1 both take a high level value or a low level value and are input to the control terminal of the selector 15. The mask circuits 20 and 21 are connected to the system switching signal C, respectively.
This is a circuit that allows or blocks 0 and C1 from being input to the control terminal of the selector 15. Specific configurations and operations of these circuits will be described later with reference to FIGS.

The active system notification signals A0 and A1 output to the selection control unit 18 are the active system computer 1 respectively.
0 or a signal for the standby system computer 11 to notify the selection control unit 18 that it is the active system.
That is, for example, when the self is an active system, it outputs a pulsed signal that takes a high level value and a low level value at a constant cycle. When the operation system notification signal A0 or A1 has a low level constant value, for example, the computer that outputs this signal is a standby system.

The mask control signals M0 and M1 output from the selection control unit 18 are signals for instructing the mask circuits 20 and 21 whether or not to block the system switching signals C0 and C1. In the circuit shown in FIG. 1, for example, the active computer 10 periodically notifies the selection control unit 18 that it is the active computer. This notification is performed by the operation system notification signal A0 described above. The selection control unit 18
Upon receiving such an operation system notification signal A0, the operation system computer 10 recognizes that it is the operation system and controls the mask circuits 20 and 21. In this embodiment, when the active computer 10 is the active system, the mask circuit 20 allows the system switching signal C0 to be supplied to the selector 15, and the mask circuit 21 prevents the system switching signal C1 from being input to the selector 15. Block. Therefore, even when the standby computer 11 goes out of control and the system switching signal C1 is output uncontrolled, the selector 15 is not reached and no malfunction occurs.

FIG. 3 shows a block diagram of an embodiment of the selection controller. The selection control unit 18 shown in FIG. 1 is configured as shown in this figure, for example. That is, this circuit is a circuit that receives the operation system notification signals A0 and A1 from the operation system computer 10 or the standby system computer 11, respectively, and generates the mask control signal M0 and the mask control signal M1.

This circuit has 10 flip-flops 3
1 to 40 and 12 gates 51 to 62 are provided. The operational notification signal A0 is composed of three flip-flops 3
It is configured to be sequentially transmitted to 1, 32, and 33 every one clock, and the input signal of the third flip-flop 33 and the inverted signal of the output signal are input to the AND gate 51.

The output of the AND gate 51 is the OR gate 5.
2 and an AND gate 53 to input to the flip-flop 34. The output of the flip-flop 34 is fed back to the OR gate 52. Further, the output of the flip-flop 34 and the output of the AND gate 51 are input to the AND gate 54. Therefore, the high-level signal is sent to the output side only when both the signal input to the flip-flop 34 immediately before and the signal input subsequently are both at the high level. The AND gate 53 is controlled to pass the signal only when the operational notification signals A0 and A1 have different contents, that is, when one is a high level, the other is a low level, and when one is a low level, the other is a high level. It is a gate to do.

On the output side of the AND gate 54, an OR gate 55, an AND gate 56, and a flip-flop 35.
Are arranged and connected in order. Flip-flop 35
Signal is input to the OR gate 55, and the signal input immediately before is combined with the signal input next. The function of the AND gate 56 is similar to that of the AND gate 53.

With the above configuration, the mask control signal M0 is output from the inverted signal output terminal of the flip-flop 35. The circuit in the lower half shown in FIG. 3 has exactly the same configuration as the circuit in the upper half, and is configured to receive the operation system notification signal A1 and generate the mask control signal M1.

FIG. 4 is an explanatory view showing a concrete operation of the above circuit. FIG. 4A shows the contents of the working notification signal A0, and FIG. 4B shows the contents of the working notification signal A1. That is, the signal of (a) is the operating computer 10.
And the signal of (b) is output from the standby computer 11
Is output from.

The signal (c) is the mask control signal M0.
Then, the signal of (d) is the mask control signal M1. That is,
The mask control signal M0 shown in (c) is output from the active computer 10 and controls the mask circuit 20 inserted in the signal path of the system switching signal C0. On the other hand, the mask control signal M1 shown in (d) controls the mask circuit 21 output from the standby computer 11 and inserted in the signal path of the system switching signal C1. Also, the selector 15 is shown in (e).
The system switching operation of is shown.

As shown in (a), for example, the operational notification signal A0 is a signal which becomes high level only during the time t2 in the cycle of t1. It is assumed that the flip-flops shown in FIG. 3 are controlled in operation at the cycle t1, for example.
Here, for example, at time T1, the active computer 10 switches from the active system to the standby system, and the standby computer 11
Outputs the operational notification signal A1. In this case, the active computer 10 stops outputting the active notification signal A0.

At this time, the flip-flop 3 shown in FIG.
6 receives the operation system notification signal A1 and sends it to the flip-flops 37 and 38 and the AND gate 57 in order. These circuits are circuits for detecting the rising edge of the operation system notification signal A1, and are circuits for outputting a high level signal from the AND gate 57 when the rising edge is detected. Therefore, the high-level signal is sent to the flip-flop 39 at the clock next to the time T1. At this time, since the operation system notification signal A0 remains low level, the AND gate 59 is opened and the storage of the high level signal in the flip-flop 39 is not hindered.

The OR gate 58, the AND gate 59, the flip-flop 39, and the AND gate 60 are circuits for detecting whether or not the operation system notification signal A1 is input twice in succession. That is, this is a circuit for recognizing that the active system notification signal A1 is valid when the same type of pulse is input twice consecutively. This has the effect of blocking the input of noise and improving security. Figure 4
As shown in (b), the operational notification signal A1 is the time T1,
It becomes high level for a certain period of time twice after T2. As a result, the output of the AND gate 60 shown in FIG. 3 becomes high level and is input to the flip-flop 40 through the OR gate 61 and the AND gate 62. The circuit on the output side of the AND gate 60 outputs the input signal to the AND gate 6
This is a circuit that is maintained until 2 is closed. When a high level signal is input to the flip-flop 40, the mask control signal M1 which has been at the high level up to now is switched to the low level.

At time T1, when the output of the AND gate 57 shown in FIG. 3 becomes high level, the AND gate 56 is closed, so that the mask control signal M0 output from the flip-flop 35, which has been at the low level until now, changes to the time level. It changes to a high level after T1. As a result, after time T1, the operation of the mask circuit 20 shown in FIG. 1 becomes effective, and the input of the system switching signal C0 to the selector 15 is blocked.

Since the mask control signal M1 is switched to the low level after the time T2, the system switching signal C1 output from the standby computer 11 is the mask circuit 21.
Through the selector 15. Thus, as shown in FIG. 4E, the mask circuit for masking the system switching signal is switched in accordance with the system switching operation.

Here, a specific circuit configuration of the selector 15 will be described. FIG. 5 is a block diagram of an embodiment of the selector. This selector includes eight gates 63 to 70 and seven flip-flops 41 to 47. The AND gates 63 to 66 have system switching signals C00 and C, respectively.
01, C10, C11 are input.

C00 is a signal for requesting that the active computer 10 connect the target device 16 to itself, and the system switching signal C01 is used by the active computer 10 for the target device 1.
6 is a signal instructing that 6 should be connected to the standby computer 11. Both signals are naturally signals of opposite content. Further, the system switching signal C10 is a signal for instructing that the standby computer 11 should connect the target device 16 to the active computer 10, and C11 instructs the standby computer 11 to connect the target device 16 to itself. It is a signal.
These relationships are also signals having contents opposite to each other.

That is, when the system switching signal C00 is at high level, C01 is at low level, C10 is at high level,
C11 is at low level. Therefore, the system switching signal C0 shown in FIG. 1 immediately generates the system switching signals C00 and C01, and the system switching signal C1 immediately generates the system switching signals C10 and C11 to be input to this circuit.

Here, for example, when the mask control signal M0 is at low level, the AND gates 63 and 64 are opened, and the system switching signals C00 and C01 are input to the flip-flops 41 and 44 through the OR gates 67 and 68, respectively. For example, when the system switching signal C1 is at high level,
Since the system switching signal C00 goes high and C01 goes low, only the flip-flop 41 is set via the OR gate 67. This signal is input to the flip-flop 43 through the flip-flop 42. The AND gate 69 compares the signal input to the flip-flop 43 immediately before with the signal input to the next flip-flop 43, detects a change point, and outputs it to the flip-flop 47.

The output of the AND gate 69 is input to the reset terminal of the flip-flop 47, and the output of the AND gate 70 is input to the set terminal of the flip-flop 47. Therefore, when the reset terminal goes high for only one clock, the system switching signal C3 output from the flip-flop 47 is output.
Becomes low level, and the selector 15 connects the input / output bus 12 to the target device 16. Conversely, the flip-flop 47
When the signal input to the set terminal of the above becomes high level for one clock, the system switching signal C3 output from the flip-flop 47 becomes high level, and the input / output bus 13 is connected to the target device 16.

As described above, the mask circuit 2 shown in FIG.
0 and 21 and the selector 15 have mask control signals M0 and M
System switching signals C0 and C1 input from the system where 1 is valid
The switching of the selector 15 is executed only by. That is, when the mask control signals M0 and M1 are invalid,
AND gates 63 to 66 shown in FIG. 6 prevent input of the system switching signal, and the switching operation of selector 15 is not performed.

Further, AND gates 51 and 57 shown in FIG.
The output of each of the gates opens and closes the gates 53, 56, 59 and 62 for controlling the signals of the other party,
Both operational notification signals A0 and A1 are simultaneously selected by the selection control unit 1
When it is input to 8, it becomes impossible to recognize which computer is the active system, and both mask circuits 20 and 21 are masked. That is, the system switching signals C0 and C1 from either computer are not accepted.

As a result, for example, at time T3 in FIG.
In addition, when the operating system notification signal A0 also periodically becomes high level, the operating system notification signal A1 output from the other computer is not stopped yet. Therefore, the mask control signal M
Both 0 and the mask control signal M1 are valid. In this way, all the AND gates 63 to 66 shown in FIG. 5 are closed. Therefore, as shown in FIG. 4E, the system switching operation is performed at time T3.
It will not be performed after that.

The present invention is not limited to the above embodiments. In the above-described embodiment, the target device is controlled by using two operating computers and standby computers, but any number of standby computers may be used. Also,
The target device is not limited to the hard disk device, and may be an information processing device such as various other input / output devices. Further, the configuration of the mask circuit for controlling the selection operation of the selector and the configuration of the selection control unit for controlling the mask circuit can mask the system switching signal output from the standby system during the control of the target device by the active system. All you have to do is
It can be realized by using various equivalent functional circuits other than the above-mentioned embodiment.

[0037]

The multiplexing system of the present invention described above is configured to switch the connection with the target device from the active system to the standby system by using the selector, and during the control of the target device by the active system, Since a mask circuit that masks the system switching signal output from the standby system to block the input to the selector is provided, even if the computer, etc. configuring the standby system runs out of control and outputs the system switching signal randomly , This is prevented and the selector does not work accidentally. Therefore, for example, when the operating system controls a hard disk device or the like as a target device, there is no possibility of interrupting the control and causing a disk crash or the like.

[Brief description of drawings]

FIG. 1 is a block diagram of a multiplexing system of the present invention.

FIG. 2 is a block diagram of a conventional multiplexing system.

FIG. 3 is a block diagram of an embodiment of a selection control unit.

FIG. 4 is an operation explanatory diagram of a selection control unit.

FIG. 5 is a block diagram of an embodiment of a mask circuit.

[Explanation of symbols]

 10 Operating Computer 11 Standby Computer 15 Selector 16 Target Device 18 Selection Control Unit 20, 21 Mask Circuit

Claims (1)

[Claims] 1. An active system that is currently controlling a target device, a standby system that controls the target device on behalf of the active system when a failure occurs in this active system, and a target switching device when a system switching signal is input. The selector switches the control of the control from the control of the active system to the control of the standby system, and masks the system switching signal output from the standby system during the control of the target device by the active system to block the input to the selector. A multiplexing system comprising a mask circuit.