JPH07104768B2 - CRT display controller - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION A. Field of Industrial Application The present invention relates to a CRT display control device in which a programmable controller (hereinafter referred to as a PC) and a CRT display device are combined.

B. Summary of the Invention In the present invention, in a CRT display control device in which a PC and a CRT display device are combined, an output signal sent at every sequence cycle time of the PC is applied to a memory switching unit when there is no input data. By reading the required screen data from the memory, even if the input / output methods and time characteristics of the PC and CRT device do not match, that data is preferentially displayed only when change data occurs.

C. Conventional technology Conventional control systems that used CRT required high-level computer technology. However, in recent years, due to the remarkable progress of microcomputer technology, an easy-to-use CRT terminal device has emerged in which a microcomputer is built in the CRT terminal side and the main screen control can be easily performed. CRT like this
The terminal device is being used in combination with a PC that does not require knowledge of software and can be easily changed.

D. Problems to be Solved by the Invention When connecting the CRT terminal device and the PC as described above, there are the following problems.

(1) The data input / output methods do not match.

In order to control the screen of a general CRT terminal device, it is necessary to supply a signal conforming to JIS code character by character as in the typewriter. However, since the output of the PC is usually formed for the on / off control of the motor palm, disconnector, etc., this output can not be directly supplied to the CRT terminal device, and the memory content is also supplied to the PC. Even if there is a transfer function,
Not suitable for creating data equivalent to typewriter character control. After all, there is a problem that the screen cannot be controlled by PC output because the data input / output methods do not match.

(2) Problems due to sequence steps Normally, the sequence of a PC is designed to cycle once. The input data will be processed and output within this one cycle. In this case, the PC wants to use as few steps as possible to exchange data with the CRT terminal device. Therefore, it is not preferable to carry out all the data processing for one screen within one cycle because a large number of steps are required. Therefore, if only one point on the screen is processed for each cycle of the sequence, the number of steps can be small, but the time required for updating the display on the screen for one cycle of the sequence is required. However, there is a problem that it becomes unpractical because it takes a lot of time.

(3) The time characteristics do not match.

The data transmission speed to the CRT terminal device and the update speed of the data input / output from the PC do not match due to the above-mentioned sequence step problem. For example, if the PC-side speed is higher than the CRT terminal device speed, data will overflow, and in the opposite case, the responsiveness will deteriorate.

(4) There is a problem in data reliability.

Since data is variously converted when data is exchanged between the PC and the CRT terminal device, if a failure occurs in each conversion unit, an erroneous display is displayed, which seriously hinders the operation.

(5) I want to shorten the response time.

When switching screens, I want to update all data corresponding to the new screen as quickly as possible. Also, after that, it may be a little slower in order to improve the reliability of the data, but I would like to continue updating for reconfirmation of the screen data. Moreover, if a new status change signal comes in during that time, I want to display it with priority. I want to perform the above processing without increasing the number of steps.

E. Means for Solving Problems The first invention is configured as follows. Provided is an all-point part state memory that has an input processing unit to which data is input, and when an address output corresponding to the data processed by this input processing unit is input, the data is sent from the memory corresponding to that address. To be This memory is formed corresponding to the position where the CRT screen is divided into a plurality of sections. When there is change data among the data processed by the input processing unit, the signal output through the first gate circuit is preferentially read from the memory. At this time, the signal of the first gate circuit is input to and controlled by the memory switching unit instead of being directly read from the memory. The data read from the memory is input to a data creating unit that creates data for displaying on a CRT screen, and the data created by the data creating unit is supplied to the CRT terminal device via a buffer memory. A screen data address updating unit is provided to output the output for each cycle of the sequence time of the PC and output when the required number of designated screen positions arrives. The output of this updating unit is the second gate when there is no change data generation output. The gate of the circuit is opened and given to the switching unit, necessary screen data is taken out from the memory and supplied to the data creating unit.

According to the second aspect of the invention, the output transmitted for each cycle of the scanning time of the first aspect of the invention is transmitted as it is or is transmitted via a frequency dividing circuit (eg, if the frequency dividing ratio is 1/2, the scanning 2
A screen switching unit is provided, which is sent once per cycle.

F. Action When data is given to the all-point part state memory via the input processing unit, the contents of the memory at the address corresponding to the data are updated. On the other hand, when new change data arrives at the input processing unit, this data is preferentially read from the memory via the first gate circuit and displayed on the CRT terminal device. Also, when there is no change data for each cycle of the scanning time of the PC, the necessary screen data is read from the memory and displayed on the CRT terminal device. In the case of the second invention, when switching screens,
The screen switching signal is sent out quickly using the output of each cycle of the PC, and the screen data is switched via the frequency dividing circuit when displaying normal data.

G. Embodiment An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 1, 1 is input data (this data is a slave station having a plurality of equipment to be monitored and controlled (not shown))
From a centralized supervisory control device (not shown). } Is an input processing unit. Reference numeral 2 is an all-point portion state memory, and this memory 2 is a memory in which the CRT screen is divided into a predetermined number and data corresponding to the number of the divided areas is stored.
Predetermined data is read from the memory 2 by the memory switching unit 3. The data read from the memory 2 is input to the data creation unit 4 for displaying the data on the CRT. The embedded data created by the data creating unit 4 is supplied from the first-in first-out (FIFO) type buffer memory 5 to the CRT terminal device 7 via the converting unit 6.

Data input by the input processing unit 1 {state of each supervisory control target equipment in each slave station (for example, opening or closing of breaker)}
Change data generation signal 1a, which is the first and second control signals when there is a change in (the first control signal is created by being input from the centralized monitoring control device when the state of the equipment changes) and the input data State position address signal 1b (calculates the corresponding address of all-point state memory 2 from the slave station number and equipment number, which are the contents of the input data, and creates the second control signal), and sends these signals. 1a and 1b are first gate circuits 8
Given to. When the first gate circuit 8 receives the signal 1a, it opens the gate and sends out the signal 1b. The signal 1b is the OR circuit 9
Is given to the memory switching unit 3 via. Memory switching unit 3
Reads data from a predetermined address of the memory 2 according to the given signal 1b (number of data status position addresses) and supplies it to the data creating section 4.

The change data generation signal 1a is also supplied to the inhibition terminal of the second gate circuit 10, but the gate of the second gate circuit 10 is closed when this signal is present, so that no output signal is sent out. The second gate circuit 10 has a screen data address updating unit 11 (this updating unit 11 is a coefficient circuit (not shown) to which the sequence output signal of the PC is supplied, and a screen number corresponding memory to which the screen number command signal is supplied. (200 addresses) (not shown),
A 200-point corresponding memory address is divided by the output signal (8 bits) of the coefficient circuit for selection, and a 25-point address selected by the first selecting section is selected one by one. It is composed of a second selection section for sending an address update signal to the gate circuit 10. } Address update signal is sent out every sequence cycle time of the PC according to the screen number. Normally, there are a plurality of CRT screens, and in order to distinguish between them, a screen number is made to correspond to each screen, a screen number is designated, and a desired screen is displayed. Therefore, to switch to another screen, another screen number is designated. Therefore, the address update signal divides the data for one screen corresponding to the screen number command signal that specifies the screen number of the display screen with dozens of screens for each cycle of the PC sequence to obtain the desired data. The address is designated, and when the address update signal is given to the memory switching section 3 through the second gate circuit 10, the memory switching section 3 reads out predetermined data from the memory 2 and supplies it to the data creating section 4. To do.

Next, the operation of the above embodiment will be described.

When no data arrives at the input processing unit 1, the change data generation signal 1a is not sent from the input processing unit 1. Therefore, the first gate circuit 8 remains closed. Meanwhile, the second
Since the gate circuit 10 does not have the change data generation signal 1a, the gate is open. Therefore, an address update signal is supplied from the screen data address update unit 11 to the memory switching unit 3 via the second gate circuit 10 every time the sequence cycle of the PC is completed. Since the address of the desired data belonging to the screen is given to the address update signal, it is possible to know which address data is to be displayed. At this time, the memory switching unit 3 uses, for example, 25 points of embedded data for all points necessary for the screen from the state memory of all points of the memory 2, for example, 200 points for each cycle of the PC sequence.
The buffer memory 5 that is input to the buffer memory 5 through the screen-embedded data creation unit 4 one by one for each point is interposed is the data transmission speed to the CRT terminal device described in Problem 3 and the data update from the PC. This is to adjust the speed mismatch. Since the buffer memory 5 uses the first-in first-out (FIFO) method as described above, the screen update order set on the PC side can be exactly kept. Further, if this buffer memory capacity is set to 1 / n of the data of one screen, even if a failure occurs in one of the buffer memories, there will be a display error at n points and the error can be easily judged. Further, a failure of the screen-embedded data creation unit 4 and a conversion unit 6 which will be described later results in a display error of all data and can be more easily determined. This improves the reliability of the data. After that, the signal is converted by the data converter 6 into a signal suitable for the CRT terminal device, which is a measure for the problem (1). Further, the number of sequence processing steps in one cycle can be reduced to 1/8 by dividing 200 points into eight every 25 points. (Measures for problem (2).) Here, when the change data generation signal 1a is input to the first gate circuit 8, the gate of the first gate circuit 8 opens and the input data state position address signal 1b changes. It is supplied to the memory switching unit 3 through the first gate circuit 8. Memory switching unit 3 is an address signal
Data corresponding to the number of addresses of 1b is read from the memory 2 and input to the data creating unit 4, and the data is displayed on the predetermined screen position of the CRT terminal device 7 via the buffer memory 5 and the converting unit 6. Thereby, the priority display of the state change signal can be performed among the problems (5).

Next, another embodiment of the present invention will be described with reference to FIG. In FIG. 2, reference numeral 12 is a frequency dividing circuit that divides the signal transmitted at every cycle time of the PC. If the frequency dividing circuit 12 divides the time, for example, the frequency dividing ratio becomes 1/2, the PC Input to the third gate circuit 13 every two cycles of the sequence. The gate of the third gate circuit 13 is normally open, and the gate is closed when a screen switching signal sent when it is desired to update all the data at the time of screen switching is input. Therefore, normally, the signal obtained by dividing the PC sequence signal by the frequency dividing circuit 12 is applied to the screen data address updating unit 11 via the OR circuit 14, so that the address updating signal updates the screen relatively gently. However, when a switching signal is given to the fourth gate 15 in order to switch the screen to another screen, this gate is opened and the output signal for each cycle of the scanning time of the PC is directly input to the screen data address updating unit 11. When this signal is directly input to the update unit 11, the screen update speed is increased and new data is displayed quickly.

H. Effect of the Invention As described above, according to the present invention, the input / output methods and time characteristics of the PC and the CRT device may be inconsistent, the number of sequence steps may be relatively small, and a failure may occur. There are few missed errors at the time, and it is possible to display the changed data preferentially only when the changed data occurs, so that the response time can be greatly shortened. Further, the screen can be switched in a short time by inputting the screen switching signal when the user wants to see the necessary screen.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a block diagram showing an essential part of another embodiment of the present invention. 1 ... Input processing unit, 2 ... All point state memory, 3 ... Memory switching unit, 4 ... Data creating unit, 5 ... Buffer memory, 6 ... Conversion unit, 7 ... CRT terminal device, 8, 10,13,15 ...
... 1st to 4th gate circuits, 11 ... screen data address updating unit, 12 ... divider circuit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kiyoshi Aoki 638-48 Higashihara, Numazu City, Shizuoka Prefecture (56) References JP-A-58-54440 (JP, A) JP-A-58-115480 (JP, A) Special Open Sho-56-135235 (JP, A) Actual Open Sho-58-19306 (JP, U) Actual Open Sho-55-150447 (JP, U)

Claims (2)

[Claims] 1. A CRT display control device in which a programmable controller and a CRT display device are combined, processes input data, and when there is a change in the input data, a change data generation signal and an input data status position address signal. A first gate circuit that opens a gate when a change data generation signal transmitted from the input processing section is given, and a second gate circuit that closes the gate when there is the generated signal; When the CRT display screen of the CRT display device is divided into a predetermined number in advance and a memory in which data corresponding to the number of divisions is stored and the gate of the first gate circuit is opened, the input processing unit sends the data. An input data status position address signal is provided, and data is read from a predetermined address of the memory in response to the address signal. A switching unit, an output signal sent out every one cycle time of the programmable controller, and a command signal having a number given in advance on a screen displayed on the CRT display device are input, and the gate of the second gate circuit is opened. Then, the screen data address updating unit that gives a screen data address updating signal to the memory switching unit, and the memory switching unit reads data from the memory by the signal given through the first and second gate circuits A CRT display control device comprising: a CRT terminal device which is supplied to a creation unit and to which the data created by the data creation unit is supplied. 2. A CRT display control device in which a programmable controller and a CRT display device are combined to process input data, and when there is a change in the input data, a change data generation signal and an input data state position address signal. A first gate circuit that opens a gate when a change data generation signal transmitted from the input processing section is given, and a second gate circuit that closes the gate when there is the generated signal; When the CRT display screen of the CRT display device is divided into a predetermined number in advance and a memory in which data corresponding to the number of divisions is stored and the gate of the first gate circuit is opened, the input processing unit sends the data. An input data status position address signal is provided, and data is read from a predetermined address of the memory in response to the address signal. A switching unit; a frequency dividing circuit that divides the output signal of the programmable controller that is sent every sequence cycle time; a signal that is divided by the frequency dividing circuit; and an output signal that is sent every sequence cycle time. The switching unit that outputs when there is a control signal for switching to the screen displayed on the CRT display device, the output signal sent from this switching unit, and the command signal with the number given in advance to the screen displayed on the CRT display device. A screen data address updating unit that inputs a screen data address updating signal to the memory switching unit when the gate of the second gate circuit is opened, and the memory switching unit is supplied via the first and second gate circuits. And a CRT terminal device to which the data created by the data creation unit is supplied and which is supplied to the data creation unit CRT display controller.