JPH07104390B2 - Semiconductor memory device test method - Google Patents
Semiconductor memory device test methodInfo
- Publication number
- JPH07104390B2 JPH07104390B2 JP62333965A JP33396587A JPH07104390B2 JP H07104390 B2 JPH07104390 B2 JP H07104390B2 JP 62333965 A JP62333965 A JP 62333965A JP 33396587 A JP33396587 A JP 33396587A JP H07104390 B2 JPH07104390 B2 JP H07104390B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor memory
- power supply
- supply voltage
- test method
- memory device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Tests Of Electronic Circuits (AREA)
Description
【発明の詳細な説明】 〈産業上の利用分野〉 本発明は半導体記憶装置のテスト方法に関し、特には所
要時間の短縮を図ったテスト方法に関する。The present invention relates to a test method for a semiconductor memory device, and more particularly to a test method for shortening required time.
〈従来の技術〉 半導体基板上に256K,1Mビット等のメモリセルを作製し
た場合、出荷に際してこれらのメモリセルが所定の機能
を果し得るか否かのテストが実施される。<Prior Art> When memory cells of 256K, 1M bits or the like are manufactured on a semiconductor substrate, a test is performed at the time of shipment to determine whether or not these memory cells can fulfill a predetermined function.
従来から行われているテスト方法としては、ダイナミッ
クバーンイン装置を適用して行なう方法と、ICテスタを
用いる方法等がある。前者のテスト方法はテスト時間が
長く掛るのに比べて後者は短時間でテストすることがで
き、テストの内容については夫々特徴がある。Conventional test methods include a method using a dynamic burn-in device and a method using an IC tester. The former test method requires a long test time, whereas the latter test can be done in a short time, and each test method has its own characteristics.
〈発明が解決しようとする問題点〉 実際の半導体メモリチップの中には、本来配線を介して
印加される電圧によって、「０」又は「１」の論理値が
確定されるべき端子でありながら、製造工程時等の不良
により配線と端子との接続が不十分でないため電圧が印
加されず、論理値が確定しない端子（以下浮きノードと
呼ぶ）に起因する不良がしばしば生じる。この種の不良
は半導体装置にとって誤動作の原因となり、好ましくな
いが、特に半導体メモリにおいては記憶させたデータを
損なうことになり、避けねばならない。テスト段階で浮
きノードによる欠陥の検出も行われるが、浮きノード部
は電荷の蓄積に時間が掛り、そのためにテスト時間の長
いダイナミックバーンインや実装後のテスト等において
しか検出されず、テスト時間と不良解析に要する時間が
長くなってテストの効率が著しく悪くなるという問題が
あった。<Problems to be Solved by the Invention> In an actual semiconductor memory chip, although a logical value of “0” or “1” should be determined by the voltage originally applied through the wiring, Since a connection between the wiring and the terminal is not insufficient due to a defect during the manufacturing process, a voltage is not applied and a defect often occurs due to a terminal (hereinafter referred to as a floating node) whose logical value is not fixed. This kind of failure causes a malfunction in the semiconductor device and is not preferable, but especially in a semiconductor memory, it causes damage to the stored data and must be avoided. Defects are also detected by the floating node in the test stage, but it takes time for the floating node to accumulate charges, which is only detected in dynamic burn-in with a long test time or a test after mounting. There is a problem that the time required for analysis becomes long and the efficiency of the test remarkably deteriorates.
本発明は上記従来のテスト方法の問題点に鑑みてなされ
たもので、所要時間の短縮化を図った半導体記憶装置の
テスト方法を提供する。The present invention has been made in view of the above problems of the conventional test method, and provides a test method of a semiconductor memory device in which the required time is shortened.
〈問題点を解決するための手段〉 本発明は、半導体記憶装置に予め設定した規定電圧を越
える高い電源電圧を印加してスタンバイ状態に保ち、次
に規定電圧より低い電源電圧を印加してテスト信号を供
給することにより半導体記憶装置に浮きノードが存在し
ているか否かをテストする。<Means for Solving Problems> According to the present invention, a semiconductor memory device is applied with a high power supply voltage exceeding a preset voltage to maintain a standby state, and then a power supply voltage lower than the preset voltage is applied to perform a test. By supplying a signal, it is tested whether a floating node exists in the semiconductor memory device.
〈作用〉 半導体メモリに規定の電圧より充分高い電源電圧を印加
してスタンバイ状態にすることにより、浮きノードへの
電荷の蓄積が加速され、その直後に規定電圧より低い電
源電圧でテストパターンを実行することにより、浮きノ
ードに起因して生じる不良を短時間で検出できる。尚、
スタンバイ状態とは、各種クロック信号を電源電圧に保
った、動作時でない状態をいう。<Operation> By applying a power supply voltage that is sufficiently higher than the specified voltage to the semiconductor memory and putting it in the standby state, the accumulation of charges in the floating node is accelerated, and immediately after that, the test pattern is executed with the power supply voltage lower than the specified voltage. By doing so, a defect caused by the floating node can be detected in a short time. still,
The standby state is a state in which various clock signals are kept at the power supply voltage and not in operation.
〈実施例〉 １個のMOSトランジスタ及び１個の容量から各メモリセ
ルが構成されてなるDRAM（ダイナミックランダムアクセ
スメモリ）の推奨動作電源電圧がV1〜V2の範囲に設定さ
れているとする。このような半導体メモリに対して、テ
スト実行にあたってまず上記推奨動作電源電圧より充分
高い電圧VH（VH＞V1）を印加する。該高い電圧VHを印加
したスタンバイ状態でT0秒保持する。保持時間T0秒は浮
きノードに電荷を蓄積し得る時間に設定されるが、印加
電圧として推奨動作条件の電圧よりも充分に高い電圧を
設定しているため蓄積は著しく加速され、従来の規定電
源電圧を印加する場合に比べて著しく短絡される。上記
スタンバイ状態によって電荷の蓄積がなされた後、印加
電源電圧を上記低い側の規定電源電圧V2（V1＜V2）より
も低い電圧VLを印加し、この状態で従来のテスト方法と
同様にテストパターンを書込み、更にメモリの内容を読
み出して各メモリセルの良否を判定する。Recommended operating power supply voltage of the <Example> one MOS transistor and one DRAM consisting configured each memory cell from the capacity (dynamic random access memory) is to be set in the range of V 1 ~V 2 . When performing a test, a voltage V H (V H > V 1 ) sufficiently higher than the recommended operating power supply voltage is applied to such a semiconductor memory. In the standby state where the high voltage V H is applied, it is held for T 0 seconds. The holding time T 0 seconds is set to a time that allows charges to be accumulated in the floating node, but since the applied voltage is set to a voltage that is sufficiently higher than the voltage under the recommended operating conditions, the accumulation is significantly accelerated. It is significantly short-circuited as compared with the case of applying the power supply voltage. After the charge is accumulated in the standby state, the applied power supply voltage is applied with a voltage V L lower than the lower specified power supply voltage V 2 (V 1 <V 2 ), and in this state, the conventional test method is used. Similarly, the test pattern is written, and the contents of the memory are read to determine the quality of each memory cell.
上記テスト方法において、浮きノードが存在すれば上記
スタンバイ状態で蓄積された電荷は、たとえ低い電圧VL
が印加された状態になっても保持され、該当メモリセル
或いは周辺メモリセルに蓄積電荷による影響を及ぼし、
読出しデータとして所定の信号が得られず、不良が検出
される。図は上記テスト方法の手順を示す。In the above test method, if there is a floating node, the charge accumulated in the standby state is low voltage V L.
Is maintained even when applied, and the influence of accumulated charges on the corresponding memory cell or peripheral memory cell is exerted,
A predetermined signal cannot be obtained as read data, and a defect is detected. The figure shows the procedure of the above test method.
上記実施例はDRAMを挙げて説明したが、その他の半導体
メモリについても同様に適用することができる。Although the above embodiment has been described by taking the DRAM as an example, it can be similarly applied to other semiconductor memories.
〈効果〉 以上本発明によれば、半導体記憶装置に生じた特に浮き
ノードによる不良を短時間のテストで検出することがで
き、テスト時間と不良解析の時間を短縮することができ
る。<Effect> As described above, according to the present invention, it is possible to detect a defect caused by a floating node in a semiconductor memory device by a short-time test, and it is possible to shorten a test time and a defect analysis time.
図は本発明によるテスト方法の手順を示すフローチャー
トである。The figure is a flow chart showing the procedure of the test method according to the present invention.
Claims (1)
動作させる半導体メモリセルが形成された記憶装置に浮
きノードが存在するか否かをテストする方法において、 予め設定された規定電圧よりも高い電源電圧を印加して
半導体メモリセルをスタンバイ状態に保持し、該高電源
電圧印加後に規定電圧よりも低い電源電圧を印加してテ
スト信号を入力することを特徴とする、半導体記憶装置
のテスト方法。1. A method for testing whether or not a floating node exists in a memory device in which a semiconductor memory cell, which is operated by applying a power supply voltage within a specified voltage range, is tested. A semiconductor memory device in which a semiconductor memory cell is held in a standby state by applying a power supply voltage higher than the specified power supply voltage, and a test signal is input by applying a power supply voltage lower than a specified voltage after applying the high power supply voltage. Test method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62333965A JPH07104390B2 (en) | 1987-12-29 | 1987-12-29 | Semiconductor memory device test method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62333965A JPH07104390B2 (en) | 1987-12-29 | 1987-12-29 | Semiconductor memory device test method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01174989A JPH01174989A (en) | 1989-07-11 |
| JPH07104390B2 true JPH07104390B2 (en) | 1995-11-13 |
Family
ID=18271969
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62333965A Expired - Fee Related JPH07104390B2 (en) | 1987-12-29 | 1987-12-29 | Semiconductor memory device test method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07104390B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0457013A3 (en) * | 1990-04-16 | 1992-03-04 | National Semiconductor Corporation | Ferroelectric capacitor test structure for chip die |
| JP6900802B2 (en) * | 2017-06-28 | 2021-07-07 | 株式会社リコー | Control board, backup power supply method for control board, backup power supply program for control board |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61280582A (en) * | 1985-05-20 | 1986-12-11 | Sanyo Electric Co Ltd | Method for measuring mos semiconductive apparatus |
-
1987
- 1987-12-29 JP JP62333965A patent/JPH07104390B2/en not_active Expired - Fee Related
Non-Patent Citations (1)
| Title |
|---|
| 「マイクロコンピュータ基礎講座５テストと信頼性」ＰＰ．５３−５８オーム社昭和５７年４月２０日 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01174989A (en) | 1989-07-11 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |