JPH0698556A - Control circuit for power converter - Google Patents

Abstract

PURPOSE:To equalize the range of an output voltage to the range of a voltage, theoretically outputted, regardless of a dead time period. CONSTITUTION:Not the ON/OFF states of a PWM signal A from a PWM (pulse-width modulation) generating circuit 2 but the rise-up and fall-down of the signal are detected with a rise-up detecting circuit 3 and a fall-down detecting circuit 4, respectively. The ON/OFF of switching elements (e.g. S1 and S4) of a power converter 1 are controlled. Thus, the pulse widths of the waveforms of the PWM signal and the output voltage can be made equal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a voltage source power converter control circuit, and more particularly to a pulse width modulation (PWM) control circuit thereof.

[0002]

2. Description of the Related Art FIG. 13 shows a conventional example. As shown in the figure, semiconductor switches S1 to S such as transistors are provided.
6 and diodes D1 to D6 connected in antiparallel
And the voltage source power converter (inverter) 1 including the DC voltage source Ed, the semiconductor switch S of the upper and lower arms for each phase.
1 and S4, S2 and S5, S3 and S6 are alternately turned on and off to control the output voltage. Although the drawing is an example of three phases, it goes without saying that the present invention is not limited to this.
In such a voltage type power converter, it is necessary to prevent the semiconductor switches S1 and S4, S2 and S5, S3 and S6 of the upper and lower arms from being turned on at the same time, and one of the semiconductor switches of the upper and lower arms is turned off. After that, the other semiconductor switch is turned on after a fixed time (also referred to as dead time). In this case, there is a drawback that the output voltage has a waveform different from that of the PWM signal due to the influence of the dead time, and the voltage distortion rate of the output voltage increases.

As a method of improving the distortion of the output voltage waveform, a method of switching a wide control signal and a narrow control signal, which are modified in consideration of the influence of dead time, according to the current polarity to turn on and off the semiconductor switch. Is proposed. FIG. 14 is a block diagram showing such a conventional system, and FIG. 15 is a waveform diagram of each part for explaining the operation. Although FIG. 14 shows only one phase, the same applies to the other phases. Further, among the operation waveforms shown in FIG. 15, the PWM signal A,
The wide signal B and the narrow signal C indicate "1"("1" and "0" represent logical values 1 and 0, respectively) to turn on the semiconductor switch S1 and "0" to turn on S4. , D indicates "1" to turn on S1 and "0" to turn off, and E indicates "1" to turn on S4 and "0" to turn off.

When the PWM signal A output from the PWM generation circuit 2 is input to the wide signal generator 36, the PWM signal A
The wide-width signal B delayed by the dead time Td from the fall of the waveform of is output. When the PWM signal A is input to the narrow-width signal generator 37, the narrow-width signal C delayed from the rising of the waveform of the PWM signal A by the dead time Td is output. Here, when the current polarity is i (+) indicated by the arrow in FIG. 14, the changeover switch 38 is set to the wide signal generator 36 side. When the output signal of the changeover switch 38 is input to the short circuit prevention circuit 39, the signals D and E with the dead time Td secured are output, and the semiconductor switches S1 and S4 are turned on and off through the drive circuit 11.

If the potential difference between the negative side of the DC power supply voltage Ed of the voltage type power converter and the output voltage is V0, the current polarity is i.
When it is (+), V0 is determined by the on / off state of S1. When this voltage waveform of V0 is compared with the PWM signal A,
The whole is only delayed by the dead time Td, and the duty of “1” and “0” match the PWM signal A. Therefore, it becomes possible to improve the distortion of the output voltage. On the other hand, when the current polarity is i (-), the changeover switch 3
8 to the narrow signal generator 37 side. In this case, V0 is determined by the on / off state of S4. Therefore, even when the current polarity is i (-), V0 has the same waveform as when the current polarity is i (+), as shown in FIG.

[0006]

However, in the conventional control method, when the period of "1" of the PWM signal A becomes shorter than the dead time Td, the output C of the narrow signal generator 37 is always "0". Become. On the other hand, when the period of "0" of the PWM signal A becomes shorter than Td, the output B of the wide signal generator 36 is always "1". Therefore, when the pulse width of the PWM signal is narrow, the output voltage of the power converter is saturated. Therefore, there is a problem that the range of voltage that can be output is narrower than the range of voltage that the power converter can theoretically output. Further, a semiconductor switch such as a large-capacity transistor or GTO needs to secure an on period and an off period for a certain time (on minimum time, off minimum time) or more, but in the conventional control method, the short circuit prevention circuit 3 is used.
In some cases, the pulse widths of the output signals D and E of 9 become less than this fixed time. Therefore, there is a problem in that the semiconductor switch, which needs to secure the ON period and the OFF period for a certain time or more, cannot be used. Therefore,
An object of the present invention is to make the range of the output voltage equal to the range of theoretically output voltage regardless of the dead time period so as not to lower the capacity. In addition, if necessary, the pulse width of the input signal to the drive circuit should not be less than a fixed time, and it should be possible to use this for a semiconductor switch that needs to secure an ON period and an OFF period for a certain time or longer. To do.

[0007]

In order to solve such a problem, according to the first invention, in a control circuit for generating a PWM drive signal for turning on and off a semiconductor switch which constitutes a voltage type power converter, a PWM First and second detecting the rising edge and the falling edge of the signal respectively
Edge detecting means and first and second pulse detecting means for generating pulse signals of a predetermined width in accordance with the outputs of the first and second edge detecting means.
Second signal generating means, the first edge detecting means, and the second
When the current polarity is positive and the period in which the semiconductor switch of the upper arm should be turned off is less than or equal to a certain time, first and second delaying means for delaying the output from the edge detecting means by a certain time respectively, and outputting, First on-blocking means for preventing the semiconductor switch of the lower arm from turning on, and a semiconductor switch of the upper arm when the current polarity is negative and the period for which the semiconductor switch of the lower arm should be turned off is a fixed time or less. A second on-blocking means for preventing the current from turning on, and a signal of a predetermined width, which is generated depending on whether the current polarity is positive or negative and gives the moment when the semiconductor switch should be turned on or off, the current polarity is positive. When it is positive, the pulse signal generated at the moment when it should be turned on and off is selected, and when the current polarity is negative, the pulse signal generated when it is turned on and off when it is negative is selected. And a holding means for holding each pulse signal generated at the moment when it should be turned on or off by the signal selection means as a set input and a reset input, regardless of the pulse width of the PWM signal. Is characterized in that the drive signal of the semiconductor switch is generated so that the duty of the output voltage becomes equal to that of the output voltage.

According to the second aspect of the present invention, the control for generating the PWM drive signal for turning on and off the semiconductor switch which constitutes the voltage type power converter and is required to secure the ON period and the OFF period for a certain time or more. In the circuit, PWM
Pulse width correcting means for correcting the pulse width of the PWM signal so that the pulse of the signal becomes a certain width or more, and first and second detections for detecting the rising and falling edges of the output signal from the pulse width correcting means, respectively. Means and this first, second
First and second signal generating means for respectively generating pulse signals of a predetermined width according to the output from the detecting means;
When the current polarity is positive and the period when the semiconductor switch of the upper arm should be turned off is constant, the first and second delay means delay the pulse signal of a predetermined width from the second detection means and output the pulse signal with a predetermined time delay. First ON blocking means for preventing the semiconductor switch of the lower arm from being turned on when the time is less than or equal to time, and when the current polarity is negative and the period when the semiconductor switch of the lower arm should be turned off is less than or equal to a certain time. A second ON blocking means for preventing the semiconductor switch of the upper arm from turning on, and a signal of a predetermined width which is generated depending on whether the current polarity is positive or negative and gives the moment when the semiconductor switch should be turned on or off. , When the current polarity is positive, select the pulse signal that is generated at the moment when it should be positive and on when it is positive, and when the current polarity is negative, it is generated at the moment when it should be on and off when it is negative The semiconductor switch is provided with a signal selecting means for selecting a loose signal and a holding means for setting each pulse signal generated at the moment when it should be turned on or off by the signal selecting means as a set input and a reset input. It is characterized in that a period is secured for a certain period of time, and a drive signal for the semiconductor switch is generated so that the output signal from the pulse width correcting means and the duty of the output voltage become equal.

Further, according to the third aspect of the present invention, a control for generating a PWM drive signal for turning on and off a semiconductor switch which constitutes a voltage type power converter and is required to secure an ON period and an OFF period for a certain time or more. In the circuit, PW
First signal generating means for detecting a rising edge of the M signal to generate a pulse signal of a predetermined width, and second signal generating means for detecting a falling edge of the PWM signal to generate a pulse signal of a predetermined width.
And the pulse width of the PWM signal is constant when the pulse width of the PWM signal (the period when the semiconductor switch of the upper arm should be turned on) is more than a certain time, the pulse width of the PWM signal is constant. When the time is less than or equal to the time, the first signal selecting means for selecting the pulse signal generated after a certain time from the fall of the PWM signal and the pulse width of the PWM signal (the period when the semiconductor switch of the lower arm should be turned on) are more than the certain time Second signal selecting means for selecting a pulse signal generated at the time of falling of the PWM signal, and selecting a pulse signal generated for a certain time after the rising of the PWM signal when the pulse width of the PWM signal is less than or equal to the certain time. And the first and second delay means for delaying the respective outputs from the first and second signal selecting means by a fixed time respectively, and the current polarity is positive. A first ON blocking means for preventing the lower arm semiconductor switch from turning on when the upper arm semiconductor switch should be turned off for a certain time or less, and when the current polarity is negative and the lower arm When the period when the semiconductor switch of should be turned off is less than a certain time,
Second to prevent the upper arm semiconductor switch from turning on
Of the ON blocking means and a signal of a predetermined width that is generated depending on whether the current polarity is positive or negative and gives the moment when the semiconductor switch should be turned on or off. Select the pulse signal generated at the moment when it should be turned off, and turn it on when the current polarity is negative,
Third selection of pulse signal generated at the moment to turn off
Signal selecting means and holding means for inputting and resetting respective pulse signals generated at the moment of turning on or off, and when the pulse width of the PWM signal is a certain time or less, the semiconductor switch is on. Further, the semiconductor switch drive signal is generated so that the duty of the PWM signal is equal to the duty of the output voltage when the off period is a constant time and the pulse width of the PWM signal is a constant time or more.

[0010]

(1) About the first invention When the current flows from the power converter to the load (when the current polarity is positive), the waveform of the output voltage is determined by turning on and off the semiconductor switch of the upper arm. Therefore, when the current polarity is positive, the on / off timing of the upper and lower arm semiconductor switches should be determined with reference to the on / off timing of the upper arm semiconductor switch. by the way,
Since it is necessary to secure the dead time Td from turning off the semiconductor switch of the lower arm to turning on the semiconductor switch of the upper arm, the semiconductor of the lower arm is changed at the moment when the PWM signal changes from "0" to "1". Switch off, P
The delay is smallest when the upper arm semiconductor switch is turned on after Td when the WM signal changes from "0" to "1".
Then, the Td when the PWM signal changes from "1" to "0"
When the semiconductor switch of the upper arm is turned off later, the period of "1" of the PWM signal becomes equal to the on period of the semiconductor switch of the upper arm, and the period of "0" of the PWM signal becomes equal to the off period of the semiconductor switch of the upper arm. . Similarly, it is necessary to secure Td from the time when the semiconductor switch of the upper arm is turned off to the time when the semiconductor switch of the lower arm is turned on. Therefore, the semiconductor signal of the lower arm is turned on when the PWM signal is from "1" to "0". It will be 2Td after the change to "". However, when the period of "0" of the PWM signal is 2Td or less,
Since the timing to turn off comes before the timing to turn on, the semiconductor switch in the lower arm does not turn on.

On the other hand, when the current flows from the load to the power converter (when the current polarity is negative), the waveform of the output voltage is determined by the on / off state of the semiconductor switch of the lower arm. Therefore, when the current polarity is negative, the on / off timing of the upper and lower arm semiconductor switches should be determined based on the on / off timing of the lower arm semiconductor switch. By the way, since it is necessary to secure the dead time Td from turning off the semiconductor switch of the upper arm to turning on the semiconductor switch of the lower arm, at the moment when the PWM signal changes from "1" to "0", the upper arm The delay is the smallest when the semiconductor switch of the lower arm is turned on and the semiconductor switch of the lower arm is turned on after Td when the PWM signal changes from "1" to "0". Then, when the upper arm semiconductor switch is turned off after Td when the PWM signal changes from "0" to "1", the PWM signal is "0" and the lower arm semiconductor switch is on, and the PWM signal is "1". And the off period of the lower arm semiconductor switch are equal to each other. Similarly, since it is necessary to secure Td from when the semiconductor switch of the lower arm is turned off to when the semiconductor switch of the upper arm is turned on, the semiconductor switch of the upper arm is turned on when the PWM signal is from "0" to "1". Changed to 2 "
It is after Td. However, the period of "1" of the PWM signal is 2
When it is equal to or lower than Td, the timing to turn off comes before the timing to turn on, so the semiconductor switch of the upper arm does not turn on. By determining the on / off timing of the semiconductor switch as described above, even when the pulse width of the PWM signal is narrower than Td, the dead time is secured and the PWM signal and the output voltage waveforms of "1" and "0" are The duty can be made equal, and further, the delay of the output voltage waveform with respect to the PWM signal can be set to the theoretical minimum value Td.
Can be

(2) Second Invention When the period of "1" and "0" of the PWM signal is Tmin (on-minimum time or off-minimum time, whichever is longer), "1" and "0". 0 "period is T
By providing a pulse width correction circuit that corrects the pulse width so that the pulse width becomes min, and by configuring in the same manner as in (1) above, when the current polarity is positive, both the ON period and the OFF period of the upper arm semiconductor switch are always Tmin. Can be secured. By the way, in the case of (1) above, the current polarity is positive and PW
When the period of "0" of the M signal is Tx0, the on period Twl of the semiconductor switch of the lower arm is Twl = Tx0-2Td (1), and depending on the size of Tx0, Twl <Tmin (2) ) Becomes, and the ON period of the semiconductor switch of the lower arm is changed to Tmi
In some cases, it cannot be set to be n or more. From the equation (1), the ON period of the semiconductor switch of the lower arm becomes Tmin or longer when Tx0> Tmin + 2Td (3), and Tmin <n · Td (n = 1, 2 ...) (4) ) For the integer n satisfying the relation, the lower arm semiconductor switch may be turned on only when the condition of Tx0> (n + 2) · Td (5) is satisfied.

Therefore, the semiconductor switch of the lower arm is turned on at the moment when the period of “0” of the output signal of the pulse width correction circuit becomes (n + 2) · Td (“0” of the output signal of the pulse width correction circuit is turned on). It is best to turn off the semiconductor switch of the upper arm after (n + 1) Td when the output signal of the pulse width correction circuit changes from "1" to "0" when the period is (n + 2) · Td or less). There is little delay. When the semiconductor switch of the upper arm is turned on after (n + 1) Td when the output signal of the pulse width correction circuit is changed from "0" to "1", the output signal of the pulse width correction circuit is "1".
And the ON period of the semiconductor switch of the upper arm, the period of "0" of the output signal of the pulse width correction circuit and the OFF period of the semiconductor switch of the upper arm are equal to each other. Further, since it is necessary to secure Td until the semiconductor switch of the lower arm is turned on until the semiconductor switch of the upper arm is turned on, the semiconductor switch of the lower arm is turned off because the output signal of the pulse width correction circuit is " N changed from "0" to "1"
It is after Td.

On the other hand, even when the current polarity is negative, by performing the same operation as in the case of (1), it is possible to always secure Tmin for both the ON period and the OFF period of the semiconductor switch of the lower arm. However, in the case of (1), when the current polarity is negative and the period of "1" of the PWM signal is Txl, the on period Twu of the semiconductor switch of the upper arm is Twu = Txl-2Td (6) Depending on the size of Txl, Twu <Tmin (7), and the ON period of the semiconductor switch of the upper arm is Tmi.
In some cases, it cannot be set to be n or more. From the equation (6), the ON period of the upper arm semiconductor switch becomes Tmin or more when Txl> Tmin + 2Td (8), and the upper arm semiconductor switch is turned ON when Txl> (n + 2). -Td ... Only when the condition (9) is satisfied.

Therefore, the semiconductor switch of the upper arm is turned on at the moment when the period of "1" of the output signal of the pulse width correction circuit becomes (n + 2) Td (when the output signal of the output signal of the pulse width correction circuit is "1"). It is best to turn off the semiconductor switch of the lower arm after (n + 1) Td when the output signal of the pulse width correction circuit changes from "0" to "1" when the period is (n + 2) · Td or less). There is little delay. When the semiconductor switch of the lower arm is turned on after (n + 1) Td when the output signal of the pulse width correction circuit is changed from "1" to "0", the output signal of the pulse width correction circuit is "1".
And the OFF period of the lower arm semiconductor switch, and the period of "0" of the output signal of the pulse width correction circuit is equal to the ON period of the lower arm semiconductor switch. Further, since it is necessary to secure Td until the semiconductor switch of the upper arm is turned on until the semiconductor switch of the lower arm is turned on, the semiconductor switch of the upper arm is turned off because the output signal of the pulse width correction circuit is " N changed from "1" to "0"
It is after Td. As described above, the dead time is secured by deciding the on / off timing of the semiconductor switches, and both the upper and lower semiconductor switches have their on periods,
The off period is set to Tmin or less, and the pulse width correction signal (m in FIG. 5) and the output voltage waveform “1”,
The duty of “0” can be made equal, and further, the delay of the output voltage waveform with respect to the PWM signal can also be set to the theoretical minimum value (n + 1) Td.

(3) Third Aspect of the Invention A first aspect of the present invention provides a timing for turning on and off a semiconductor switch.
When the “0” period of the PWM signal is Tmin or more in the reference time of, the moment when the PWM signal changes from “0” to “1” is selected, and when the “0” period of the PWM signal is Tmin or less. Is the Tmi when the PWM signal changes from "1" to "0"
Choose after n. Further, in the second reference time, when the period of the PWM signal "1" is Tmin or more, the moment when the PWM signal changes from "1" to "0" is selected, and the period of the PWM signal "1" is When it is less than Tmin, the time after Tmin when the PWM signal changes from "0" to "1" is selected. The first reference time and the second reference time thus selected are
It is the same as the timing of the rising edge and the falling edge of the pulse width correction circuit in the case of (2) above. Therefore, by using these reference times instead of the pulse width correction circuit in (2), the same action and effect as in (2) can be obtained.

[0017]

1 is a block diagram showing an embodiment of the present invention. As is clear from the figure, in this embodiment, the power converter 1, the PWM generation circuit 2, the rising edge detection circuit 3 for detecting a rising edge and generating a differential pulse (a pulse signal of a narrow width), and the falling edge Fall detection circuit 4 that detects and generates a differential pulse, a terminal that outputs a differential pulse after Td when the differential pulse is input, and 2Td
Delay circuit 5 having terminal for outputting differential pulse later
A, 5B, monostable circuit 6 with pulse width 2Td
A, 6B, gate circuits 7A, 7B, changeover switch 8
A, 8B, 8C, 8D, the contact of the changeover switch is determined according to the current polarity of the power converter (the contact of the switch can be changed is that both outputs of the monostable circuits 6A, 6B are "0"). When) the switching judgment device 9, the holding circuit 10A which becomes "1" at the rising edge of the set signal and becomes "0" at the rising edge of the reset signal,
10B (all the holding circuits shown in the following figures have the upper input as a set input and the lower input as a reset input), a drive circuit 11, a current detector 12, a load 13, and the like. Note that, although a transistor is shown as an example of the semiconductor switch in the same drawing, it goes without saying that the present invention is not limited to this.

The operation of FIG. 1 will be described with reference to FIG. 2, the PWM signal A is "1" to indicate that the semiconductor switch S1 is on, and "0" to indicate that S4 is on. The output signal Q of the holding circuit 10A is "1" to indicate S1. Is on, "0" indicates off,
The output signal R of the holding circuit 10B is "1" and S4 is turned on.
"0" indicates that it is off. At the moment when the PWM signal A output from the PWM generation circuit 2 changes from "0" to "1", the rising edge detection circuit 3 outputs a differential pulse F, and the PWM signal A also changes from "1" to "0". At the moment of change, the fall detection circuit 4 outputs the differential pulse J. The delay circuit 5A outputs the differential pulse G to the upper side after Td when the rising edge detection circuit 3 outputs the differential pulse F, and outputs the differential pulse H to the lower side after 2Td. The monostable circuit 6A includes the rising edge detection circuit 3
Outputs the differential pulse F, the pulse width of "1" is 2T
The pulse signal I of d is output.

Similarly, the delay circuit 5B outputs the differential pulse K to the upper side after Td when the fall detection circuit 4 outputs the differential pulse J, and outputs the differential pulse L to the lower side after 2Td. When the fall detection circuit 4 outputs the differential pulse J, the monostable circuit 6B outputs a pulse signal M having a pulse width of "1" of 2Td. Gate circuit 7
A, when the output signal M of the monostable circuit 6B is "1", blocks the passage of the signal H from the delay circuit 5A, and the gate circuit 7B delays when the output signal I of the monostable circuit 6A is "1". Block the passage of signal L from circuit 5B.

When the current polarity of the power converter is i (+), the set signal of the holding circuit 10A is the changeover switch 8
G is selected by A, and K is selected by the changeover switch 8C as the reset signal. In addition, the holding circuit 10
For the set signal of B, P is selected by the changeover switch 8D, and for the reset signal, F is selected by the changeover switch 8B. The output signals Q and R of the holding circuits 10A and 10B are drive signals of the semiconductor switches S1 and S4, and the semiconductor switches S1 and S4 are controlled to be turned on and off via the drive circuit 11. DC voltage E of voltage source power converter
When the potential difference between the negative side of d and the output voltage is V0, when the current polarity is i (+), the semiconductor switch S1 is turned on and off,
That is, V0 is determined by the drive signal Q. Therefore, regardless of the pulse width of the PWM signal A, the voltage waveform of V0 only lags the dead time Td with respect to the PWM signal A as a whole, and the duty of "1" and "0" becomes equal to that of the PWM signal A.

On the other hand, when the current polarity is i (-), O is selected by the changeover switch 8A as the set signal of the holding circuit 10A, and the reset signal is changedover switch 8C.
Selects J. As for the set signal of the holding circuit 10B, K is selected by the changeover switch 8D,
As the reset signal, G is selected by the changeover switch 8B. When the current polarity is i (-), S0 is turned on and off, that is, V0 is determined by the drive signal R. Therefore, when the current polarity is i (−), as in the case of i (+), the voltage waveform of V0 is only delayed by the dead time Td with respect to the PWM signal A as a whole, and is “1”, “0”. Has the same duty as the PWM signal A. In FIG. 1, the polarity is judged from the actual current value detected by the current detector 12 provided for controlling and protecting the voltage source power converter 1, but instead of the actual current value, It goes without saying that the current command value may be used.

FIG. 3 is a block diagram showing a modification of FIG. As is clear from the figure, this is the changeover switches 8A, 8B, 8C, 8D and the holding circuit 1 shown in FIG.
Instead of 0A, 10B, holding circuits 14A, 14B, 1
4C, 14D and change-over switches 15A, 15B are provided to change the holding circuits 14A, 14B.
A, holding circuit 14C, 14D changeover switch 15B
The feature is that they are placed in front of each. Since the operation is exactly the same as in the case of FIG. 1, the description thereof will be omitted.

FIG. 4 is a block diagram showing another modification of FIG. Instead of the monostable circuit 6A shown in FIG. 1, a holding circuit 16A which uses the output signal F of the rising edge detection circuit 3 as a set signal and the output signal H of the delay circuit 5A as a reset signal is used, and the monostable circuit 6B Instead, a holding circuit 16B that uses the output signal J of the fall detection circuit 4 as a set signal and the output signal L of the delay circuit 5B as a reset signal is used. Figure 1 shows the basic operation
Since it is the same as, the description is omitted. Further, as in the case of FIG. 3, the relationship between the changeover switch and the holding circuit can be reversed.

FIG. 5 is a block diagram showing another embodiment of the present invention. This is because when the pulse width correction circuit 17 is provided in the rear stage of the PWM generation circuit 2 shown in FIG. 1 and the differential pulse is input in the front stage of the delay circuit 5A, nTd (n is 1 in all operating waveforms). A delay circuit 18A for outputting a differential pulse is provided later, and a delay circuit 18B having the same function as the delay circuit 18A is provided in the preceding stage of the delay circuit 5B. Further, instead of the monostable circuits 6A and 6B, the pulse width is ( n + 2) Td monostable circuit 19A,
The feature is that 19B is provided.

The pulse width correction circuit 17 is a circuit that secures the periods of "1" and "0" of the PWM signal for a certain time Tmin or longer. For example, as shown in a specific example of FIG. 3, a rising edge detection circuit 27 having the same function as that of No. 3, a falling edge detection circuit 28 having the same function as that of the falling edge detection circuit 4, and a pulse width of Tmin.
Monostable circuits 32A, 32B and AND circuit 2
It is composed of 9, 31, 35, knot circuits 30, 33, an OR circuit 34, and the like. FIG. 7 shows operation waveforms of respective parts of the pulse width correction circuit shown in FIG. 6, and FIG. 8 shows operation waveforms of respective parts of FIG. In the operation waveform of FIG. 8, m is “1” to indicate that the switch S1 is on, “0” to indicate that S4 is on, and γ is “1” to indicate that the switch S1 is on and “0” is off. Δ is “1” and the switch S4 is on,
"0" indicates that it is off.

At the moment when the output signal m of the pulse width correction circuit 17 changes from "0" to "1", the rising edge detection circuit 3 outputs a differential pulse n, and the output signal m changes from "1" to "0". At the moment of change, the fall detection circuit 4 outputs the differential pulse u. The delay circuit 18A outputs the differential pulse p after nTd when the rising edge detection circuit 3 outputs the differential pulse n. The delay circuit 5A outputs the differential pulse q to the upper side after Td when the delay circuit 18A outputs the differential pulse p, and outputs the differential pulse r to the lower side after 2Td. The output signal t of the monostable circuit 19A is "1" when the rising edge detection circuit 3 outputs the differential pulse n.
Has a pulse width of (n + 2) Td.

The delay circuit 18B outputs the differential pulse v after nTd when the fall detection circuit 4 has output the differential pulse u. The delay circuit 5B outputs the differential pulse w to the upper side after Td when the delay circuit 18B outputs the differential pulse v, and outputs the differential pulse x to the lower side after 2Td. The output signal y of the monostable circuit 19B becomes a pulse signal whose pulse width of "1" is (n + 2) Td when the fall detection circuit 4 outputs the differential pulse u. The gate circuit 7A blocks passage of the output signal r from the delay circuit 5A when the output signal y of the monostable circuit 19B is "1", and the gate circuit 7B outputs the output signal t of the monostable circuit 19A of "1". At this time, the passage of the output signal x from the delay circuit 5B is blocked. Changeover switches 8A, 8B,
The operations after 8C and 8D are the same as in the case of FIG.

That is, the pulse width of the PWM signal A is Tm.
When it is more than in, the DC voltage Ed of the voltage type power converter is
The potential difference V0 between the negative side and the output voltage is only delayed by (n + 1) Td from the PWM signal A regardless of the current polarity, and is equal to the duty of "1" or "0" of the PWM signal A. In addition, the PWM signal A "1", "0"
Is less than Tmin, V0 is "1",
The waveform has a period of "0" secured for Tmin. Also in this embodiment, as in the case of FIG. 3, the relationship between the changeover switch and the holding circuit can be reversed.

FIG. 9 is a block diagram showing a modification of FIG. Instead of the monostable circuit 19A shown in FIG. 5, a holding circuit 20A that uses the output signal n of the rising edge detection circuit 3 as a set signal and the output signal r of the delay circuit 5A as a reset signal is used, and the monostable circuit 19B is used. Instead of, the holding circuit 20B using the output signal u of the fall detection circuit 4 as the set signal and the output signal x of the delay circuit 5B as the reset signal is used, and its operation is the same as in FIG. Therefore, the details are omitted.

FIG. 10 is a block diagram showing still another embodiment of the present invention. As is apparent from the figure, in this embodiment, the contact point of the input signal is switched according to the power converter 1, the PWM generating circuit 2, the rising detection circuit 3, the falling detection circuit 4, and the pulse width of the PWM signal A. Changeover switches 21A, 21B, delay circuits 5A, 5B and 1
8A 18B, a delay circuit 24A that outputs a differential pulse after Tmin (on-minimum time or off-minimum time, whichever is longer) when the differential pulse is input
24B, gate circuits 7A and 7B, changeover switch 8
A, 8B, 8C, 8D, switching determination device 9, holding circuit 1
0A, 10B, 22A, 22B, 23A, 23B, a drive circuit 11, a current detector 12, a load 13, and the like. Although a transistor is shown as an example of a semiconductor switch in the figure, the invention is not limited to this.

The operation of FIG. 10 will be described with reference to FIG. In the operation waveform of FIG. 11, k is "1" to indicate that the semiconductor switch S1 is on and "0" to be off, and l is "1" to indicate S4 is on and "0" is off. It is shown that. The changeover switch 21A outputs the PWM signal when the PWM signal “0” period has passed Tmin or more (the output signal f of the holding circuit 22B is “0”).
At the moment when the signal becomes "1" (the rising edge detection circuit 3 outputs the differential pulse F), the differential pulse S is output, and when the period of "0" of the PWM signal is Tmin or less, it is "1".
When it becomes, the differential pulse S is output after Tmin (the delay circuit 24B outputs the differential pulse e) from the moment when the PWM signal becomes “0”.

The delay circuit 18A includes a changeover switch 21A.
Outputs the differential pulse T nTd after the differential pulse is output, and the delay circuit 24A outputs the differential pulse W after Tmin when the changeover switch 21A outputs the differential pulse. The delay circuit 5A outputs the differential pulse U to the upper side of the delay circuit 18A after the time Td when the differential circuit 18A outputs the differential pulse T, and outputs the differential pulse V to the lower side of the time after 2Td. The output signal X of the holding circuit 22A becomes "1" when the changeover switch 21A outputs the differential pulse, and becomes "0" when the delay circuit 24A outputs the differential pulse W. The output signal Y of the holding circuit 23A is the output of the changeover switch 21A.
When it outputs a differential pulse S, it becomes "1", and when V becomes a differential pulse, it becomes "0".

When the PWM signal "1" period has elapsed Tmin or more (the output signal X of the holding circuit 22A is "0"), the changeover switch 21B is the moment when the PWM signal becomes "0". A differential pulse (falling detection circuit 4 outputs a differential pulse J) to
When the period of "1" of the WM signal becomes "0" when Tmin is less than or equal to Tmin, Tmi starts from the moment when the PWM signal becomes "1".
After n, the differential pulse is output (the delay circuit 24A outputs the differential pulse W). The delay circuit 18B outputs the differential pulse a after nTd time when the changeover switch 21B outputs the differential pulse Z, and the delay circuit 24B outputs the differential pulse e after Tmin when the changeover switch 21B outputs the differential pulse Z. The delay circuit 5B is the delay circuit 18B.
Outputs the differential pulse a to the upper side Td after the differential pulse a is output, and outputs the differential pulse d to the lower side 2d after the time Td.

The output signal f of the holding circuit 22B becomes "1" when the changeover switch 21B outputs the differential pulse, and becomes "0" when the delay circuit 24B outputs the differential pulse. The output signal g of the holding circuit 23B becomes "1" when the changeover switch 21B outputs the differential pulse, and becomes "0" when d becomes the differential pulse. The gate circuit 7A has a delay circuit 5 when the output signal g of the holding circuit 23B is "1".
When the output signal Y of the holding circuit 23A is "1", the gate circuit 7B blocks passage of the output signal V of A and the delay circuit 5B.
Of the output signal d is blocked. Changeover switch 8
The operation after A, 8B, 8C, and 8D is the same as that in the case of FIG. 5, and the operation is also the same as that of FIG. Tmin is nTd
If it does not matter, the delay circuits 24A, 24
Instead of the output signals W and e of B, the delay circuits 18A and 18A
The output signals T and a of B may be used. Also in this embodiment, as in the case of FIG. 3, the relationship between the changeover switch and the holding circuit can be reversed.

FIG. 12 is a block diagram showing a modification of FIG. This is the holding circuit 22A, 22B shown in FIG.
Instead of, the monostable circuits 25A and 25B having a pulse width of Tmin are used, and the monostable circuits 26A and 26B having a pulse width of (n + 2) Td are used instead of the holding circuits 23A and 23B. Since the basic operation is the same as the operation shown in FIG. 10, its details are omitted.

[0036]

According to the present invention, since the drive signal of the semiconductor switch is generated with reference to the rising edge and the falling edge of the PWM signal, the PWM signal and the output voltage are irrespective of the dead time Td period. "1" and "0" have the same duty, and the advantage is that the range of voltage that can be output can be made equal to the range of voltage that the power converter can theoretically output. In addition, the drive signal of the semiconductor switch is "1",
Since the drive signal is generated so that the period of "0" is Tmin (on-minimum time or off-minimum time, whichever is longer), it is necessary to secure the on-state and off-state for a certain period of time or more. It is also possible to use a semiconductor switch with a certain type. Further, when the pulse width of the PWM signal is Tmin or more, the drive signal is generated so that the duty of the PWM signal is equal to that of "1" and "0" of the output voltage, so that the output voltage with less distortion is obtained. be able to.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is an operation waveform diagram of FIG.

FIG. 3 is a block diagram showing a modified example of FIG.

FIG. 4 is a block diagram showing another modification of FIG.

FIG. 5 is a block diagram showing another embodiment of the present invention.

6 is a circuit diagram showing a specific example of the pulse width correction circuit shown in FIG.

FIG. 7 is a waveform chart of each part of FIG.

FIG. 8 is an operation waveform diagram of FIG.

9 is a block diagram showing a modified example of FIG.

FIG. 10 is a block diagram showing still another embodiment of the present invention.

11 is an operation waveform diagram of FIG.

12 is a block diagram showing a modified example of FIG.

FIG. 13 is a block diagram showing a general example of a power converter.

FIG. 14 is a block diagram showing a conventional example of a power converter control circuit.

FIG. 15 is a waveform chart of each part for explaining the operation of FIG.

[Explanation of symbols]

1 ... Voltage type power converter, 2 ... PWM generating circuit, 3, 27
... rising edge detection circuit, 4, 28 ... falling edge detection circuit, 5A, 5B, 18A, 18B, 24A, 24B ... delay circuit, 6A, 6B, 19A, 19B, 25A, 25
B, 26A, 26B, 32A, 32B ... Monostable circuit, 7A, 7B ... Gate circuit, 8A, 8B, 8C, 8
D, 15A, 15B, 21A, 21B ... Changeover switch, 9 ... Changeover determination device, 10A, 10B, 14A, 1
4B, 16A, 16B, 20A, 20B, 22A, 22
B, 23A, 23B ... Holding circuit, 11 ... Driving circuit, 12
... current detector, 13 ... load, 17 ... pulse width correction circuit,
29, 31, 35 ... AND circuit, 30, 33 ... Not circuit, 34 ... OR circuit.

Claims (3)

[Claims] 1. A control circuit for generating a PWM drive signal for turning on and off a semiconductor switch which constitutes a voltage-type power converter, wherein first and second detecting a rising edge and a falling edge of a PWM signal, respectively. Edge detecting means,
The outputs from the first and second signal generating means, which generate pulse signals of a predetermined width in accordance with the output of the second edge detecting means, and the outputs from the first edge detecting means and the second edge detecting means, are delayed by a predetermined time. When the current polarity is positive and the period for which the upper arm semiconductor switch should be turned off is less than a certain time, the lower arm semiconductor switch is prevented from turning on. When the current polarity is negative and the period when the semiconductor switch of the lower arm should be turned off is less than a fixed time,
Second to prevent the upper arm semiconductor switch from turning on
Of the ON blocking means and a signal of a predetermined width that is generated depending on whether the current polarity is positive or negative and gives the moment when the semiconductor switch should be turned on or off. Select the pulse signal generated at the moment when it should be turned off, and turn it on when the current polarity is negative,
It is provided with signal selecting means for selecting a pulse signal generated at the moment to turn off, and holding means for setting each pulse signal generated at the moment to turn on or off by the signal selecting means as a set input and a reset input. , PWM
A control circuit for a power converter, which generates a drive signal for a semiconductor switch such that the PWM signal and the output voltage have the same duty regardless of the pulse width of the signal. 2. A control circuit for generating a PWM drive signal for turning on and off a semiconductor switch, which constitutes a voltage type power converter and is required to secure an ON period and an OFF period for a certain time or more, Pulse width correcting means for correcting the pulse width of the PWM signal so that the pulse has a width equal to or more than a certain width, and first and second detecting means for detecting rising and falling of the output signal from the pulse width correcting means, respectively. A first and second signal generating means for generating a pulse signal of a predetermined width in accordance with the outputs from the first and second detecting means, and a pulse of a predetermined width from the first and second detecting means. When the current polarity is positive and the period in which the semiconductor switch of the upper arm should be turned off is less than or equal to a certain time, the first and second delaying means for delaying and outputting the signals by a certain time respectively. Means for preventing the semiconductor switch of the arm from turning on, and a semiconductor switch of the upper arm when the current polarity is negative and the period for which the semiconductor switch of the lower arm should be turned off is less than a fixed time. A second on-blocking means for preventing the current from turning on, and a signal of a predetermined width, which is generated depending on whether the current polarity is positive or negative and gives the moment when the semiconductor switch should be turned on or off, the current polarity is positive. Selects the pulse signal generated at the moment when it should be turned on and off when it is positive, and selects the pulse signal generated at the moment when it should be turned on and off when it is negative when the current polarity is negative Means, and holding means for respectively inputting and resetting the respective pulse signals generated at the moment when the signal selecting means should be turned on or off, and the semiconductor switch is turned on. A control circuit for a power converter, which secures a certain period of time and an off period and generates a drive signal of a semiconductor switch so that the output signal from the pulse width correction means and the duty of the output voltage become equal. . 3. A control circuit for generating a PWM drive signal for turning on and off a semiconductor switch, which constitutes a voltage type power converter and is required to secure an ON period and an OFF period for a certain time or more, First signal generating means for detecting a rising edge and generating a pulse signal of a predetermined width, second signal generating means for detecting a falling edge of the PWM signal and generating a pulse signal of a predetermined width, and pulse of the PWM signal When the width (the period when the upper arm semiconductor switch should be turned on) is more than a certain time, the pulse signal generated at the rising edge of the PWM signal is selected, and when the pulse width of the PWM signal is less than the certain time, the falling edge of the PWM signal is selected. And a pulse width of the PWM signal (a semiconductor switch in the lower arm is turned on). If the pulse width of the PWM signal is less than a certain time, the pulse signal generated after a certain time from the rising of the PWM signal is selected. Second signal selecting means for selecting, first and second delaying means for delaying respective outputs from the first and second signal selecting means by a fixed time respectively, and outputting when current polarity is positive A first on-blocking unit for preventing the semiconductor switch of the lower arm from turning on when the period when the semiconductor switch of the arm should be turned off is less than a certain time; and a semiconductor switch of the lower arm when the current polarity is negative. Second on-blocking means for preventing the semiconductor switch of the upper arm from being turned on when the period to be turned off is equal to or less than a fixed time, and the current polarity is generated depending on whether the polarity is positive or negative. When the current polarity is positive, the pulse signal generated at the moment when the semiconductor switch should be turned on or off is selected from the signals of a predetermined width that gives the moment when the semiconductor switch should be turned on or off. When negative, third signal selecting means for selecting a pulse signal generated at the moment when it should be turned on and off when negative, and set input and reset of each pulse signal generated at the moment when it should be turned on or off Holding means for inputting, when the pulse width of the PWM signal is a fixed time or less, the semiconductor switch has an ON period and an OFF period of a fixed time, and when the pulse width of the PWM signal is a fixed time or more, the PWM signal and the output A control circuit for a power converter, which generates a drive signal for a semiconductor switch so that the duty of a voltage becomes equal.