JPH0697841A - Digital logic circuit - Google Patents

Abstract

PURPOSE:To improve the reliability of a digital logic circuit by reducing much the probability of a case where an error can not be informed at the due time. CONSTITUTION:A digital logic circuit consists of a 1st AND circuit GA1 which inputs the signals a1 and b1 of one of the 1st and 2nd redundant signals, a 1st OR circuit G01 which inputs the signals a0 and b0 of the other of the 1st and 2nd redundant signals, the 2nd-5th AND circuits GA2-GA5 which input a signal c1 received from the circuit GA1 and the signal b0 of the 2nd redundant signal, a signal c0 received from the circuit G01 and the signal b1 of the 2nd redundant signal, the signals c1 and b1, the signals c0 and b0 respectively, a 2nd OR circuit G02 which inputs the signals y11 and y10 received from the 2nd and 3rd AND circuits GA2 and GA3, and a 3rd OR circuit G03 which inputs the signals y01 and y00 received from the 4th and 5th AND circuits GA2 AND GA3 respectively.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital logic circuit applied to a system for handling digital signals such as a computer and a memory circuit, and more specifically, for example, a 2-rail parity check result output from a parity checker. The present invention relates to a digital logic circuit which is convenient for constructing an error signal output circuit in which is controlled by a 2-rail strobe signal input from the outside.

[0002]

2. Description of the Related Art FIG. 5 is a block diagram showing an example of an error signal output circuit as applied to a parity checker. In the figure, M1 is a parity checker,
N-bit data DA applied via the data bus
And a data parity PT corresponding to the data are input, a parity check is performed, and the check result is output as a 2-rail redundant signal (s1, s0). Here, the redundant code signal by the two rails output from the parity checker M1 defines s1, s0 = (0, 1), (1, 0) as a code word, and when it is a code word, no error occurs. Meaning,
s1, s0 = (0,0), (1,1) are defined as non-code words, and when they are non-code words, they mean an error.

M2 is a digital logic circuit which is the object of the present invention, and is used here as an error signal output circuit. Redundant code signals s1 and s0 from the parity checker M1 are applied to terminals a1 and a0. Redundant strobe signals PENA1 and PENA0 of two rails are externally applied to terminals b1 and b0, respectively. FIG. 6 shows terminals a1 and a0 and a terminal b in the digital logic circuit M2.
It is a figure which shows the meaning of the signal output to the output terminals y1 and y0 with respect to the combination of each signal (redundant signal of 2 rails) applied to 1 and b0.

In this digital logic circuit M2, as shown here, for example, when (b1, b0) = (1,0), the error of (a1, a0) is valid (b1, b0) = (0, In the case of 1), the error of (a1, a0) has a meaning such as invalid, and the parity check results PER1, PER0 of the two rails are obtained at the timing of the redundant strobe signal.
Is configured to output.

FIG. 7 is a block diagram showing an example of a simple logic circuit that can be considered when realizing the combination shown in FIG. In this example, the AND circuit G1 that inputs the signals of the terminals a1 and b1 and the OR circuit G2 that inputs the signals of the terminals a0 and b0 are used.

[0006]

FIG. 8 shows the combination of each signal (2-rail redundant signal) applied to the terminals a1 and a0 and the terminals b1 and b0 in the configuration of FIG.
It is a figure which shows the state of the signal output to the output terminals y1 and y2 in detail. The digital logic circuit as shown in FIG. 7 has the following problems.

(1) The signal applied to the input terminal b1 is
When it becomes “0” for some reason, the error applied to the terminals a1 and a0 should be validated, but when (a1, a0) = (1,1), As shown in * 1 part of 8,
0) = (0,1), which results in an output meaning no error.

(2) When the signal applied to the input terminal b0 is fixed to "1" for some reason, the error applied to the terminals a1 and a0 should be valid. However, when (a1, a0) = (0, 0), (y1,
y0) = (0,1), which results in an output meaning no error.

The present invention has been made in view of such a point, and in a digital logic circuit which handles a redundant signal by two rails, due to a defect of wiring for guiding an input signal or the like, the input terminal as described above is used. The signal applied to
Even if an accident that is fixed to "0" or "1" occurs, it is necessary to provide a digital logic circuit that does not cause no error by a strobe signal or the like externally applied to the signal from the parity checker. To aim.

[0010]

According to the present invention which achieves such an object, the redundant signals (a1, a) by the first two rails are provided.
0), and the redundant signal (b1,
b0) and receives the redundant signal (y1,
y0) for outputting a digital logic circuit,
A first AND circuit that inputs one signal (a1) of the first redundant signals and one signal (b1) of the second redundant signals, and the other signal (a0) of the first redundant signals A first OR circuit that inputs the other signal (b0) of the second redundant signals, a signal (c1) from the first AND circuit, and the other signal (b0) of the second redundant signals. And a third AND circuit for inputting the signal (c0) from the first OR circuit and one signal (b1) of the second redundant signals, Signal (c1) from the AND circuit of
A fourth logical product circuit for inputting one of the redundant signals (b1), a signal (c0) from the first logical sum circuit, and the other signal (b0) for the second redundant signal. And a signal (y11) from the second AND circuit
And a signal (y10) from the third AND circuit and a second OR circuit from which a signal (y0) from the fourth AND circuit (y0) is input.
1) and a third logical sum circuit for inputting the signal (y00) from the fifth logical sum circuit are provided, and the signal from the second logical sum circuit and the signal from the third logical sum circuit are described above. It is a digital logic circuit characterized by being obtained as a redundant signal (y1, y0) by a third two-rail.

[0011]

The first AND circuit and the first OR circuit receive the first and second redundant signals respectively, take the logical product and the logical sum, and output the two-rail redundant signal. . Second
~ The fifth AND circuit and the second and third OR circuits are
A 2-to-2 wire type code checker is configured, and the redundant signal (b1, b0) by the second two rails is, for example, a strobe signal, and the parity is valid when (1, 0).
When (0, 1) means that the parity is invalid, and the signal from the second OR circuit and the signal from the third OR circuit are used as the redundant signal (y1, y0) by the third two rails. Output.

[0012]

An embodiment of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a configuration block diagram showing an embodiment of the present invention. In the digital logic circuit of the present invention, the first
Redundant signals (a1, a0) by the second two rails, the redundant signals (b1, b0) by the second two rails corresponding to the strobe signals are received, and the redundant signals (y1, y0 by the third two rails are received. ) Is assumed to be a logic circuit that outputs.

GA1 is a first first AND circuit, which inputs one signal (a1) of the first redundant signals and one signal (b1) of the second redundant signal and logically ANDs them. Take
The signal c1 is output. GO1 is a first OR circuit,
The other signal (a0) of the first redundant signals and the other signal (b0) of the second redundant signals are input, the logical sum thereof is taken, and the signal c0 is output.

CHK is the first AND circuit GA1, the first
2 lines 2 for receiving the output signals c1 and c0 of the OR circuit GO1 and the redundant signals (b1 and b0) by the second two rails.
It is a pairwise code checker. In this two-wire two-pair code checker, GA2 is a second AND circuit, which outputs the signal (c1) from the first AND circuit GA1 and the other signal (b0) of the second redundant signals. It is input and the logical product of these signals is taken and the signal y11 is output.

GA3 is a third logical product circuit, which inputs the signal (c0) from the first logical sum circuit GO1 and one signal (b1) of the second redundant signals, and logically products these signals. To output a signal y10. GA4 is a fourth AND circuit, which inputs the signal (c1) from the first AND circuit GA1 and one signal (b1) of the second redundant signals and calculates the logical product of these signals. The signal y01 is output. GA5
Is a fifth AND circuit, which receives the signal (c0) from the first OR circuit GO1 and the other signal (b0) of the second redundant signals, calculates the logical product of these signals, and outputs the signal. Outputs y00.

GO2 is a second logical sum circuit, which inputs the signal (y11) from the second logical product circuit GA2 and the signal (y10) from the third logical product circuit GA3, and logically sums these signals. And outputs the signal y1. Further, GO3 is a third logical sum circuit, which is a signal (y01) from the fourth logical product circuit GA4 and a signal (y0) from the fifth logical product circuit GA5.
0) is input and the logical sum of these signals is taken to obtain the signal y0.
Is output.

Here, the signal from the second OR circuit GO2 and the signal from the third OR circuit GO3 are the second and third signals.
It is designed to be output as a redundant signal (y1, y0) by the rail. FIG. 2 shows the redundant signal (a1, a0) by the first two rails and the redundant signal (b by the second two rails in the digital logic circuit configured as described above.
1, b0) and a redundant signal (y1, y0) by a third two-rail output based on each of these signals.

As is apparent from this figure, the redundant signals (b1, b1) by the second two rails corresponding to the strobe signal are provided.
0) is (0,1), that is, the parity is invalid, and the redundant signal (b1, b0) is (1,0), that is, the parity is valid and the parity is normal. , Both show no error (y1, y0) =
The redundant signal of (1, 0) is output. In other cases, a redundant signal indicating (y1, y0) = (0,0) or (1,1) indicating an error is output.

Next, in the case where the digital logic circuit according to the present invention having such a configuration is applied to a parity checker as shown in FIG. 5 (this is referred to as case 2), the digital logic circuit of FIG. In comparison with the case of applying (this is referred to as case 1), its effect is considered. For the parity checker (error detector) M1, not being able to notify the occurrence of an error is the most damaging in a system to which it is applied. Therefore, here, in the case where the parity checker M1 outputs errors (0,0) and (1,1), the second redundant signal PE
Consider the failure rate from the path through which NA1 and PENA0 are introduced to the path through which the third redundant signals PER1 and PER0 are output.

Now, the parity checker M1 shown in FIG.
If the failure rate inside the IC is Rin and the failure rate outside the IC is Rout, each wiring has a fixed failure of "0" and a failure of "1". And a fixed fault, and it is assumed that they occur with the same probability, and the first AND circuit, the first
If each output signal (c1, c2) of the logical sum circuit of is an error, its output is (0, 0) with the same probability (0.5),
It is assumed that there is an input of n-bit data and parity so as to be (1,1).

At this time, in case 1 the output (PER
The probability that (1, PER0) cannot notify an error is (1/2) * Rout * 0.5 * 2 = 0.5Rout from FIG. FIG. 3 shows the output (PE
R1, PER0) is a combination of signals for obtaining the number of cases in which an error cannot be notified (signals S1, S0 from the parity checker and strobe signals PENA1, PE).
It is a figure which shows (combination with NA0). In this figure, each signal PENA1, PENA0, c1, c0, y1
Regarding the wirings of 1, y10, y01, y00, consider fixing “0” and fixing “1”.

FIG. 4 shows the output (PE
It is a figure which shows the case where an error cannot be notified to R1, PER0). From this figure, in the case of Case 2, the probability that the outputs (PER1, PER0) cannot report an error is (1/2) * Rin * 0.5 * 10 = 2.5Rin.

In general, when focusing on one wiring and discussing the failure rate of the output end of the element that drives it by including it in the failure rate of the wiring, the IC is compared with the failure rate of one wiring inside the IC. Failure of one external wiring is large. Therefore, 0.5 * Rout >> 2.5Rin, which makes it possible to significantly reduce the probability that an error cannot be notified when an error should be notified.

[0024]

As described in detail above, according to the present invention, a signal (PENA) corresponding to a strobe signal is obtained.
1, PEN A0), and the wiring to which each signal (c1, c0, y11, y10, y01, y00) output in the internal circuit is guided, is fixed to "0" or "1". In such a case, it is possible to reduce the probability that the redundant signal that should otherwise be output cannot be output.

Therefore, by applying the digital logic circuit of the present invention to the error detection circuit, the probability that the error cannot be notified when the error should be notified can be greatly reduced and the reliability can be improved.

[Brief description of drawings]

FIG. 1 is a configuration block diagram showing an embodiment of the present invention.

2 is a circuit diagram of a digital logic circuit of FIG.
The redundant signals (a1, a0) by the rails, the redundant signals (b1, b0) by the second two rails, and the redundant signals (y by the third two rails that are output based on these signals).
It is a figure which shows the relationship with (1, y0).

FIG. 3 shows an output (PER1, P
It is a figure which shows the combination of the signal for calculating | requiring the number when (ER0) cannot notify an error.

FIG. 4 is an output (PER1, PER) obtained from FIG.
It is a figure showing a case where an error cannot be notified to 0).

FIG. 5 is a configuration block diagram showing an example of an error signal output circuit as applied to a parity checker.

FIG. 6 is a diagram showing the meaning of signals output to output terminals y1 and y0 for combinations of signals applied to terminals a1 and a0 and terminals b1 and b0 in the digital logic circuit M2 of FIG.

7 is a block diagram showing an example of a simple logic circuit that can be considered when realizing the combination shown in FIG.

8 is a diagram showing a configuration of FIG. 7 in which terminals a1 and a0 and a terminal b are provided.
It is a figure which shows in detail the state of the signal output to the output terminals y1 and y2 with respect to each combination of the signals applied to 1 and b0.

[Explanation of symbols]

 GA1 1st 1st AND circuit GO1 1st OR circuit CHK 2-line 2-pair code checker GA2 2nd AND circuit GA3 3rd AND circuit GA4 4th AND circuit GA5 5th AND circuit GO2 second OR circuit GO3 third OR circuit

Claims (2)

[Claims] 1. Redundant signals (a1, a) by the first two rails.
0) is input, and the redundant signals (b1, b0) of the second two rails are received, and the redundant signals (y1, y0) of the third two rails are output. A first AND circuit for inputting one signal (a1) of the redundant signals and one signal (b1) of the second redundant signals, and the other signal (a0) of the first redundant signal and the second signal A first logical sum circuit for inputting the other signal (b0) of the redundant signals, and a signal (c1) from the first AND circuit and the other signal (b0) for the second redundant signal. A second logical product circuit for inputting the signal (c0) from the first logical sum circuit and one signal (b1) of the second redundant signals, and a first logical product circuit Fourth logical product circuit for inputting the signal (c1) from the product circuit and one signal (b1) of the second redundant signals A fifth logical product circuit for inputting the signal (c0) from the first logical sum circuit and the other signal (b0) of the second redundant signals, and the signal (y11 from the second logical product circuit). ) And the signal (y10) from the third AND circuit, the second OR circuit, the signal (y01) from the fourth AND circuit and the signal (y00) from the fifth AND circuit. And a signal from the second logical sum circuit and a signal from the third logical sum circuit are used as redundant signals (y1, y) by the third two rails.
0) A digital logic circuit characterized by being obtained as 0). 2. Redundant signals (a1, a) by the first two rails.
0) is the signal from the parity checker, the second 2
2. The digital logic circuit according to claim 1, wherein the redundant signals (b1, b0) by the rail are strobe signals given from the outside.