JPH0697813A - Logical operation unit - Google Patents

Abstract

PURPOSE:To provide a logical operation unit which can work at a high speed with high reliability by using the 1st and 2nd MOS transistors TR which open and close the section between the 1st input and output respectively and a 3rd MOS TR which opens and closes the section between a power supply and the output. CONSTITUTION:An NMOS TR T1 opens and closes the section between the 1st input, the inverse of A and the 1st output, the inverse of Q with the 2nd input B used as the input of a gate electrode. A PMOS TR T2 opens and closes the section between the input, the inverse of A and the output, the inverse of Q with the 3rd input, the inverse of B used as the input of the gate electrode. A PMOS TR T3 opens and closes the section between a power supply VCC and the output, the inverse of Q with the 2nd input B used as the input of the gate electrode. The signal, the inverse of Q is shown as '-Q=-A.-B'. Therefore a signal passes through only a single TR between the input and the output so that the delay time is reduced. Furthermore the crosstalk noises can be eliminate between the wirings adjacent to each other as long as the positive and negative signal lines are set in parallel to each other. Thus the occurrence of malfunctions can be prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logical operation unit, and more particularly to a logical operation unit which is a differential output type using a transfer gate composed of MOS transistors and is a basic constituent element of a digital information processing apparatus.

[0002]

2. Description of the Related Art Generally, a digital LSI represented by a microprocessor or the like is constructed by combining a large number of logical operation units such as NAND gates, NOR gates and inverters.

Typical CMO in a conventional logical operation unit
The two-input NAND gate or NOR gate having the S structure is composed of two P-type MOS transistors and two N-type MOS transistors. In addition, the inverter is composed of one P-type MOS transistor and one N-type MOS transistor.
AND gates and OR gates are NAND gates and NOR gates.
It was realized by connecting an inverter to each output of the gate.

[0004]

The above-mentioned conventional logical operation unit is a logical operation unit such as a NAND gate, an AND gate and an OR gate having a CMOS structure, in which an input signal is output after passing through at least two MOS transistors. However, there is a drawback in that the delay time is large and the operation speed is low because Further, since the arrangement of the input / output wirings is not always regular, if the logic amplitude decreases and the signal changes sharply with the progress of miniaturization of the device structure due to the high integration of LSI, the wiring between the adjacent wirings However, there is a drawback that crosstalk noise is generated and malfunction easily occurs and reliability is low.

An object of the present invention is to eliminate the above-mentioned conventional drawbacks and provide a high-speed and highly reliable logical operation unit.

[0006]

According to a first aspect of the present invention, there is provided a logical operation unit which opens and closes between a first input and an output and uses a second input as an input of a gate electrode. Between the first MOS transistor and the second MOS transistor of the second conductivity type that opens and closes between the first input and the output and uses the third input as the input of the gate electrode, and between the power supply and the output. And a third MOS transistor of the second conductivity type which opens and closes and uses the second input as the input of the gate electrode.

Further, the logic operation unit of the second invention comprises a first MOS transistor of a first conductivity type which opens and closes between the first input and the negative output by the second input, and a first power supply. Second conductive type second and third MOS transistors connected in series between the negative input and the negative output by the second input and the first clock signal, and the third input and the positive output A second MOS transistor of a second conductivity type that opens and closes with a fourth input, and a series that opens and closes between a second power supply and the positive output with the fourth input and a second clock signal. Fifth and sixth MOS transistors of the first conductivity type connected,
A seventh MOS transistor of a first conductivity type that opens and closes between the negative output and a third power supply by the first clock signal, and the first output between the positive output and the third power supply. 8th M of the first conductivity type that opens and closes according to the clock signal of
And an OS transistor.

[0008]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 shows a first embodiment of a logical operation unit of the present invention, (A) is a circuit diagram, and (B) is a truth table.

As shown in FIG. 1, the logical operation unit of this embodiment comprises an N-type MOS transistor T1 and P-type MOS transistors T2 and T3.

Next, the operation of this embodiment will be described.

The N-type MOS transistor T1 conducts when a high potential of logic "1" is applied to its gate, and opens when a low potential of logic "0" is applied. P type M
The OS transistors T2 and T3 operate in the opposite manner to the N-type MOS transistor T1.

First, second and third input signals A shown below
If four kinds of logic signals of I, B and BI are given, MO
The S transistors T1, T2 and T3 perform the operation according to the truth table shown in FIG. 1B and output the output signal QI.

[0014]

Here, the symbol "x" indicates the open state, and
The symbol "-" indicates a conductive state. As a result, the output signal QI becomes "0" only when the input signal AI = "0" and the input signal B = "1". Sunahachi,
The logical operation shown in the following equation is performed.

[0016]

Next, a second embodiment of the present invention will be described.

2A and 2B show a second embodiment of the present invention. FIG. 2A is a circuit diagram and FIG. 2B is a truth table.

This logical operation unit has a complementary relationship with the circuit of FIG. 1, and the N-type MOS transistor T1 in FIG.
To P-type MOS transistor T4
The transistors T2 and T3 are N-type MOS transistors T
5, T6, and the power source is grounded. In addition, first, second and third input signals A, BI,
Give B.

[0020]

As a result, the operation according to the truth table shown in FIG. 2B is performed and the output signal Q is output. The output signal Q is "1" only when the input signals A and B are "1".
Becomes That is, the logical operation shown in the following equation is performed.

Q = A · B Next, a third embodiment of the present invention will be described.

FIG. 3 shows a third embodiment of the present invention, (A) is a circuit diagram, and (B) is a truth table.

In this logical operation unit, the circuits shown in FIGS. 1 and 2 are combined, and the output terminal is connected to the power supply voltage VC.
It has the function of precharging to about 1/2 of C. That is, N-type MOS transistors T8, T9, T10
And a P-type MOS transistor T7 are provided for this function.

Next, the operation of this embodiment will be described.

First, prior to the operation, the clock signal CL
When K is given, the positive output terminal and the negative output terminal are 1/2 VCC
Will be precharged. Next, the clock signal CLK
When returning from 1'to '0', the logical operation is started. Figure 3
When four kinds of logic signals shown in (B) are given, the MOS transistors T1, T3, T4, T6 operate according to the truth table shown in FIG. 3 (B), and the positive and negative output signals Q,
Output QI.

As a result, the positive and negative output terminals respectively output the logical operation results shown in the following equations.

[0028]

In this case, "1" of the output signal is 1/2 VC
It shows that it changes from C to VCC, and the output signal is "0".
Means to change from 1/2 VCC to the ground potential.

Next, a fourth embodiment of the present invention will be described.

FIG. 4 is a circuit diagram showing a fourth embodiment of the present invention.

In this logical operation unit, the first and second logical operation units 1 and 2 shown in FIG. 3 are connected in two stages in series, and the positive and negative outputs of the logical operation unit 2 are used as input signals to the differential circuit 3. Has been done.

A more complicated logical operation is realized by the three signals A1, B1 and B2.

Next, the operation of this embodiment will be described.

First, in the first logical operation unit 1, the input signal A
1 and B1 as inputs, and a complementary output signal Q shown in the following equation
1 and Q1I are generated.

[0036]

The second logical operation unit 2 includes the first logical operation unit 1
Complementary output signals Q1 and Q1I of input terminals A and
It is input to AI and the logical operation shown in the following equation is executed.

[0038]

The output signals Q2 and Q2I are logic "1".
In the case of, it changes from 1 / 2VCC to VCC, and logic '
In the case of 0 ', it changes from 1/2 VCC to the ground potential.

Complementary output signals Q2 of the first logical operation unit 2
Q2I is input to the differential amplifier 3. The differential amplifier 3 is
The difference between these two input signals Q2 and Q2I is amplified and an output signal Q3 is generated.

FIG. 5 is an operation waveform diagram of the logical operation unit of this embodiment shown in FIG.

As shown in FIG. 5, the clock signal CLK
Is "1", the first and second logical operation units 1 and 2 are
Output is precharged to 1/2 VCC. When the clock signal CLK becomes "0", the logical operation is started. If the result is '1', the signals Q2, Q2I change as shown by the solid line, and if it is '0', the signals Q2, Q2.
2I changes as shown by the dashed line. Differential amplifier 3
Is a signal Q2, Q2 that changes slowly with the time constant determined by the conduction resistance of the MOS transistor and the input capacitance and wiring capacitance.
I is amplified to generate an output signal Q3 that changes abruptly.

By changing the connection between the first and second logical operation units 1 and 2, various logical operations can be realized. For example, if the output terminals Q and QI of the first logical operation unit 1 are connected to the input terminals AI and A of the second logical operation unit 2, respectively, the logical operation shown in the following equation becomes possible.

[0044]

Further, the number of serially connected stages of the logic operation unit is not limited to two, and the number of stages can be further increased to realize a complicated logic operation.

[0046]

As described above, the logic operation unit of the present invention can realize the logic operation of two logic signals by three MOS transistors, and the logic operation unit of a MOS transistor through which a signal passes from input to output. Since the number is reduced to one half of the conventional one, the delay time is shortened and the operation speed is improved. Further, since the positive and negative signal lines are wired in parallel, the crosstalk noise between the adjacent wirings can be canceled by the positive and negative signals, so that there is an effect that malfunction can be prevented and reliability can be improved.

[Brief description of drawings]

FIG. 1 is a circuit diagram and a truth table showing a first embodiment of a logical operation unit of the present invention.

FIG. 2 is a circuit diagram and a truth table showing a second embodiment of the logical operation unit of the present invention.

FIG. 3 is a circuit diagram and a truth table showing a third embodiment of the logical operation unit of the present invention.

FIG. 4 is a circuit diagram and a truth table showing a fourth embodiment of the logical operation unit of the present invention.

FIG. 5 is a waveform diagram showing an example of the operation of the logical operation unit according to the fourth embodiment.

[Explanation of symbols]

 1 1st logic operation unit 2 2nd logic operation unit 3 Differential circuit T1-T10 MOS transistor

Claims (3)

[Claims] 1. A first conductivity type first M, which opens and closes between a first input and an output and uses the second input as an input of a gate electrode.
An OS transistor, a second MOS transistor of the second conductivity type that opens and closes between the first input and the output, and uses the third input as the input of the gate electrode, and between the power supply and the output. And a third MOS transistor of a second conductivity type which is opened / closed and has the second input as an input of a gate electrode. 2. A first conductivity type first MOS transistor which opens and closes between a first input and a negative output by a second input, and a first power supply and the negative output which are connected between the first power supply and the negative output. The second and third MOS transistors of the second conductivity type connected in series, which are opened / closed by the second input and the first clock signal, and the fourth input is opened / closed between the third input and the positive output. A fourth MOS transistor of a second conductivity type; and a first conductivity type of a fourth series connected to open and close between the second power supply and the positive output by the fourth input and the second clock signal. Fifth and sixth MOS transistors, a seventh MOS transistor of the first conductivity type that opens and closes between the negative output and the third power supply by the first clock signal, the positive output and the third Of the first conductivity type that is opened and closed by the first clock signal between the Logic unit, characterized in that it comprises a MOS transistor. 3. The logic operation unit according to claim 1 and 2 which are connected in series, and the positive output of the logic operation unit according to claim 2 which is one of the first and second. And a differential amplifier having a negative output as an input.