JPH0697465A - Fabrication of semiconductor mechanical sensor - Google Patents

Abstract

PURPOSE:To provide a method of fabrication of a semiconductor mechanical sensor capable of ensuring high sensitivity or miniaturization of the sensor avoiding destruction of a thin-walled distortion generating portion. CONSTITUTION:Before a back chief surface of a semiconductor substrate 41 (including an epitaxial layer 42) is rendered to first etching to form a lower separation groove 10, a resist film 49 is rendered to photopatterning on a chief surface of the semiconductor substrate 41 excepting an upper separation groove formation intended region. Accordingly, there is eliminated a procedure where a predetermined region of the semiconductor substrate 41 is thin-walled through the first etching, and thereafter the resist film 49 is applied by spinning on the chief surface of the semiconductor substrate 41 for photopatterning. Thus, the thin-walled portion is prevented from being destroyed owing to vacuum chucking of a wafer upon the resist film 49 being spinning applied.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor acceleration sensor or a semiconductor pressure sensor (hereinafter collectively referred to as a semiconductor dynamic sensor).

[0002]

2. Description of the Related Art A conventional method for manufacturing a semiconductor dynamic sensor is shown in FIGS. First, as shown in FIG. 10, a wafer 40 having an n-type epitaxial layer 42 on a p-type substrate 41 is prepared, a p ⁺ diffusion layer 43 which is a piezoresistive region is formed, and is used as an electrode contact during electrochemical etching. The n ⁺ diffusion layer 44 is formed. Subsequently, a plasma nitride film (P-SiN) 45 is formed on the back surface of the wafer 40, and a predetermined patterning is performed by photoetching.

Next, as shown in FIG. 11, the surface of the wafer 40 is adhered to the alumina support substrate 46 while being protected by the wax W, immersed in an etching solution, and the n ⁺ diffusion layer 44 is energized for electrochemical etching. Then, the lower isolation trench 10 is formed in the p-type substrate 41. Next, as shown in FIG.
5 is removed, a resist 49 is applied to the front surface of the wafer 40 for photo patterning, and then a resist 50 is applied to the entire back surface of the wafer 40.

Next, as shown in FIG. 13, a resist film 49 is formed.
The upper isolation trench 51 is formed by etching the epitaxial layer 42 from the opening. Next, as shown in FIG. 14, the resists 49 and 50 are peeled off, and the wafer cutting process is performed.

[0005]

In recent years, there has been a demand for high sensitivity or miniaturization of the sensor. For that purpose, it is effective to reduce the thickness of the thin strain element 52 in which the piezoresistive region 43 is formed. . However, according to the method for manufacturing the semiconductor dynamic sensor described above, after etching the substrate 41 in FIG. 11 to make a part of the epitaxial layer 42 thin, a resist 49 is spun on the surface of the epitaxial layer 42 in FIG. In order to apply, it is necessary to vacuum chuck the central portion of the wafer 40 on a spinning table,
As a result, as the epitaxial layer 42 becomes thinner,
There is a problem that the thin portion of the epitaxial layer 42 is damaged by the vacuum pressure. Therefore, according to the conventional manufacturing method, the thin wall flexure portion 52 is required to have a minimum wall thickness that can withstand the vacuum chuck in the resist coating step for photo patterning after etching the substrate 41 (for example, several +
.mu.m), and it was not possible to achieve high sensitivity by further thinning the thin strained portion 52.

The present invention has been made in view of the above problems, and it is an object of the present invention to provide a method for manufacturing a semiconductor dynamic sensor, which is capable of increasing the sensitivity or downsizing the sensor while avoiding damage to the thin strained portion. Its purpose is.

[0007]

A method of manufacturing a semiconductor dynamic sensor according to the present invention comprises a photo-patterning step of covering a front main surface of a semiconductor substrate with a resist film except the surface of an upper separation groove forming region, and thereafter, A first etching step of etching a predetermined region of the back main surface of the semiconductor substrate to a predetermined depth to form a lower isolation trench under the upper isolation trench formation-scheduled region and under the thin-walled strained portion formation region. ,
The upper main surface of the semiconductor substrate is etched from the opening of the resist film to form an upper isolation groove that communicates with the lower isolation groove, and the thin isolation strain portion is formed in the thin-wall strain occurrence area to be formed by the isolation grooves. And a second etching step for partitioning and forming.

[0008]

As described above, in the method for manufacturing the semiconductor dynamic sensor of the present invention, the back main surface of the semiconductor substrate is first etched to form the lower portion of the upper isolation groove forming region and the thin strained portion forming region. Prior to forming the lower isolation trench in the lower portion, the resist film is photo-patterned on the front main surface of the semiconductor substrate excluding the upper isolation trench formation scheduled region. There is no need to perform photo-patterning by spin-coating a resist film on the front main surface of the semiconductor substrate after thinning the region where the strained portion is to be formed, as in the prior art.

Therefore, it is possible to avoid the vacuum chucking of the wafer during the spin coating of the resist film from damaging the thinned upper separation groove formation-scheduled regions and thin-walled strained portion formation-scheduled regions. As a result, it is possible to realize high sensitivity of the sensor by further reducing the thickness of the thin-walled strain generating portion (for example, several μm), and to reduce the size of each portion.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a semiconductor acceleration sensor to which the present invention is applied will be described below with reference to the drawings. FIG. 1 shows a perspective view of this semiconductor acceleration sensor, FIG. 2 shows a plan view of the semiconductor acceleration sensor, and FIG. 3 shows a cross section taken along the line AA of FIG.
This sensor is used in the ABS system of an automobile.

A square plate-shaped silicon chip 2 is bonded onto a square plate-shaped base 1 made of Pyrex glass. The silicon chip 2 has a rectangular frame-shaped first supporting portion 3 whose back main surface is joined to the pedestal 1, and the first supporting portion 3 is formed by using four sides of the silicon chip 2. The upper separation groove 4 is formed inside the first support portion 3 of the silicon chip 2.
a, 4b, 4c, 4d and the lower separation groove 10 are provided as recesses, and the upper separation grooves 4a, 4b, 4c, 4d and the lower separation groove 10 communicate with each other to form a through groove penetrating the chip 2. . A C-shaped upper separation groove 4d formed in the rectangular frame-shaped first supporting portion 3 and a lower separation groove 10 below the upper separation groove 4d.
The thick-walled U-shaped second support portion 11 and the thick-walled connecting portion 1
2 is divided and formed, and the second support portion 11 is connected to the first support portion 3 by the connection portion 12. Furthermore, the second support portion 1
A thin thin strain element 5, 6, 7, 8 is extended from the inner side surface of 1, and a thick square weight portion 9 is connected to the tip of the thin strain element 5, 6, 7, 8. Has been done.

That is, the second support portion 11 is connected to the thick first support portion 3 joined to the pedestal 1 through the connecting portion 12,
The weight portion 9 is provided from the second support portion 11 through the thin wall strain generating portions 5 to 8.
Is supported at both ends. The lower separation groove 10 is formed below the upper separation grooves 4a, 4b, 4c, 4d and the thin-walled strain generating portions 5-8, and the upper separation grooves 4a, 4b, 4c, 4d and the lower separation groove 10 communicate with each other. , A through groove penetrating the chip 2 is formed.

The thickness of the thin strained portions 5-8 is set to about 4 μm, and two piezoresistive regions 13a, 13b, 14a, 14b, 15a, 15 are provided on the surface of each of the thin strained portions 5-8.
b, 16a, 16b are formed. Further, as shown in FIG. 3, a recess 17 is formed in the center of the upper surface of the pedestal 1,
When the weight 9 is displaced due to acceleration, the weight 9 is not contacted.

An aluminum wiring pattern on the surface of the silicon chip 2 is shown in FIG. Ground wiring 18 and power supply voltage V
Wiring 19 for applying cc and wirings 20 and 21 for outputting for extracting a potential difference according to acceleration are laid. Further, another set of four wires is prepared for these wires. That is, the wiring 22 for grounding, the wiring 23 for applying the power supply voltage, and the wirings 24, 25 for outputting for extracting the potential difference according to the acceleration are formed. The impurity diffusion layer 26 of the silicon chip 2 is interposed in the middle of the wiring 19 for applying the power supply voltage, and the wiring 18 for grounding intersects with the impurity diffusion layer 26 via the silicon oxide film. Similarly, the wiring 23 for applying the power supply voltage is connected to the wiring 19 for applying the power supply voltage via the impurity diffusion layer 27, and the wiring 22 for grounding is connected to the wiring 18 for grounding via the impurity diffusion layer 28. , And output wiring 2
Reference numeral 4 is connected to the output wiring 20 through the impurity diffusion layer 29. The output wirings 21 and 25 are connected via an impurity diffusion layer 30 for resistance adjustment. In this embodiment, the wirings 18 to 21 are used for connection.

Each piezoresistive region 13a, 13b, 14
a, 14b, 15a, 15b, 16a, 16b constitute a Wheatstone bridge circuit as shown in FIG. 4, a terminal 31 is a ground terminal, a terminal 32 is a power supply voltage applying terminal, and a terminal 33 and 34 are output terminals for extracting the potential difference according to the acceleration. Next, a method of manufacturing this sensor will be described with reference to FIGS. However, FIGS. 5 to 9 show AA cross sections of FIG.

First, as shown in FIG. 5, the plane orientation is (10
N) on the p-type substrate (semiconductor substrate in the present invention) 41 of 0)
Type epitaxial layer (semiconductor substrate in the present invention) 42
Of the piezoresistive regions 13a, 1
3b, 14a, 14b, 15a, 15b, 16a, 16
The p ⁺ diffusion layer 43 is used as b, and the upper isolation trenches 4a, 4b, 4c, 4d are used as electrode contacts during electrochemical etching.
An n ⁺ diffusion layer 44 is formed on the surface of the region to be etched. After that, a silicon oxide film (not shown) formed on the epitaxial layer 42 is selectively opened, and aluminum wirings 18 to 25 (see FIG. 2, not shown in FIGS. 5 to 8) are formed on the silicon oxide film to form an aluminum film. Wiring 18 to 25 is p ⁺ diffusion layer 4
3 is contacted at a predetermined position, then a passivation insulating film (not shown) made of a silicon oxide film or the like is deposited, and the passivation insulating film is selectively opened to form a contact hole for wire bonding. Also, the aluminum film is deposited in a series of fixed on the n ⁺ diffusion layer 44, energizing the aluminum contact portion to contact the n ⁺ diffusion layer 44 by opening the passivation layer (not shown) is provided .

Next, a plasma nitride film (P-Si) is formed on the back surface of the wafer 40, that is, the front surface (back main surface in the present invention) of the substrate 41 excluding the etching planned region of the lower isolation trench 10.
N) 45 is formed, and the plasma nitride film 45 is photopatterned using a resist film (not shown) not shown. Next, a resist film (resist film in the present invention) 49 is spin-coated on the front main surface of the wafer 40, that is, on the surface of the epitaxial layer 42, which will be the regions to be etched in the upper isolation trenches 4a, 4b, 4c, 4d. Photo-pattern. The upper separation grooves 4a, 4b, 4c,
The silicon oxide film and the passivation insulating film on the region to be etched 4d have been removed in advance, and the above-mentioned aluminum contact portion for conduction is exposed on the surface of the epitaxial layer 42 exposed by the photo-patterning of the resist film 49. There is. The resist film 49 is made of polyimide (P) having resistance to an organic solvent for removing wax.
IQ (as a film.

Next, as shown in FIG. 6, the surface of the wafer 40 is adhered to a support substrate 46 made of alumina while being protected by a resin wax W, and an etching solution (for example, 33 wt% KO) is used.
Electrolytic etching is carried out by immersing in H solution, 82 ° C.). The supporting substrate 46 is a hot plate (200 ° C., not shown).
The resin wax W is placed on the support substrate 46 to be softened, and the wafer 40 is further placed and adhered thereon, and then the support substrate 46 and the wafer 40 are removed from the hot plate to cure the wax. . A platinum electrode (not shown) is extended on the support substrate 46, and the tip of the platinum electrode is brought into contact with the aluminum contact portion 60 so that the n ⁺ diffusion layer 44 is formed.
The electrochemical etching (anisotropic etching) is performed by energizing the epitaxial layer 42 and the substrate 41 through
As a result, the lower isolation trench 10 is formed in the substrate 41. An electrode plate (not shown) is suspended in the etching solution tank so as to face the wafer 40, and the platinum electrode is positive between the base end of the platinum electrode and the electrode plate and is 0.6 V or more. Voltage is being applied. When the etching reaches the junction between the substrate 41 and the epitaxial layer 42 in this way, an anodic oxide film (not shown) is formed, and the etching rate is remarkably reduced, so that the etching stops at this junction.

Next, as shown in FIG. 7, after removing the nitride film 45 with hydrofluoric acid, the support substrate 46 is placed on a hot plate to soften the resin wax W, and the wafer 40 is separated from the support substrate 46. The prepared wafer 40 is dipped in an organic solvent (for example, trichloroethane), the resin wax W is washed and dissolved to take out the wafer 40, and then the resist 50 is applied to the entire back main surface of the wafer 40.

Since the resist 50 is not used for photo patterning, it is only necessary to allow the resist solution to flow down. As in the case of resist application for photo patterning (for example, the second resist film 49), a spinning device is used. It is not necessary to vacuum chuck the wafer 40 on the spinning table. Next, as shown in FIG. 8, the epitaxial layer 42 is dry-etched from the opening of the second resist film 49 to form upper isolation trenches 4a, 4b, 4c and 4d.

Next, as shown in FIG. 9, the resist film 49 is removed by oxygen ashing, and the resist 50 is removed by an organic solvent to complete the upper isolation trenches 4a, 4b, 4c, 4d. 4a, 4b, 4c, 4d and the lower separation groove 10 are communicated with each other to form a through groove. Subsequently, the wafer 40 is bonded onto the pedestal 1 and finally diced into chips.

As described above, according to the method of manufacturing the semiconductor pressure sensor of this embodiment, the wafer (semiconductor substrate) 4
No. 0 back main surface is first etched to form upper isolation grooves 4a, 4
b, 4c, 4d, the lower part of the planned region and the thin-walled strained portion 5
8 Before forming the lower isolation trench 10 in the lower part of the planned formation region, the upper isolation trenches 4a, 4b, 4 are formed on the front main surface of the wafer 40.
Since the resist film 49 is photo-patterned except the regions where the c and 4d are to be formed, the regions where the upper isolation trenches 4a, 4b, 4c and 4d are to be formed and the thin strained portions 5 to 8 are to be formed by the first etching. After thinning, it is not necessary to spin-coat the resist film 49 on the front main surface of the wafer 40 and perform photo-patterning as in the conventional case.

Therefore, by vacuum chucking the wafer 40 during the spin coating of the resist film 49, these thinned upper isolation trenches 4a, 4b, 4c, 4d forming regions and thin straining portions 5 to 8 forming regions are formed. Can be prevented from being damaged. As a result, by making the thin-walled strain generating portions 5 to 8 thinner than before (for example, several μm), it is possible to realize high sensitivity of the sensor and to reduce the size of each portion.

Further, a wax W is used as the resist film 49.
Since the polyimide film having resistance to the organic solvent for removal (trichloroethane, trichloroethylene, etc.) is adopted, it is possible to prevent the photo-patterned resist film 49 from being damaged in the subsequent wax removing step.

[Brief description of drawings]

FIG. 1 is a perspective view of a semiconductor acceleration sensor according to an embodiment.

FIG. 2 is a plan view of a semiconductor acceleration sensor.

FIG. 3 is a sectional view taken along line AA of FIG.

FIG. 4 is a bridge circuit diagram of this sensor.

FIG. 5 is a cross-sectional view showing a manufacturing process of the sensor of FIG.

FIG. 6 is a cross-sectional view showing a manufacturing process of the sensor of FIG.

FIG. 7 is a cross-sectional view showing a manufacturing process of the sensor of FIG.

FIG. 8 is a cross-sectional view showing a manufacturing process of the sensor of FIG.

FIG. 9 is a cross-sectional view showing a manufacturing process of the sensor of FIG.

FIG. 10 is a cross-sectional view showing a manufacturing process of a conventional sensor.

FIG. 11 is a cross-sectional view showing the manufacturing process of the conventional sensor.

FIG. 12 is a cross-sectional view showing a manufacturing process of a conventional sensor.

FIG. 13 is a cross-sectional view showing a manufacturing process of a conventional sensor.

FIG. 14 is a cross-sectional view showing the manufacturing process of the conventional sensor.

[Explanation of symbols]

4a to 4d Upper separation groove 5 to 8 Thin wall strain generating portion 10 Lower separation groove 41 p-type substrate (semiconductor substrate in the present invention) 41 n-type epitaxial layer (semiconductor substrate in the present invention) 49 resist film

Claims (1)

[Claims] 1. A photo-patterning step of covering a front main surface of a semiconductor substrate with a resist film except for a surface of an upper separation groove formation planned region, and thereafter etching a predetermined region of a back main surface of the semiconductor substrate to a predetermined depth. And a first etching step of forming a lower isolation groove under the upper isolation groove formation scheduled region and under the thin flexural strain portion formation scheduled region, and thereafter, a front main surface of the semiconductor substrate is opened from the opening of the resist film. An upper separation groove communicating with the lower separation groove is formed by etching, and a thin flexure portion is defined and formed in the thin flexure portion formation planned region by the both separation grooves.
A method for manufacturing a semiconductor dynamic sensor, comprising: an etching step.