JPH0697460A - Multifunction semiconductor device - Google Patents

Abstract

PURPOSE: To provide a multi-functional semiconductor device, having two vertical laminated channels under a gate electrode. CONSTITUTION: Channels 12, 14 are formed on a wide band-gap buffer layer 11 and are coupled to source electrodes 21, 22 and drain electrodes 23, 24, respectively. These electrodes are formed in such a manner that they face each other on both sides across a gate electrode 17. The uppermost channel 14 is separated from the gate electrode 17 by a gap layer 16 of a wide band-gap semiconductor material. The channels 12, 14 are separated from each other by a barrier layer 13, and have a band-gap energy greater than that of each channel.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION This invention relates generally to semiconductor devices, and more particularly to field effect transistors having a plurality of vertically aligned channels.

[0002]

BACKGROUND OF THE INVENTION Compound semiconductor based heterostructure devices are expected to offer significant speed and power advantages over silicon devices. Most compound semiconductor-based HFET designs aim to copy most silicon-based structures using compound semiconductor materials. One drawback of this method is that the advantageous properties of compound semiconductor materials have not been fully utilized,
The smallest feature of the device is also not improved over the silicon-based one. As a result, gallium arsenide devices are not much smaller than silicon-based devices and are not cost competitive with conventional CMOS technology. There is a need for a truly compact and high performance complementary heterojunction field effect transistor structure using compound semiconductor materials.

[0003]

Conventional binary logic circuits are based on transistors having one output.
Many transistors must be interconnected to provide circuits that perform basic and complex functions. The cost of the integrated circuit increases because a significant number of transistors are required for each logic function. Also, interconnecting many transistors is complex and time consuming, further increasing the cost of logic circuits. Provides multiple outputs,
There is a need for semiconductor devices that can perform complex functions even with a reduced number of added components.

[0004]

In summary, the advantages of the present invention are achieved by a multi-functional semiconductor device having two vertically stacked channels below the gate electrode. The channel is formed on a wide bandgap buffer layer, each channel being coupled to a source electrode and a drain electrode, the electrodes being formed on opposite sides of a gate electrode. The top channel is separated and separated from the gate electrode by a cap layer of wide bandgap semiconductor material. The channels are separated from each other by a barrier layer having a bandgap energy that is greater than the bandgap energy of each channel.

[0005]

EXAMPLES A major problem in the design of quantum well field effect transistors is the structure of the channel region under the gate electrode. The performance of this channel region almost determines the performance of the entire device. FIG. 1 is a very simplified cross-sectional view of a channel region of a multifunction semiconductor device according to the present invention. The resulting embodiment of the invention, including all material layers shown in FIG. 1, is substantially a single crystal epitaxial growth layer. To this end, each epitaxial layer must be composed of a material that is crystallographically compatible with the underlying substrate. Therefore, it should be noted that in addition to the electronic material constraints described below with respect to the individual embodiments, the choice of material is also limited by the properties of the crystal. The epitaxial layer of the present invention may be grown by metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), atomic layer epitaxy (ALE), or the like.

Although the present invention is described in the context of a multifunction device having two N-channels and two outputs, it should be understood that multiple outputs can be provided with minor modifications. These variations are readily understood by one of ordinary skill in the art and are intended to be included within the scope of the present invention.

The embodiment shown in FIG. 1 comprises a wide bandgap buffer layer 11 formed on a semiconductor crystal substrate or a semi-insulating crystal substrate 10, which crystal substrate 10 forms a laminated semiconductor structure. Suitable for
The buffer layer 11 is antimony aluminum (ALS
It is composed of a material such as b). Although other wide bandgap materials are known and used in compound semiconductor devices, in the preferred embodiment, ALS is used to ensure compatibility with the other materials used in each overlayer.
b is desirable. The first quantum well channel 12 is formed on a part of the buffer layer 11. In the preferred embodiment, the channel 12 is composed of indium arsenide (InAs) and has a thickness of approximately 10-15 nanometers.

The channel 12 is covered by a barrier region 13 having a predetermined thickness, which is composed of a material having a wide bandgap ALSb. In the preferred embodiment, barrier region 13 is about 3-10 nanometers thick. The second quantum well channel 14 is about 5-10 nanometers thick and covers at least a portion of the barrier region 13, and is the same material used for the first channel 12, such as InAs in the preferred embodiment. Composed of ingredients. The cap layer 16 is formed on the channel 14.
The cap layer 16 is composed of a wide bandgap material such as ALSb and has a thickness of about 30 nanometers, although other wide bandgap materials may be used.

The gate electrode 17 is formed on a part of the cap layer 16 and makes a Schottky contact with the cap layer 16. In the preferred embodiment, channels 12 and 14 are substantially undoped. N-type charge carriers (free electrons) are provided in the channels 12, 14 using well-known doping techniques such as modulation doping. Electrodes 21,2
4 are formed so as to be opposed to each other with the gate electrode 17 sandwiched therebetween, and can function as a source electrode or a drain electrode for the channel 12. The electrodes 22 and 23 are formed so as to face each other with the gate electrode 17 sandwiched therebetween, and can function as a source electrode or a drain electrode for the channel 14. The electrodes 21 to 24 have a surface portion 21.
a to 24a, which is highly conductive and is used to interconnect the device to external or integrated circuits (not shown). Electrodes 21-24 are also formed by diffusing portions 21b-24b, which provide low resistance coupling to channels 12,14.

As indicated by the dashed line in FIG. 2, channel 14 has a first quantized electronic state (also referred to as the "ground state") E _e14 , which is the conduction band energy E of channel 12.
It is located slightly above _c . The value of E _e14 is channel 1
4 thickness. E _e14 is the minimum energy of the electrons in the channel 14. Similarly, channel 12 has a first quantized electronic state E _e12 , which is channel 12
Is the minimum energy of the electrons in. E _e12 is channel 1
2 depends on the thickness. As channel 12 increases in thickness, E _e12 gradually _{moves away} from E _c . Similarly, as the thickness of channel 14 increases, E _{e14 progressively moves away} from E _c . Since channel 12 is thicker than channel 14, E _e14 is _greater than E _e12 even when channels 12 and 14 are both composed of the same material composition. The specific dimensions and thicknesses specified in the preferred embodiment are for illustrative purposes. This structure must be designed to ensure that when the gate is forward biased there is substantially no thermoelectron pair injection from E _e12 into the gate at the top of barriers _13,16 . In practice, the layer thickness may differ from that specified, but
The dimensions should always be chosen such that the _distance between E _e14 and E _e12 is significantly larger than kT, where k is the Boltzmann constant and T is the Kelvin temperature. Forward gate
Bias is limited by leakage current.

In the first configuration, the thickness of the barrier region 13 is E
_e14 Is E_e12 Is always equal to
Charge transfer between channels 12 and 14)
Choose to prevent. In the preferred embodiment, channel 12
Thickness of zero bias the gate electrode 17
And E_e12 < E_F (Fermi energy of this structure)
To be As a result of this relationship,
Channel 12 may be filled with charge carriers or
Turns on with gate bias. Channel 14 thickness
Sa, E_e14 > E_F To be Therefore
Channel 14 turns off with zero gate bias
It

The opposite relationship can be easily achieved by selecting the thickness of the channel 12 such that E _e12 > E _F when zero bias is applied to the gate electrode 17. In this second configuration, channel 12 is "off" with zero gate bias. The thickness of the channel 14 is E _e14
<E _F , in which case channel 14
Turns "on" with zero gate bias. The operation of the multi-function semiconductor device will be described below with reference to the first configuration having a structure in which the channel 14 is normally off and the channel 12 is normally on. The multi-function device according to the present invention operates in the second configuration as long as the polarity of the bias voltage is reversed.

FIG. 3 shows the influence of the application of the positive bias voltage on the energy band relationship shown in FIG. Gate bias is in conjunction with E _e12 E _e14
Lower. FIG. 3 shows the resonance state when E _e14 = E _e12 . At resonant gate bias, the charge on channel 12 tunnels through barrier 13 turning on channel 14. As the gate bias increases to the point where E _e14 <E _e12 , E _e14 and E _e12 become _misaligned ,
Channel 14 remains on, but channel 12 turns off. Gate bias is lowered and E _e14 > E _e12
Then the process reverses.

FIG. 4 shows a multi-output switch composed of one multifunctional transistor according to the present invention. The source electrodes 21 and 22 are both short-circuited. Gate electrode 17
Serves as an input, the drain electrode 24 serves as a first output, and the drain electrode 23 serves as a second output. During operation, the field effect transistor (F
ET) 27 has zero gate bias and gate electrode 1
When turned on, it turns on and couples the sources 21-22 with the drain electrode 24. At zero gate bias, the FET 26 corresponding to channel 14 is turned off.

When a signal is applied to the gate electrode 17, the gate bias increases and the FET 27 turns off. The charge in channel 12 moves to channel 14 and FET2
6 is turned on and couples the signals of sources 21-22 to drain electrode 23. Thus, the preferred embodiment requires only one transistor space and power,
Acts as a single pole double throw switch. Also, high mobility InAs
A multi-output switch consisting of a single multifunction device using is significantly reduced in power requirements and operates faster than is possible with conventional transistor designs. Therefore, the speed power product of a differential amplifier is a factor of 16 below what is possible with conventional transistor designs.

In a similar embodiment, channel 14 is designed to be conductive with zero gate bias. In this case, the channel 14 is wider than the channel 12 as described above. The source electrode 21 is selectively excluded or simply separated from the external circuit. The channels 12, 14 and the barrier 13 are such that when the gate depletion layer pinches off the channel 14, the energy bands at the source ends of the channels 12 and 14 are matched and charge is transferred from the source electrode 22 through the channel 14. It is designed to move to channel 12. Therefore, the source electrode 22 is selectively coupled to the drain electrode 23 or the drain electrode 24. In this example, channel 12
May require a higher drain voltage than channel 14 to equalize the currents in the two channels. This can be easily accomplished at a single voltage by using loads with various resistances, i.e. the low resistance loads used in channel 12.

It will be appreciated here that a multifunction semiconductor device with improved performance is provided. The multi-functional device according to the invention allows excellent materials to be optimally used in HFET technology, as well as effective geometries for high packing densities. This combination allows new functions to be performed with fewer devices and simpler circuits than before.

[Brief description of drawings]

FIG. 1 shows, in a very simplified manner, a sectional view of a part of a multifunctional semiconductor device according to the invention.

2 is a band of the structure of FIG. 1 with no bias applied;
A band diagram is shown.

FIG. 3 shows a band diagram of the structure of FIG. 1 with a gate bias applied.

FIG. 4 shows a simplified schematic diagram of a multiple output switch according to the invention.

[Explanation of symbols]

 10 Crystal Substrate 11 Wide Band Gap Buffer Layer 12, 14 Channel 13, 16 Barrier 17 Gate Electrode 17 21,22 Source Electrode 23, 24 Drain Electrode

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Jun Shen S. Twenty Fifth Place, Phoenix, Arizona, USA 14654 (72) Inventor Said Terani, Ethan Alfredo Drive, Scottsdale, Arizona, USA 8602 (72) Inventor, X Theodore Zoo, Congress Drive 1351, Chandler, Arizona, USA.

Claims (4)

[Claims] 1. A multi-function semiconductor device, said device comprising: a multi-layer semiconductor substrate having an upper surface; a gate electrode (17) formed on said upper surface; an isolation below said gate electrode (17). A first source electrode (22) coupled to the first channel (14); a first drain electrode coupled to the first channel (14); The first drain electrode (23) and the first source electrode (22) are formed opposite to each other with the gate electrode (17) in between, and the first channel (14) is conductive. A first drain electrode composed of a material having a band energy E _C ; a barrier region (13) below the first channel (14), the barrier region (13) being the first
A barrier region (13) composed of a material having a bandgap energy larger than that of the channel (14);
A second channel (12) below the barrier layer (13) and separated from and separated from the first channel (14) by the barrier layer 13; a second channel (12) coupled to the second channel (12). Two source electrodes (21); and a second drain electrode (24) coupled to the second channel (12).
The second drain electrode (24) and the second source electrode (21) are formed opposite to each other with the gate electrode (17) interposed therebetween, and
The channel is such that the first channel (14) has energy E
_{If the} gate electrode has a first quantized electronic state with _e1 and the second channel (12) has a first quantized electronic state with energy E _e2 and the gate electrode is zero biased, then E A multi-function, characterized in that it comprises a second drain electrode (24) coupled to the second channel (14) made of a material having a conduction band energy E _c such that _e1 > E _e2. Semiconductor device. 2. The multifunctional semiconductor device according to claim 1, wherein E _e1 <E _e2 when the predetermined positive bias is applied to the gate electrode (17). 3. The multifunctional semiconductor device according to claim 1, wherein E _e1 = E _e2 is satisfied when a predetermined positive bias is applied to the gate electrode (17). 4. A multifunctional semiconductor device, said device comprising: a substrate (10) on which a laminated semiconductor device can be formed; a wide bandgap buffer layer (11) covering said substrate (10); The buffer layer (1
A first channel region of a first material component formed on a portion of 1) (12), wherein the first material component conduction band energy E _c, the first channel region (12 with); the first A barrier region (13) of a second material component covering one channel (12), wherein the second material component has a greater bandgap energy than the first material component (13); A second channel region (14) of the first material component covering a region (13); a wide bandgap cap layer (16) covering the second channel; the first and second channels (12, 14) )
A gate electrode (17) formed over the first channel and separated from the second channel (14) by the cap layer (16), wherein the first and second channels (12, 14) are A gate electrode (17) each having a first end on one side of the gate electrode (17) and a second end on the other side of the gate electrode (17);
A first source electrode (21) coupled to the first end of the first channel (12); a first drain electrode (24) coupled to the second end of the first channel (12);
A second source electrode (22) coupled to the first end of the second channel (14); and the second channel (1
4) a second drain electrode (2) coupled to the second end of
3) wherein the first channel has a first quantized electronic state with energy E _e1 and the second channel has a first quantized electronic state with energy E _e2 ,
When a bias is applied to the gate electrode, E _e2 > E _e1
And a second drain electrode (23) coupled to the second end of the second channel (14);