JPH0697186A - Manufacture of semiconductor element - Google Patents

Abstract

PURPOSE:To obtain a second epitaxial growth layer which has an improved flatness by using selective epitaxial growth, instead of isotropic etching, for silicon and thereby eliminating troubles specific to isotropic etching. CONSTITUTION:A p-type epitaxial layer 12 of mesa shape is formed on a semiconductor substrate 1 by a selective epitaxial growth method. A mask layer 13 is formed on the uppermost layer of the mesa epitaxial layer 12. A silicon film containing Sb is deposited on exposed parts of the semiconductor substrate 1 and the mesa p-type epitaxial layer 12. The collector 15 of a transistor is formed by heat treatment, and then an n-type epitaxial layer 16 is formed. The resultant device is then subjected to a 'mecha-chemical' polishing process involving chemicals, which is so designed that the polishing operation is automatically stopped when the mask layer 13 is reached. This obtains a semiconductor element which enables higher degrees of integration, making it possible to manufacture integrated circuits having a high breakdown voltage.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and is particularly suitable for improving a method for manufacturing a high breakdown voltage integrated circuit having an epitaxial growth layer.

[0002]

2. Description of the Related Art A method of manufacturing a high breakdown voltage bipolar type integrated circuit element used in a wide field will be described with reference to the drawings. First, as shown in FIG. 1, for example, the surface of a P ^-- type silicon substrate 1 is covered. The oxide film 2 is selectively removed by a known photolithography technique (see FIG. 1) to provide a window. That is, a perforated pattern of the photoresist layer 3 functioning as a mask is provided, and the oxide film 2 portion is removed by several tens of μm by isotropic etching using a nitric acid-based agent to expose the silicon semiconductor substrate 1 portion and then the photoresist. Remove layer 3 (see Figure 2).

Next, as clearly shown in FIG. 3, after coating the silica film 4 containing Sb, heat treatment at a high temperature is performed to obtain N.
⁺ Layer 5 is formed. Here, the oxide film 2 and the like formed on the P ⁻ type semiconductor substrate 1 are removed to remove the N ⁻ epitaxial growth layer 6
Are deposited (see FIG. 5). The uneven surface is formed into a flat surface by the subsequent lapping polishing step, and then the N ^- epitaxial growth layer 6 is provided with a transistor base.
The cross-sectional structure of FIG. 6 is obtained by forming the source region 7 and the emitter region 8.

In FIG. 7, other elements besides the transistor N
^- shows an example of forming the epitaxial growth layer 6.

[0005]

In such a manufacturing method, there is a problem in the etching accuracy of the silicon semiconductor substrate. That is, since the isotropic etching is performed using a nitric acid-based chemical solution, there is a large variation in the amount of isotropic etching on the surface of the silicon substrate to be processed, within the lot and between lots. Especially on the surface of the silicon substrate to be processed,
Depending on the pattern size, there are places where the etching depth differs, which in turn affects the characteristics and is not suitable for miniaturization.

The purpose of using isotropic etching is to avoid damage caused by dry etching.
Moreover, the oxide film 2 becomes overhanging due to the isotropic etching, resulting in a so-called overhang shape, which deteriorates the degree of integration.

Furthermore, in order to stop the lapping / polishing process of the N ⁻ epitaxial growth layer 6 by controlling the lapping / polishing apparatus for the thickness, it is difficult to strictly control. Further, variations in the thickness of the N ⁻ epitaxial growth layer 6 deposited on the silicon semiconductor substrate 1 to be processed and the silicon semiconductor substrate 1 to be processed 1
If the flatness of the substrate is lowered or the flatness of the semiconductor substrate 1 is lowered, the accuracy of the lapping polishing process is lowered. In short, the process stability is low and it is not suitable for miniaturization.

The present invention has been made under such circumstances, and it is an object of the present invention to provide a method of manufacturing a high breakdown voltage integrated circuit element, which can be highly integrated.

[0009]

SOLUTION: A step of selectively depositing a first epitaxial growth layer on a semiconductor substrate of a first conductivity type,
The step of partially removing the mesa-shaped first epitaxial growth layer portion under a mask selectively formed in the first epitaxial growth layer, and the exposed semiconductor substrate portion and the first epitaxial growth layer portion Forming a region of opposite conductivity type, depositing a second epitaxial growth layer on the entire surface, forming a flat surface of the second epitaxial growth layer up to the mask by mechanochemical polishing, The method of manufacturing a semiconductor device according to the present invention is characterized by the step of forming an active or passive device in the second epitaxial growth layer embedded in the semiconductor substrate portion.

Further, in the step of polishing the mask and the second epitaxial growth layer, a chemical solution having a selective ratio between them is used,
Another feature is that it stops automatically when it reaches the mask. Furthermore, the first epitaxial growth layer is deposited only on the exposed semiconductor substrate by adding hydrogen chloride as a source gas under reduced pressure. There are also features in terms.

In addition, the polishing step after the second epitaxial layer depositing step is characterized in that the mask layer provided on the protruding semiconductor substrate portion is processed at the same time.

[0012]

In order to form a transistor by the method of the present invention, for example, an oxide film formed on a silicon semiconductor substrate is partially removed by a known photolithography technique, and then the first epitaxial growth layer is selectively formed by a selective epitaxial growth method. accumulate.

Further, after forming an oxide film or a silicon nitride layer functioning as a mask on the mesa-shaped first epitaxial growth layer, the exposed semiconductor substrate is covered with a Sb-containing silica film to form an N ⁺ layer by heat treatment.

After depositing the second epitaxial growth layer, the surface to the mask are removed by a polishing process to form a flat surface, on which an active or passive element is formed. The most characteristic feature of the polishing step is that it is performed with a chemical solution having a selection ratio of the second epitaxial growth layer and the silicon nitride layer of the mask, and is automatically stopped when the mask reaches the mask.

[0015]

EXAMPLE A high breakdown voltage bipolar device as an example according to the present invention.
A manufacturing process of the integrated circuit device will be described with reference to FIGS. That is, for example, the oxide film 11 provided to cover the surface of the silicon semiconductor substrate 10 is partially removed by a known photolithography technique to expose the surface portion of the silicon semiconductor substrate 10.

Next, a P ^-- type first epitaxial growth layer 12 having a thickness of about 10 μm is selectively deposited on the exposed portion of the surface of the silicon semiconductor substrate 10. The epitaxial growth conditions at this time are such that a hydrogen chloride gas of about 1% by volume is mixed as a source gas under a reduced pressure of about 50 torr maintained at about 950 ° C., and the sectional structure of FIG. 8 is used. The inclusion of hydrogen chloride gas helps the selective formation of the P ⁻ -type first epitaxial growth layer 12 by reducing the growth rate.

In the subsequent step, as shown in FIG. 9, the portion of the oxide film 11 adjacent to the P ⁻ type first epitaxial growth layer 12 is removed by a known photolithography technique, and then P ^−.
After covering the entire surface of the first epitaxial growth layer 12 with a silicon nitride layer 13 having a thickness of, for example, about 0.5 μm, which functions as a mask, a known photolithography technique, that is, a patterning process using a resist is performed. As a result, the silicon nitride layer 1 is formed only on the surface of the P ⁻ -type first epitaxial growth layer 12 protruding.
3 is deposited (see FIG. 10).

Subsequently, an N ⁺ diffusion layer 15 (collector of the transistor) is formed on the P ⁻ semiconductor substrate 10 and the P ⁻ type first epitaxial growth layer 12 by a deposition step of the Sb-containing silica film 14 and a heat treatment step at a high temperature. Is used as), the silica film 15 is removed to obtain the cross-sectional structure of FIG. An N ⁻ -type second epitaxial growth layer 16 having a thickness of about 10 μm + α is deposited on the surface having such irregularities, and a polycrystalline silicon layer 17 is laminated on the silicon nitride layer 13 as shown in FIG.

Further, the N ^-- type second epitaxial growth layer 16 is polished by a mechanochemical polishing process in which a chemical reaction agent and a mechanical polishing process simultaneously proceed. The chemical solution used in this step has a higher etching rate for silicon and the polycrystalline silicon layer 17 than that of the silicon nitride layer 13, and when the silicon nitride layer 13 surface is reached, the polishing step is automatically stopped (Fig. 13).

The N ^- type second surface having such a flat surface
A transistor base 18 is formed on the epitaxial growth layer 16.
And the emitter 19 is formed by a conventional method (see FIG. 14). In this embodiment, a transistor for a high breakdown voltage integrated circuit element, that is, an active element is described, but a passive element can be formed.

The concentrations of the collector, base and emitter of the transistor for high breakdown voltage integrated circuit device of this embodiment are as follows.
10 ¹⁵ / cc, 10 ¹⁸ / cc, 10 ²⁰ / cc in order
It is a known value of degree.

[0022]

As described above, in the method of manufacturing a semiconductor device according to the present invention, selective epitaxial growth is carried out without performing isotropic etching of silicon. A second epitaxial growth layer having improved properties is obtained. Therefore, the pattern
Since size variation and side etching are eliminated, miniaturization is possible. Further, in the mechanochemical polishing step using a chemical, since the silicon nitride layer is used as a stopper, polishing control is easy and accuracy is improved.

In short, the improvement in the degree of integration enables miniaturization, and a process with high stability and easy control can be realized.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a manufacturing process of a conventional semiconductor device.

FIG. 2 is a sectional view of a step following FIG.

FIG. 3 is a sectional view of a step following FIG.

FIG. 4 is a sectional view of a step following FIG. 3;

FIG. 5 is a sectional view of a step following FIG. 4;

FIG. 6 is a cross-sectional view of a step following FIG.

7 is a sectional view of a step following FIG. 6; FIG.

FIG. 8 is a cross-sectional view showing the manufacturing process of the semiconductor element of the present invention.

9 is a sectional view of a step following FIG. 8; FIG.

FIG. 10 is a sectional view of a step following FIG. 9;

11 is a cross-sectional view of a step following FIG.

12 is a cross-sectional view of a step following FIG.

FIG. 13 is a sectional view of a step following FIG. 12;

FIG. 14 is a sectional view of a step following FIG. 13;

[Explanation of symbols]

 1, 10: Semiconductor substrate, 2, 11: Oxide film, 3: Resist, 4, 14: Silica film, 5, 15: Collector, 6, 12, 16: Epitaxial layer, 13: Mask, 17: Polycrystalline silicon layer 7, 18: base, 8, 19: emitter.

Claims (4)

[Claims] 1. A first substrate is selectively formed on a semiconductor substrate of a first conductivity type.
A step of depositing an epitaxial growth layer, a step of partially removing the first epitaxial growth layer under a mask selectively formed in the first epitaxial growth layer to provide a mesa-shaped first epitaxial growth layer portion, and an exposed semiconductor substrate Forming a region of opposite conductivity type in the first portion and the first epitaxial growth layer portion;
A step of depositing an epitaxial growth layer on the entire surface, a step of forming a flat surface of the second epitaxial growth layer up to the mask by mechanochemical polishing, and a step of forming a second epitaxial growth layer buried in the mesa-shaped semiconductor substrate portion. And a step of forming an active or passive element. 2. A method of manufacturing a semiconductor device, wherein in the step of polishing the mask and the second epitaxial growth layer, a chemical solution having a selective ratio to each other is used, and when the mask is reached, the step is automatically stopped. 3. A method of manufacturing a semiconductor device, wherein the first epitaxial growth layer is added only to an exposed semiconductor substrate by adding hydrogen chloride as a source gas under reduced pressure. 4. The method of manufacturing a semiconductor device, wherein the polishing step after the second epitaxial layer depositing step is performed simultaneously with a mask layer provided on a protruding semiconductor substrate portion.