JPH0697183A - Bipolar transistor and fabrication thereof - Google Patents

Abstract

PURPOSE:To make uniform the characteristics such as hFE of bipolar transistor. CONSTITUTION:Base region has a structure provided with a first base region 61 constituting a base take-out region connected with a base electrode, a second base region 62 formed immediately below an emitter region 25 while being self-aligned therewith, and a third base region 63 coupling between the first and second base regions 61, 62.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bipolar transistor suitable for application to a bipolar CMOS (Bi-CMOS) used, for example, in an SRAM (Static Random Access Memory), particularly a vertical bipolar transistor and its manufacture. Involved in the method.

[0002]

2. Description of the Related Art In a bipolar transistor, in order to increase a current and to reduce a parasitic capacitance, particularly an emitter junction capacitance, the planar shape of the emitter is changed to a shape in which the length is greatly reduced and the width of the emitter is reduced. It is necessary to increase the so-called peripheral length and reduce the area thereof, and this necessitates self-alignment between the emitter electrode and the emitter region.

From this requirement, the emitter electrode is composed of a semiconductor layer containing impurities, and the impurities from this are diffused into a semiconductor substrate to form an emitter region, so that the emitter electrode and the emitter region are self-aligned. It

In this case, in order to form an emitter electrode, that is, a portion where the emitter region is formed, only on the base region, a window is opened in an insulating layer such as an interlayer insulating layer formed on the surface of the semiconductor substrate. The emitter electrode is formed through the window. This will be described with reference to FIG.

In FIG. 12, reference numeral 1 is a semiconductor substrate made of silicon or the like, and a base region 3 is formed by ion implantation or the like on a collector region 2 which is a part thereof. On the surface of the semiconductor substrate 1, for example, an insulating layer such as SiO ₂ used for implanting the base region 3 to form the base region 3 at a shallow position, and further on top of this, an insulating layer such as a multilayer in a semiconductor integrated circuit. Similarly, each insulating layer 4 such as SiO ₂ becomes a interlayer insulating layer between wiring layers by CVD.
It is formed by the (chemical vapor deposition) method.

In forming the emitter region on a part of the base region 3, an etching mask 5 such as a photoresist layer is formed on the insulating layer 4 as shown in FIG. Pattern exposure and development are performed to form an opening 5W on a portion where an emitter region is to be formed.

As shown in FIG. 12B, the opening 5 of the mask 5 is formed.
An emitter formation opening 4W is formed in the insulating layer 4 by anisotropic dry etching, that is, RIE (reactive ion etching) through W, and an emitter electrode made of polysilicon containing impurities on the base region 3 exposed through the opening 4W. 6 is deposited, and impurities from this are deposited on the semiconductor substrate 1.
To form the emitter region 7 on the base region 3 in a limited manner.

In this case, the opening 4W is formed by the opening 4W.
An anisotropic RIE is desired to form W in a pattern corresponding to the opening 5W of the mask 5 as much as possible.

However, this anisotropic RIE is caused by the insulating layer 4
Since the selection ratio between the SiO ₂ and the semiconductor substrate 1 forming the substrate is not so large, the RIE is performed on the insulating layer 4 so as to surely form the opening 4W over the entire thickness thereof, as shown in FIG. 12B. Thus, the groove 8 is formed so that the base region 3 is also dug.

However, the depth of the groove 8 is difficult to control because the thickness of the groove 8 is difficult to control when the insulating layer 4 for RIE is SiO ₂ formed by CVD, and the thickness is relatively variable. The depth of 8 also varies.

Therefore, the finally obtained thickness of the base region 3 between the emitter region 7 and the collector region 2 shown in FIG. 12C,
That is, the base width W _B fluctuates, the transistor characteristics, in particular, the emitter current amplification factor h _FE fluctuates, and the base width W _B When it is configured to be sufficiently large, there arises such a disadvantage that the h _FE is increased.

As a method for avoiding such unevenness of the engraving, for example, in the method disclosed in Japanese Patent Laid-Open No. 4-125935, an oxide film having a predetermined thickness by thermal oxidation before the ion implantation of the base region is performed. Has been proposed, and the ion implantation for forming the base region is removed to form an opening for forming the emitter so that the amount of engraving becomes constant.

However, in this case, a step of forming this oxide film and a step of removing this oxide film by RIE are required,
There is an inconvenience that the manufacturing process becomes complicated.

[0014]

SUMMARY OF THE INVENTION The present invention makes it possible to avoid an increase in the number of manufacturing steps in the bipolar transistor described above, while avoiding variations in transistor characteristics such as h _FE. .

[0015]

According to a first aspect of the present invention, a first conductivity type collector region is formed on a semiconductor substrate, a second conductivity type base region is formed on the collector region, and further, a second conductivity type base region is formed on the collector region. In the vertical bipolar transistor having the formed first conductivity type emitter region, the base region of the vertical bipolar transistor is
A first base region forming a base extraction region to which a base electrode is connected, a second base region formed directly below the emitter region in a self-aligned manner with the emitter region, a first base region and a second base It is configured to be formed by a third base region that connects the region.

According to a second aspect of the present invention, a first conductivity type collector region, a second conductivity type base region formed on the collector region, and a first conductivity type formed on the collector region are formed on a semiconductor substrate. A vertical bipolar transistor having a base emitter region, the base region of which forms a base extraction region which is connected to the base electrode and is formed in self-alignment with the base electrode. A region, a second base region formed directly below the emitter region in a self-aligned manner with the emitter region, and a third base region connecting the first base region and the second base region And

According to a third aspect of the present invention, a first ion implantation step of forming a third base region and a step of forming an opening of an insulating film formed on a semiconductor substrate which determines an emitter region by anisotropic etching. A second ion implantation step of forming a second base region in the opening, and a step of forming a polycrystalline semiconductor electrode containing impurities by covering the opening.
A heat treatment step is performed in which impurities are diffused from the polycrystalline semiconductor electrode into the semiconductor substrate and the emitter region is self-aligned with the second base region.

In a fourth aspect of the present invention, a step of forming a third base region, a step of forming a base electrode containing an impurity of the second conductivity type, and a step of forming an insulating film covering the base electrode. And a step of leaving the insulating film on the side wall of the base electrode by anisotropic etching, and a step of introducing a second conductivity type impurity into the surface of the semiconductor substrate determined by the side wall to form a second base region. A step of forming an emitter electrode containing an impurity of a first conductivity type on the second base region, and a first base region forming a base extraction region by diffusing the impurity from the base electrode and the emitter electrode, respectively. And a heat treatment step of forming an emitter region on the second base region.

[0019]

According to the present invention described above, since the second base region of the portion located immediately below the emitter is formed in the opening defining the emitter region, that is, after the formation of this opening, the second base region of the portion located immediately below the emitter is formed. Since the second base region is formed, the nonuniformity of the base width due to the dug in the formation of the opening, and thus the variation in the characteristics due to the nonuniformity,
It is possible to avoid the occurrence of defective products.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A bipolar transistor according to the first aspect of the present invention and an embodiment of its manufacture will be described in detail with reference to FIGS.

As shown in FIG. 1A, a second conductivity type such as p
For example, a silicon substrate 10 of the first type is prepared, and a first conductivity type, for example, an n-type impurity A is selectively formed on a portion of a main surface of the substrate where the bipolar transistor is selectively formed.
s is selectively diffused to form a collector buried region 49, and the substrate 1 in which the buried region 49 is formed
0 on the first conductivity type, for example, an n-type silicon semiconductor layer 11
Is epitaxially grown to, for example, 10 nm to form a semiconductor substrate such as a silicon semiconductor substrate 12.

Further, the semiconductor layer 11 of the semiconductor substrate 12
Is a so-called LOC which is an insulating layer formed of a thick oxide film selectively.
The OS 13 is formed in a portion other than the electrode extraction portion and the operation area portion of the finally obtained bipolar transistor.

As shown in FIG. 1B, for example, a p-type isolation region 14 of the second conductivity type for electrically isolating the finally obtained bipolar transistors from each other or the bipolar transistor from another CMOS is provided.
Boron is ion-implanted, for example, twice by ion implantation with different energies so as to traverse the entire thickness of the semiconductor layer 11 to a depth that reaches the p-type substrate 10 in the second conductivity type in this example.

Next, as shown in FIG. 2A, a SiO ₂ insulating layer 15 having a thickness of, for example, 10 nm is formed on the entire surface by CVD or the like, and the first conductivity type n-type is formed by ion implantation with two different energies. For example, phosphorus ions are ion-implanted to fill the collector extraction region 59 with the buried region 4
It is formed over a depth reaching 9.

As shown in FIG. 2B, a portion of the semiconductor layer 11 above the buried region 49 is used as a collector region 69, and impurity ions of the second conductivity type such as BF ₂ ⁺ are shallowly ion-implanted on the collector region 69 through the insulating layer 15. As a result, a third base region 63, which is a part of the base region of the finally obtained bipolar transistor, is formed.

Then or after that, as shown in FIG. 3A, the second conductivity type impurity is similarly ion-implanted into the peripheral portion of the third base region 63 to highly concentrate the first base region 61. It forms the so-called graft base region.

As shown in FIG. 3B, the entire surface is made of, for example, Si.
An interlayer insulating layer 18 is formed by depositing O ₂ by, for example, a CVD (chemical vapor deposition) method. Then, an opening 19 corresponding to an emitter region pattern to be finally obtained by photolithography or the like is anisotropically formed over the interlayer insulating layer 18 and the insulating layer 15 below the interlayer insulating layer 18 only in a part on the third base region 63. The holes are formed by etching, for example, RIE (reactive ion etching).

Then, second conductivity type impurity ions such as BF ₂ ⁺ are ion-implanted through the opening 19 to form a second base region 62, a so-called intrinsic base region, which is to be formed immediately below the emitter.

As shown in FIG. 4A, a polysilicon layer, that is, a polycrystalline semiconductor layer 2 forming an emitter electrode over the entire surface is formed.
1 is formed, and impurity ions of the first conductivity type, for example, A
s ⁺ is entirely ion-implanted.

As shown in FIG. 4B, the polysilicon layer 21
Are selectively etched by photolithography to contact the second base region 20 through the opening 19,
The emitter electrode 22 having a required pattern in the finally obtained transistor is formed by a part of the polysilicon layer 21.

As shown in FIG. 5A, an interlayer insulating layer including the emitter electrode 22 and a semiconductor layer (not shown) for forming a TFT (thin film transistor) or the like formed on the interlayer insulating layer, and an insulating layer covering the surface of the semiconductor layer are further formed. For example, a material layer having a multi-layer structure, for example, the insulating layer 23 is formed by CVD or the like.

Then, for example, a heat treatment at 900 ° C. is performed to diffuse impurities such as As in the emitter electrode 22 by the polycrystalline silicon 21 onto the second base region of the semiconductor substrate, and as shown in FIG. 5B, the emitter region is formed. 25 is formed.

As shown in FIG. 6, insulating layers 23, 18, 1
5 are provided with openings in the isolation region 14, the collector electrode extraction region 59, the emitter electrode 22, and the first base region 61 by photolithography, and a barrier such as TiN is formed through these openings. Isolation electrode 26I, collector electrode 26C in bipolar transistor, emitter electrode 26E, by vapor deposition of metal and Al containing, for example, Si, and patterning by photolithography.
The base electrode 26B is formed to obtain the desired bipolar transistor.

According to such a configuration, the semiconductor substrate 12
A first conductivity type collector region 69, a second conductivity type base region formed thereon, that is, first to third base regions, and a first conductivity type collector region 69 formed thereon. A vertical bipolar transistor having the emitter region 25 is formed.

The base region is a first base region 61 forming a base extraction region to which the base electrode is connected, and a second base region formed directly below the emitter region in a self-aligned manner with the emitter region. 62, and a third base region 63 that connects the first base region 61 and the second base region 62 is formed.

In the bipolar transistor thus formed, after forming the opening 19 shown in FIG. 3B,
Since the second base region 62, which serves as a so-called intrinsic base or internal base that forms the base region immediately below the emitter, is formed, even when the opening 19 is dug when the opening 19 is formed, the second base region 62 is always formed. Since the second base region 62 can be formed at a predetermined depth from the bottom surface of the dug, the depth (thickness) becomes constant.

The emitter region 25 formed on the second base region 62 is formed by the diffusion of impurities from the emitter electrode 22 through the same opening 19 to form the emitter region 22 and the emitter region 22. 25, and second base region 6 below this
2 is self-aligned.

The depth of the second base region 62 is equal to
The base width, that is, the emitter area
Distance between zone 25 and collector region 69, and thus the base
Width W _BHas been set to be even and the characteristics are uniform and stable.
A bipolar transistor can be constructed.

Still another example of the bipolar transistor according to the present invention and the method of manufacturing the bipolar transistor according to the present invention will be described with reference to FIGS.

Also in this case, FIG. 1A, FIG.
By taking the steps described in A and B, that is, the same configuration as that described in FIG. 2B is first configured as shown in FIG. 7A.

Then, as shown in FIG. 7B, the insulating layer 13
Is removed at the base formation portion, and a polysilicon, that is, a polycrystalline semiconductor layer is formed over the entire surface to a thickness of 150 nm by, for example, CVD, and second surface conductivity type impurities such as boron ions are ion-implanted over the entire surface. , An insulating layer such as SiO ₂ is formed on the entire surface by CVD or the like, and then both layers are patterned by etching by, for example, photolithography to finally obtain the first base of the base region of the bipolar transistor. A base electrode 31 made of a polysilicon layer containing an impurity of the second conductivity type over the portion where the region 61 is to be formed.
Then, the insulating layer 32 is formed thereon. Thus, the opening 19A having a required width larger than the emitter region and the second base region 62 below the emitter region is formed in a part of the base region 63.

As shown in FIG. 8A, a base / emitter separation insulating layer 33 such as SiO ₂ is formed on the entire surface by CVD or the like.

As shown in FIG. 8B, anisotropic etching such as RIE is performed to a depth corresponding to the thickness of the flat surface of the insulating layer 33, so that the base electrode 31, that is, the side surface of the polysilicon, is particularly etched. A sidewall or side wall 34 having a required thickness on the inner surface of the opening 19A.
To form an opening 19 for forming the emitter region and the second base region 62 thereunder.

Next, as shown in FIG. 9A, ions are implanted into the third base region 63 to form a second base region 62 having a required depth.

Further, as shown in FIG. 9B, the polysilicon layer, that is, the polycrystalline semiconductor layer 35 is entirely covered with CV in contact with the second base region 62 through the same opening 19.
It is formed by the D method or the like, and first conductivity type impurities such as As are ion-implanted therein.

As shown in FIG. 10A, the polysilicon electrode 35 of the polycrystalline semiconductor is subjected to pattern etching by photolithography to form the emitter electrode 22 including a portion to finally form an emitter region. An interlayer insulating layer 23 made of, for example, SiO ₂ is formed on the entire surface by CV.
D and the like.

Then, for example, annealing at 900 ° C. is performed to diffuse As as impurities from the emitter electrode 22 into the second base region 62 to form the emitter region 25. At this time, at the same time, boron B is diffused from the polysilicon base electrode 31 into the third base region 63 to form the high-concentration first base region 61.

In some cases, an interlayer insulating layer or the like is entirely formed on the interlayer insulating layer by CVD or the like, and the interlayer insulating layer and the insulating layer below the interlayer insulating layer are patterned by photolithography, for example. Isolation electrode formation opening, collector electrode extraction opening,
A metal base electrode extraction opening and the like are formed.

Including these openings, for example, T
A barrier metal (not shown) such as iN and a metal such as Al containing Si are entirely formed by vapor deposition, sputtering, etc., and pattern etching is performed by photolithography, so that isolation electrodes are formed as shown in FIG. 10B. 26I, collector electrode 26C, emitter metal electrode 2
6E, the base metal electrode 26B is formed.

Thus, the desired bipolar transistor, that is, the first conductivity type collector region 69 of the semiconductor substrate 12, the second conductivity type base regions 61, 62 and 63 formed on the collector region 69, and the collector regions 69 and the second conductivity type base regions 61, 62 and 63 are further formed. A vertical bipolar transistor is formed by forming a first conductivity type emitter region 25 formed on the second base region 62, and a base extraction region formed in self-alignment with the base electrode 31 is formed. The constituent first base region 61, the second base region 62 formed directly below the emitter region in a self-aligned manner with the emitter region 25, and the first base region 61 and the second base region 62 are connected to each other. Third base region 6
A bipolar transistor according to the present invention, in which No. 3 is configured, can be configured.

In this case as well, after the opening 19 is formed, the second base region 62 immediately below the emitter is formed by controlling with a required depth, and the emitter region 25 is formed on the second base region 62, so that the base width is a predetermined width. It is possible to configure a bipolar transistor having uniform characteristics set to.

7 to 11, parts corresponding to the respective parts shown in FIGS. 1 to 6 are designated by the same reference numerals, and duplicate description will be omitted.

[0053]

As described above, according to the present invention, the opening 19 for defining the emitter region can be formed without increasing the number of complicated steps such as the formation of a special oxide film and the removal of the oxide film. After the formation of the second base region 62 and the emitter region 25 which are located immediately below the emitter, the nonuniformity of the base width due to the digging in the formation of the opening 19, and therefore the variation in the characteristics due to the nonuniformity. Moreover, it is possible to avoid the occurrence of defective products.

[Brief description of drawings]

FIG. 1 is a partial manufacturing process diagram of an example of the present invention.

FIG. 2 is a partial manufacturing process diagram of an example of the present invention.

FIG. 3 is a partial manufacturing process diagram of an example of the present invention.

FIG. 4 is a partial manufacturing process diagram of an example of the present invention.

FIG. 5 is a partial manufacturing process diagram of an example of the present invention.

FIG. 6 is a partial manufacturing process diagram of an example of the present invention.

FIG. 7 is a partial manufacturing process diagram of another example of the present invention.

FIG. 8 is a partial manufacturing process diagram of another example of the present invention.

FIG. 9 is a partial manufacturing process diagram of another example of the present invention.

FIG. 10 is a manufacturing process diagram of a part of another example of the present invention.

FIG. 11 is a partial manufacturing process chart of another example of the present invention.

FIG. 12 is a manufacturing process diagram of a conventional bipolar transistor.

[Explanation of symbols]

 12 semiconductor substrate 25 emitter region 61 first base region 62 second base region 63 third base region 69 collector region

Claims (4)

[Claims] 1. A semiconductor substrate having a first conductivity type collector region, a second conductivity type base region formed thereon, and a first conductivity type emitter region formed thereon. In a vertical bipolar transistor having, the base region is directly below the emitter region in a self-aligned manner with the first base region forming a base extraction region to which a base electrode is connected. Second formed on
And a third base region connecting the first base region and the second base region with each other. 2. A semiconductor substrate having a collector region of a first conductivity type, a base region of a second conductivity type formed thereon, and an emitter region of a first conductivity type formed thereon. In a vertical bipolar transistor having, the base region has a first base region which is connected to a base electrode and forms a base extraction region which is formed in self-alignment with the base electrode, and the emitter. And a third base region connecting the first base region and the second base region in a self-aligning manner with the region, the second base region being formed immediately below the emitter region, and the third base region being connected to the second base region. Characteristic bipolar transistor. 3. A first ion implantation step of forming a third base region, a step of forming an opening of an insulating film formed on a semiconductor substrate which determines an emitter region by anisotropic etching, and a step of forming the opening in the opening. A second ion implantation step of forming a second base region, a step of forming a polycrystalline semiconductor electrode containing impurities by covering the opening, and diffusing impurities from the polycrystalline semiconductor electrode into the semiconductor substrate. 2. A method of manufacturing a bipolar transistor according to claim 1, further comprising a heat treatment step of forming an emitter region by self-alignment with the second base region. 4. A step of forming a third base region, a step of forming a base electrode containing impurities of the second conductivity type, a step of forming an insulating film covering the base electrode, and anisotropy. A step of leaving the insulating film on the side wall of the base electrode by etching; a step of introducing a second conductivity type impurity into the surface of the semiconductor substrate determined by the side wall to form a second base region; A step of forming an emitter electrode containing an impurity of a first conductivity type on the base region; and a step of forming a first base region constituting a base extraction region by diffusing the impurity from the base electrode and the emitter electrode, respectively. The method for manufacturing a bipolar transistor according to claim 2, further comprising a heat treatment step of forming an emitter region on the second base region.