JPH0693694B2 - Flexible data communication system - Google Patents

Description

Description: TECHNICAL FIELD The device of the present invention relates to a data processing communication system, and particularly, when a defective communication path is detected, the defective module is automatically switched to an operating module. Regarding things.

[Conventional technology and problems to be solved]

A communication system is an input / output terminal network (circuit network) that communicates via dedicated lines or circuit-switched communication lines.
Can be included. The tropology of the terminal is one-to-one, and there are multiple points or cluster controllers. The communication line can be terminated by MODEM. Information from the terminal is transmitted to the communication network, and information to the terminal is received by the terminal from the communication network by MODEM.

In places such as department stores, many terminals are connected to the communication network by many MODEMs. These MODEM
Can be installed in a central location for ease of connection with the communication location and for ease of maintenance. MODE
A device is usually built such that the bank of M can handle a group of terminals.

If the MODEM in the CSU fails, this terminal or group of terminals can normally be switched to another MODEM. Such switching of MODEMs has typically been done by operators or maintenance personnel who manually patch the line to a spare MODEM.

Many MODEMs, especially many terminals in one place that require MODEMs with different functions, are usually located in one area. These MODEMs are typically rack supports, which typically require a large number of cables, which
Replacing M is difficult and error-prone.

These prior art systems typically operate as a duplex system. There was a simple automatic system for manual switching to the standby system, or system switching when one system was not working. That is, a test signal sent to one system will cause an automatic switch to the standby system if the test signal is not received by the terminator.

OBJECTS OF THE INVENTION Accordingly, it is an object of the present invention to provide an improved communication system having non-manual switchable elements for continuing automation.

SUMMARY OF THE INVENTION A data communication system includes a number of input / output terminals that send and receive messages over a communication network via a network access controller (NAC). Each NAC includes a communications server unit (CSU) and a general purpose computer.

The system is designed as a flexible system, i.e. the system automatically replaces any active module with a redundant module or component in case of failure. However, the circuitry can be reconfigured to lock out the failing device. Thus, a general purpose computer associated with one NAC may be a spare computer for yet another NAC.

The CSU is also designed to be flexible. Each CSU is 1
Includes a pair of network processors. 1 for each network processor
1 with two microprocessors connected one at a time
One control module is connected to the further supported relay module. When the general purpose computer determines that the communication link is faulty, the computer, via the network processor, signals the control module to switch the speech line in the faulty communication link to the spare MODEM. The terminals on the failed link are then activated by the spare module.

The control module can also switch the remote line test capability to verify that the link between the relay module and the terminal is working.

The normal communication path between a terminal and its associated MODEM and communication network is one relay node via a relay module.
It is on the communication line for MODEM. The serial data output from this MODEM is received by the serial input / output (SIO) module, which produces a parallel output byte, which is provided to the VMEbus. The network processor reads the data bytes and sends these bytes onto the RS232 communication line to the general purpose computer for transmission to the communication network.

The data from the communication network is received by the general purpose computer and then sent to the MODEM attached to the terminal via the network processor, SIO, MODEM, and relay network.

The spare MODEM is connected to the spare SIO. Therefore, if the control module signal received by the relay module switches the failed communication link to the spare MODEM, the spare SIO will also replace the SIO in the failed communication link. In the event of a SIO module failure, all its terminal connections (ie MODEM) are connected to its associated MODEM.
To a spare SIO module with.

Also, all components are connected to the printed circuit backplane by commercially available connectors to facilitate maintenance and replacement of faulty devices.

The manner in which the method of the present invention is carried out, the manner in which the device of the present invention is constructed, and its mode of operation will be best understood in view of the following detailed description in conjunction with the accompanying drawings. In the drawings, like reference numbers indicate similar elements in the figures.

〔Example〕

FIG. 1 is an overall block diagram of a farm banking POS (EFTPOS) system 1. This system includes a communication network 8 and many of which are connected to the communication network 8 by communication lines 16-1 to 16-n, respectively. Network access controller (NAC) 3a to 3n. Each NAC3a or
3n includes communication server devices (CSU) 2a to 2n and general-purpose computers 6a to 6n, respectively. Each CSU 2a typically communicates with a number of Point of Service (POS) terminals 4 in a one-to-one or branch topology of up to 144 lines. General purpose computer 6n is shown in FIG. 1 as a spare computer 6n for computer 6a. The terminal 4 may share one communication line like the terminal 4a, or may try to obtain one terminal controller 5 like the terminal 4b.

Also connected to the communications network 8 are a number of financial institution computer systems 10, a number of subscriber access facilities 12 and a network management computer system 14.

The POS terminal 4 is typically installed at a merchant's business location that accepts payments for goods and services based on plastic debit cards. The debit card is typically issued by the financial institution 10 to the customer.

A typical method is for a customer to present a debit card for payment of goods or services. A sales person on the premises of the store inserts this debit card into the POS terminal 4. A message including the identification of the activated POS terminal 4, the identifier of the issuing financial institution obtained from the card, and the purchase amount is presented to the NAC 3a. This message is typically retrieved in a polled environment. The NAC 3a provides this information to the communication network 8. Upon recognition of the identification code or address, the financial institution 10 accepts this information and returns acceptance or rejection of the transaction to the initial terminal 4 via the communications network 8 and NAC3.

NACs 3a-3n are geographically distributed network nodes to provide local connections to terminals 4 in the store. The NACs 3a to 3n are mainly located in the telephone exchange office, but may be located in a small proportion of the customer premises, especially when the equipment is in a commercial district.

The NAC 3a consists of two main functional units, the computer 6a and the CSU 2a. The computer 6a must respond to the overall control of the NAC 3a in order to relay information between the terminal 4 and the financial institution 10 and to provide information in the form and control such as detecting and reporting a faulty communication link. I have to.

CSU2a is configured with all critical components having spares. In the event of an internal failure, redundant components are activated to ensure continued service pending during repair of the problem. However, CSU 2a relies on the control service of computer 6a initiating the repair operation.

In case of a failure of the connection to the computer 6a or its communication network 8, the CSU 2a can establish a connection to the remote computer 6n. Remote computer 6n
Can be part of another NAC3n and has its own local CSU
Control 2n. NAC3a is usually a computer 6a and CSU2a
Consists of, but local CSU2a, remote CSU if in the fault state
2n and remote computer 6n. Computer 6a
Software can typically support up to 12 CSU2a. Therefore, it will be appreciated that the NAC 3a can be composed of one computer 6a and multiple CSUs 2a.

The subscriber access facility 12 is operated to monitor the portion of the communication in which the financial institution has limited network management capabilities in its responsibility.

The network management system 14 provides the ability to control the operation of the network 8 and help manage the network. System 14 NA
It provides a directory service by retaining information about the characteristics and addresses of the C3a-3n configuration forms and fallback addresses.

FIG. 2 shows a block diagram of the CSU 2a. The 144 communication lines and associated terminals 4 are connected via relay modules 2-2f to 2-2a, respectively. Each relay module 2-2a to 2-2f consists of four relay banks. Each relay bank serves up to six communication lines. Therefore, 24
A bank relay connects 144 communication lines. Each of the relay modules 2-2a to 2-2f is connected to the MODEM banks 2-4a to 2-4f via 28 pairs of communication lines. Each MODEM bank 2-4a to 2-4f has 28 MODEMs, that is, 24 MODEMs connected to 24 communication lines and 4 MODEMs as spares.

Each MODEM module 2-4a to 2-4f receives a series of I / O (S
IO) 2-6a to 2-6f are connected to each half thereof.
4 spare MODEMs from each MODEM module 2-4a to 2-4f with spare SIO for a total of 24 spare channels
It is connected to 2-6. Switching one spare MODEM to the system also causes a switch in that spare SIO.

Each half of SIO2-6a to 2-6f is a MODEM module 2
It converts the information on the 24 channels received from -4a through 2-4f into a parallel stream of characters placed on the VMEbus 2-8. The 16 types of signals in each full-duplex channel include a sending data signal and a receiving data signal,
Each data signal carries a stream of data bits. The remaining signals are the normal initial connection procedure signals of CCITT's V.24 interface.

Each pair of SIO2-6a and 2-6b, 2-6c and 2-6d, and 2-6e and 2-6f provide 56 fully programmable, full-duplex multiplex protocol serial data channels However, only 48 of them are used.

Each MODEM module 2-4a to 2-4f also provides 24 channels for its respective SIO2-6a to 2-6f, plus four spare channels, one spare SIO2- Give to 6s. The SIO2-6s are further connected to 24 channels to the VMEbus 2-8.

Further, the duplicated network processor 2-10a and 2-10b is connected to the VME bus 2-8. The network processor 2-10a includes a communication controller A, a communication controller B, and both communication controllers A and B.
Includes microprocessor and common logic for control of. The communication controller A is connected to the computers 6a and 6n via an RS232 communication interface. The communication controllers A and B are connected to the control module 2-12 via the RS422 communication interface. The computer 6a uses the network processor 2-10a as a master.
Or assign 2-10b. If computer 6a determines that processor 2-10a is defective, computer 6a assigns processor 2-10b as the master. All data is processed by this master processor.

The control module 2-12 provides a signal to switch the terminal 4 from the inactive communication path to the backup communication path by energizing selected relays in the relay modules 2-2a to 2-2f. Relay module 2-2a
Note that each of 2 through 2-2f has four banks of relays. Each relay bank has 6 terminals 4
Any one of them can be switched to the spare MODEM in the MODEM modules 2-4a to 2-4f. Each MODEM module has 28 MODEMs, ie 24 MODEMs for normal operation and 4 spare MODEMs for backup operation
Note that it includes.

Network processor 2-10b includes communication controller C and communication controller D, as well as its microprocessor and common logic. The communication controller C is
Control module 2-12 via RS422 interface
Connected with.

FIG. 3 shows the detailed logic of the relay module 1 of the relay module 1-4 2-2a. The relay module 1 includes six relays 211-216, each of which is activated by its respective driver 201-206 when a fault condition occurs in its communication path. Terminals 1-16 are connected to their respective MODEM1 401-M by a pair of conductors through a pair of normally closed contacts of their respective relays 211-216.
Connected with ODEM6 406.

The data enable signal DA which enables the control module 2-12 to enable the relay modules 1-4 2-2a when a faulty communication path associated with terminals 1-6 is detected.
Generate TENa and relay address signals RYAD 3 to RYAD
5 to generate relay module 1, 2, 3 or 4
Is ready for use.

The relay module 1 includes a decoder 214 which receives the data enable signal DATENa and the relay address signals RYAD3 to RYAD5 and generates one of the strobe signals STROBE1 to 4 or the remote line test strobe signal STRLLT.

The STROBE 1 signal from the decoder 214 is the driver 201 to 20.
6 is ready for use. STROBE 2 signal is relay
The corresponding driver (not shown) of module 2 is enabled. The STROBE 3 signal enables the corresponding driver of relay module 3. STROBE
The 4 signal enables the corresponding driver of the relay module 4. The remote line test STRLLT signal enables drivers 207-1 through 207-4.

The faulty communication path is reserved MODEM1 when the Echoda 216 receives data available DAATENa and relay address signals RYAD 0 through RYAD 2 from the control module 2-12.
And switch to spare SIO2-6s. Output signal DATA 1
One of DATA to DATA 6 is applied to the second input terminals of drivers 201 to 206 respectively to energize one of the relays 201 to 206. If DATA 3 signal is generated,
The wire pair at terminal 3 is sent to the spare MODEM 1 407-1 via the two normally open contacts of relay 213. If a remote line test is required after some time, the decoder 21
The signal STRLLT from 4 and the signal DATA 1 are the driver 207−
1 to activate relay 217-1. in this case,
The normally open contact pair controls the remote line test signal 2-
12a and 2-12b. Signals DATA 1 to DATA 4 have 4 relays 21 for remote line test.
Note that if 7-1 then activates one of 217-4 to generate the remote line test signal. Also, relay 1
Note that when one is energized, the communication path for the spare MODEMs 1-4 is opened by one normally closed contact pair of relays 217-1 through 217-4.

The output channels of MODEM 41 to 406 are SIO 1 to SIO 6
12-6a and the output channels of spare MODEMs 407-1 to 407-4 are provided to SIO spare 2-6s. This state protects one SIO unit from a failure and deactivates the communication path of one bank in one premises.

The logic of the relay modules 1-4 2-2a is duplicated with respect to the relay modules 2-2b to 2-2f. Terminals 25-144 are relay modules 2-2
MODEM 2-4a to 2-4f via a to 2-2f
Connected with.

FIG. 4 shows a control module 2-1 including a microprocessor (μPA) 120 and a microprocessor (μPB) 121.
2 shows a block diagram of 2. Microprocessors 120 and 121 are typically Motorola 6801 microprocessors.

RA422D− and RA422D +, which are RS422 standard differential balanced interconnection signals, are received from the network processor 2-10a and generate a received data signal RADATA (RCV
R) 122. RS422 signal RB422D- and RB422D
+ Is received from the network processor 2-10b and applied to RCVR 124 to generate the received data signal RBDATA. Signal RA
DATA and RBDATA are provided to port 2 of microprocessors 120 and 121, respectively. μPA120 and μPB12
Each one provides a communication path to provide flexibility (ie, forbid one "PA" or "PB" to "stream" in a fault condition). If the information received indicates a faulty communication path, the request bus signals ARQBUS and BRQBUS are respectively microprocessor 12
Provided to programmable array logic (PAL) 130 from ports 1 of 0 and 121. Further, the microprocessors 120 and 121 respectively give the PAL 130:
Bus connection signals ATOBUS and BTOBUS. The signal AGRANT applied to port 1 indicates that the microprocessor 120 is given access to the A bus 132,
The signal BGRANT given to the microprocessor 121 is B
Indicates that access to bus 133 is provided.

The signal AONBUS from PAL 130 enables transceiver 126 and the signal BONBUS enables transceivers 128 and 129.

The following is a logical expression of the PAL 130 input and output signals. The (!) In front of the signal name indicates the negated signal. The signals AMASTR and BMASTR are also used by the microprocessor 12
Note 0 or indicates whether the microprocessor 121 is controlling and internal to the PAL 130.

ADNBUS =! (! AGRANT &! AMASTR & ARQBUS & ATOBU
S) BONBUS =! (! BGRANT &! BMASTR & BRQBUS & BTOBU
S) AGRANT ＝! (! AMASTR & ARQBUS) AMASTR =! (ARQBUS & BGRANT) BGRANT ＝! (! BMASTER & BRQBUS) BMASTR =! (BGRANT & BRQBUS) Enable signal DAEN from port 3 of the microprocessor
A 0-5 sends signals DA through transceiver 126 and function 134 to relay modules 2-2a through 2-2f, respectively.
Select the relay modules 22a-22f included in the faulty communication channel, given as TENa through DATENf.

Similarly, in parallel, signals DAENB0-5 from port 3 of microprocessor 121 are routed through transceiver 128 to junction point 134.
Given to.

Signal from port 4 of microprocessors 120 and 121
RYADA 0-5 and RYADB 0-5 are provided to AND junction 135 via transceivers 127 and 129, respectively, to generate relay address signals RYAD 0-5. Signals RYAD 0-5 select a relay in a relay module that is in an enabled state and reserve the communication path MODEM
Switch to.

Junctions 134 and 135 produce output signals when both input signals are low. Junction points 134 and 135 remain active when either network processor 2-10a or 2-10b is not energized or a portion of control module 2-12 is inactive.

The transmission enable signal TA422E and the transmission data signal TADATA are transmitted via the port 2 of the microprocessor 120 to the driver (DRV
R) 123, and according to these signals, as described above
The transmission signals TA422D + and TA422D− which are RS422 signals are returned to the network processor 2-10a. Similarly, the transmit enable signal TB422E and the transmit data signal TBDATA are returned to the driver (DRVR) 125 via port 2 of the microprocessor 121 and, according to these signals, the transmit signals TB422D + and TB422D, which are RS422 signals as described above. -Is returned to the network processor 2-10b.

Remote line test 136 sends and receives tone signals that test the continuity of the line between terminal 4 and relay modules 2-2a through 2-2f. This tone signal path leads from the remote line test 136 to the normally open contacts of relays 207-1 to 207-4 and from the selected normally open contact of relays 211 to 216 to terminal 4. This tests the line switched to the spare MODEM.

MODEM1 to MODEM6 in FIG. 3 are 16 signal lines each.
Connected to SCC 601, 602 and 603 by CCITT V.24 channels. MODEM8 and 9 are CCITT of each
Connected to SCC604 by V.24 channel. Each channel of the V.24 interface includes full duplex operation of data transmission and data reception operations. In addition to synchronization timing, there are control and maintenance signals for the interface.

FIG. 5 shows a block diagram of SIO1 2-6a. As shown in FIG. 2, SIO2-6a and SIO6b contain seven SIOs, each of which is a duplicate of SIO1. Similarly, SIO2
-6c and 2-6d, and 2-6e and 2-6f are SIO2-
Replication of 6a and 2-6b. These are shown as two halves because 24 channels require 3 and half SIOs.

SIO1 is four serial communication controllers (SCC) 601, 60
Including 2, 603, 604. Each SCC serves two network CH A and CH B. This SCC is typically Z8530
The controller.

The SCCs 601-604 communicate with the VMEbus 2-8 through bidirectional data signals D0-D7 and data register 605.

Address and control information is sent and received on the VMEbus 2-8 via address and control buffer 608. Address information is received by data bus 611 via address controller 607. The data bus 611 sends register address information to the SCC and data or control information to and from the VMEbus 2-8.

The SCC generates an interrupt signal to interrupt the controller 609 which generates an interrupt request to the VMEbus 2-8 via the interrupt request line. When the VMEbus 2-6 acknowledges this interrupt, the interrupt controller 609 signals the bus controller 610 which, in response to the interrupt acknowledge cycle, places an interrupt vector on the VMEbus 2-8 and a data transmission acknowledge signal DTACK. Express. This interrupt cycle is released by deasserting the DTACK signal.

A number of onboard registers 606 control the operation of the SIO. These are the data rate selector register, command /
Includes status read / write registers and line loopback / maintenance registers (not shown).

FIG. 6 shows a block diagram of a network processor 2-10a that transfers information between the VMEbus 2-8 and the computer 6a. The network processor 2-10b also has a VMEbus 2-
Transfer information between 8 and computer 6a.

Data from VMEbus 2-8 appears on CPU data bus 110 via transceiver 106 and transceiver 104. 16-bit data is received by CPU100, SCC1
Channel A R S 2 3 with conditioning 01, 102
2 Receive data for transfer to computer 6a over interface or control module 2-1 over RS422 interface from channel B of SCC 101 and 102
Transfer the data to 2.

The bootstrap test and quality logic test of the CPU 100 are stored in the PROM 103. Data received from VMEbus 2-8 is provided to local memory 105 via transceiver 107 and address MUX 108.
ME Bus 2-8 can be stored in local memory 105 via transceiver 106 at the address indicated by the address signal. This data is read by the CPU 100 from the local memory 105 and produces an address on the CPU address bus 111 and address MUX 108. This address can also be placed on VMEbus 2-8 via transceiver 109 and transceiver 107. Application software is stored in local memory 105.

Data from computer 6 to RS232 channel and SCC10
Received on channel B of 1. This data is available on transceiver 104 and transceiver 106 on CPU data bus 110.
Via the VMEbus 2-8.

The computer 6a is in charge of all control of the NAC 3a. At startup, the microcode in PROM 103 supports the self-test operation, allowing itself to boot from computer 6a. By loading the program into local memory 105, computer 6a commands the operation of all CSUs 2a. If CSU 2a loses connection with computer 6a, it establishes contact with computer 6n. In addition to controlling the computer 6a, polling of the communication line may be configured, such as resolving a fault detected at the CSU 2a by switching a spare device to an active service state for replacement of a faulty or failing device. Provides control commands.

The operation of the network processor 2-10a will be described. However, the network processor 2-10b is the network processor 2-1.
It is a duplicate of 0a. Both network processors 2-10a and 2
-10b is shared by the load and any part of it. For example, the network processor 2-10a is SIO2-6a and 2-6.
The network processor 2-10b communicates with SIO2-6c, 2-
It can communicate with 6d, 2-6e and 2-6f. Either of the network processors 2-10a or 2-10b can communicate with SIOs 2-6a through 2-6f if one is in service.

In normal operation, the main role of the CPU 6a is to relay messages between the terminal 4 and the financial institution 10.

Figure 7 shows the terminal path or MODEM for CPU2.
FIG. 7 is a block diagram of the steps performed by computer 6a to test if the SIO is faulty. As a result of this test, the CPU 2a switches to the spare MODEM / SIO and notifies the network management system 14 of the failure of the terminal, MODEM or SIO.

Block 6-1 receives a communication line indication from the CSU 2a in question. Typical signals are time-out signals, and MODEM
It is a no data setting ready (DSR) signal that indicates the dropout of.

Block 6-2 commands the CSU 2a to perform a remote line test by energizing a relay on the malfunctioning line.

Decision block 6-18 branches to block 6-4 if the test indicates a failed communication link. Block 6
-4 sends a message to the network to notify the network management system 14 of the failure.

If the test is satisfactory, block 6-3 tests the remote terminal. For this, the relays of relay modules 2-2a to 2-2f must be de-energized.
Starting all further tests does not require relay switching.

Decision block 6-5 determines if the test can be performed by receiving a response from CSU 2a.

If the test is feasible, decision block 6-6
If the test to MODA fails, branch to blocks 6-8. Block 6-8 notifies the network management system 14 of the failure of the terminal 4. If this test succeeds, blocks 6-7 tell CSU2a which MODEM in question.
And SIO to perform a line loopback test.

Decision block 6-9 determines if MODEM / SIO can perform the test. If so, decision block 6-10 determines if the test failed. If the test fails, blocks 6-12 notify the network management system 14 of a local MODEM failure.

Block 6-13 then commands the CSU 2a to switch to the spare MODEM / SIO.

If decision block 6-9 indicates that the CSU 2a was unable to perform the test, or decision block 6-10 indicates that the test failed, then block 6-11 performs a local SIO line loopback test. .

Decision block 6-14 determines if the test was successful. If the test is not successful, block 6-
At 15, the CSU 2a is commanded to switch to the spare MODEM and provides an indication of the faulty SIO.

Block 6-17 notifies the network management system 14 of the failed SIO.

If decision block 6-14 indicates that the test was successful, block 6-16 notifies the network management system 14 that the test was successful and the system continues with further test operations. Absent.

FIG. 8 is a block diagram of the steps performed by CSU 2a to ensure that computer 6a is running and, if not, to switch to computer 6n.

Block 2-1 sends a "beat" signal to the computer 6a.

Decision block 2-2 receives a response that computer 6a has received a "beat" signal. If this response is not received, block 2-3 starts a 500 μsec timer T1. This timer T1 is reset if a "beat" signal is received before 500 μsec has elapsed.

Decision block 2-4 is 500μ without a "beat" signal
Test if seconds have passed. If the time has not expired, block 2-1 issues another "beat" signal.

If decision block 2-4 indicates that timer T1 has expired, block 2-5 indicates computer 6n.
Establish a connection with.

The block 2-6 notifies the computer 6n that the computer 6a is in the inactive state.
Notify.

Blocks 2-7 transmit a "beat" signal to computer 6n and continue testing computer 6n.

FIG. 9 is a block diagram showing the steps performed by computer 6a to test whether CSU 2a is operational.

Block 6-50 sends a "beat" signal to CSU 2a.
Decision block 6-51 tests for the response from CSU 2a to the "beat" signal. If this response is received, blocks 6-50 again issue this "beat" signal. If this response is not received, block 6
The −52 starts the 100 μs timer T2.

Decision block 6-53 tests whether the timer T2 expires. If so, block 6-54 directs the other network processors in CSU 2a to take over the failed network processor.

Block 6-55 notifies the network management system 14 of the configuration change.

Note that the duration of timer 2 is much shorter than the duration of timer 1. The reason for this is to handle the case where the communication path between the network processor (2-10a or 2-10b) of the CSU 2a fails. This allows other network processors in the CSU 2a to take over. If the time outs didn't make a big difference, then the actual CSU2a
CSU2 when the second network processor takes over the full load
a can switch to computer 6n. This avoids the problem of CSU 2a being simultaneously supported by computers 6a and 6n.

Although the present invention has been shown and described with respect to preferred embodiments thereof, it will be appreciated by those skilled in the art that changes in the above and other forms are possible without departing from the spirit and scope of the invention.

[Brief description of drawings]

1 is a block diagram showing the entire system, FIG. 2 is a block diagram showing a network access controller, FIG. 3 is a logic diagram of a relay module, FIG. 4 is a logic diagram of a control module, and FIG. FIG. 6 is a block diagram showing a serial I / O module, FIG. 6 is a block diagram showing a network processor, and FIG. 7 is a block diagram showing steps performed by a computer 6a for testing CSU2a MODEM / SIO and terminal communication connection. FIG. 8 is a block diagram showing the steps performed by CSU 2a to ensure that computer 6a operates, and FIG. 9 is a block diagram showing the steps performed by computer 6a to test whether CSU 2a operates. is there. 1 ... Relay module, 2 ... Communication server device (CS
U), 3 ... Network access controller (NAC), 4
...... Point of Service (POS) terminal, 6 ……
Computer, 8 ... Communication network, 10 ... Financial institution computer system, 12 ... Subscriber access facility, 14 ...
… Circuit network management computer system, 16 …… communication line, 22 …… relay module, 100 …… CPU, 101 …… S
CC, 103 ... PROM, 104, 106, 107, 109 ... Transceiver, 105 ... Local memory, 108 ... Address MUX, 110 ...
… CPU data bus, 111… CPU address bus, 120…
… Microprocessor (µPA), 121 …… Microprocessor (µPB), 122 …… Receiver (RCVR), 123 …… Driver (DRVR), 125 …… Driver, 126-129 …… Transceiver, 130 …… Programmable array・ Logic (P
AL), 132 ... A bus, 133 ... B bus, 134 ... junction point, 135 ... AND junction point, 136 ... remote line test, 201-
206, 207 …… Driver, 211-216, 217 …… Relay, 401
~ 406 ... MODEM, 607 ... address controller, 608 ... address / control buffer, 611 ... data bus.

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Claims (3)

[Claims] 1. A flexible data communication system for transferring information between a plurality of subscriber terminals (4) and a communication network (8), comprising a relay for each terminal, said data communication system comprising: Relay devices (2-2a to 2-2) connected to exchange information with a plurality of terminals
f), a modem device (2) including a modem for each terminal and a plurality of spare modems, connected to said relay device, whereby an activated relay connects each terminal to its respective modem.
-4a-2-4f) and data connected to communicate with all of the modems.
A bus (2-8), each of which is connected to the bus, transfers information received from the modem via the bus and information to be transferred to the modem via the bus, and further transfers the information to the relay device. Processor means having first and second processors (2-10a, 2-10b) for generating control signals enabling control, respectively connected to said processor means and said communication network, respectively said processor means First and second computers (6a, 6n) for passing information transferred between the communication network and the communication circuit to control the processor means, respectively.
And a computer means connected to the processor means and the relay device, and controlling the relay device in response to a control signal from the processor means to cause one of the standby modems to fail. Control device (2-1 that connects with the connected terminal)
2) A data communication system characterized by having. 2. The computer means, when one of the first and second processors becomes inoperable, transfers all the communication load of the processor means to the other of the processors. The data communication system according to claim 1, wherein the data communication system operates as follows. 3. Normally, only one of said computers is operable for the execution of the control of said processor means, and if that one computer fails, said processor means will control said control of said other means. The data communication system according to claim 1, wherein the data communication system is executed by a computer.