JPH0691522B2 - Synchronous signal generator and method - Google Patents

Description

FIELD OF THE INVENTION The present invention relates generally to synchronization of digital data streams, and more particularly to synchronization for accurately reproducing information in a data stream received from a transmission channel. Signal generating apparatus and synchronizing signal generating method. It is about.

[Prior Art] In a data transmission method, data synchronization is required in order to continuously read and reproduce transmitted information of a data stream. Generally, in the past, many schemes have involved a synchronization sequence at the beginning of each information data block to facilitate this task. Reproduction of the data is achieved by confirming the synchronization sequence and identifying the end of the sequence. Once the sync data indicating the end of the sequence has been identified, the information data block is identified as the data that follows this sequence for a predetermined interval.

Reliable detection of the synchronization sequence of the transmitted data stream is difficult because the sequence itself is partly affected by transmission errors. Of course, the detection of the synchronization sequence becomes more difficult as the data rate increases. The longer the sequence, the greater the probability of being able to detect the transmitted sequence, but the greater the length of the sequence, the greater the likelihood that its constituent parts will be received differently from the signal before transmission. .

Generally, each of these synchronization sequences consists of a predefined set of characters or symbols that occur in a time-ordered sequence. With this technique, if one particular character is received that is not in the character set,
It is considered not part of the sequence and is immediately abandoned. However, there is an inherent ambiguity or ambiguity of this method when the received symbol is one character of the character set but out of the correct order. If the preceding symbol is erroneous or the symbol currently being received is erroneous, then there is ambiguity. Therefore, in order to reliably detect this type of synchronization sequence, it is necessary to provide a means for resolving this ambiguity.

Although the invention described herein is compatible with any stream digital data transmission scheme, it has particular utility in recording and reproducing data on magnetic tape recording / reproducing devices. In a recently developed helical scan magnetic tape recorder / player for digitized television signals, the same track on the magnetic tape is recorded separately at separate locations along each track. Is included. Video data occupies about 90% of the data recorded on one track, and audio data occupies only a small portion of the data on each track. Unlike the sync sequence included in the video data, the sync sequence included in the audio data is not repetitive.

Therefore, a reliable sequence detection scheme different from that used in video playback is needed to correctly play audio data. The audio playback method must be able to play the sync sequence in one pass, because it has little or no sequence repeatability for the audio data, and must detect relatively short data sequences. Therefore, great reliability is required.

In addition, such schemes discriminate between an erroneous sync sequence that includes a partial string or sequence of sync sequence signals in the correct order and an actual sync sequence that is in the correct order but contains symbol errors. Must be able to. The reason is that the magnetic recording and playback medium may have been previously recorded, so that a partial synchronization sequence (a previously recorded sequence that has been overwritten and not completely erased) is detected. There is a possibility. This possibility must be ruled out to ensure that the correct sequence is identified for the information to be reproduced, as well as erroneous sequence symbols.

Therefore, it is an object of the present invention to reliably detect the sync sequence of a digital data stream even if the sequence contains some errors.

Yet another object of the present invention is to synchronize the timing of data blocks with a sync sequence by generating a timing signal for the detected sync sequence.

Accordingly, the present invention provides an apparatus for reliably detecting a sync sequence of a digital data stream.
A plurality of consecutive different sync symbols of a predetermined sequence are inserted in the data stream for transmission with the data stream. The synchronization sequence occupies a predetermined time period ahead of the stream of data blocks having the timing to be synchronized. At the receiver, the symbols or characters forming this sequence are detected from the received data stream and the transmitted synchronization sequence is identified. By identifying the sync sequence, a sync signal indicating the end of the identified sequence is generated, thereby signaling the beginning of the subsequent data block.

The present invention tests whether the received symbol is at a time position corresponding to the time position of the symbol of the predetermined transmit synchronization sequence. This test generates a series of candidate sequence symbols, compares the received symbols in the received sequence with the candidate symbols in the candidate sequence, and compares whether the candidate sequence corresponds to the received sequence. Generally, this comparison technique is performed by generating a predetermined sequence of symbols starting with a selected candidate symbol.

So if the candidate symbol is in the correct time position,
Comparing the generated candidate sequence and the received sequence, the respective symbols match at each time position. First, the received symbol that was first received and identified as a valid symbol is used as the first candidate symbol. Ambiguity exists when the received valid symbol does not match the symbol at the corresponding location in the candidate sequence.

The candidate sequence is compared to the received symbol sequence, and if the received symbol and the candidate sequence symbol match, the matched candidate sequence is counted. The number of matches for each candidate sequence is then counted and compared with the number of other candidate sequences in the logic program to determine which candidate sequence best corresponds to the predetermined sequence in the transmitted data stream. It From the timing of the most likely determined candidate sequence, the end of the predetermined sequence is estimated and a sync signal is generated to identify the start of the next information data block.

In one embodiment of the present invention, the operation of the present invention includes a predetermined symbol sequence in which the sync sequence represents a countdown sequence of a number from 6 to 7 7
3 trials 3 times Candidate voting (voting).
When the synchronization sequence enters the candidate sequence generation circuit, the first symbol recognized as the symbol corresponding to the predetermined sequence causes the control means to load the number corresponding to the first symbol into the first candidate sequence generator. . The candidate sequence generator then counts down from the number represented by the first symbol at the rate of the received symbols to generate the candidate sequence.

Since the first recognized symbol is ambiguous, the first symbol is tested to determine if it is part of the transmitted constant sequence. If it is a confirmed symbol, then it is identified as a candidate symbol that represents a particular position or time sequence in a predetermined sequence. If the candidate symbol represents a sequence corresponding to the transmitted sequence, the subsequently received symbol is compared to the next symbol in the candidate sequence. In such a case, the first candidate sequence generator is counted down to the last number of candidate sequences (zero in this case). Each of the subsequently received symbols is compared to the first candidate sequence,
If no match occurs, the control means loads another candidate sequence generator with the number of received symbols that do not match the first candidate sequence. The other counters count down in a predetermined sequence in the same way as the first candidate sequence generator. Similarly, the received symbol is then detected, compared to the candidate sequence, and if no match occurs the next received sequence is loaded by the control means into the third candidate sequence generator, the third candidate sequence generator Generate a third candidate sequence.

In the preferred embodiment, the control means executes a logic program to determine which symbols to load and when to reset the candidate candidate sequence generator. Further, the control means resets or clears the associated counter when a new received symbol is loaded into the candidate sequence generator. When a valid symbol is received and the symbol does not match the candidate sequence symbol, the control means selects another candidate sequence generator.

This logic program either reaches the final symbol,
Alternatively, under special conditions such that the candidate sequence is selected to best represent the predetermined sequence, it includes logic to control the contents of the candidate counter. This logic of the control means is stored in read only memory (ROM),
The memory is addressed to output control signals from the memory to the candidate sequence generator and counter circuits according to inputs (match, valid data, candidate selection, final symbol generation, counter utilization, etc.). This configuration can easily change the criteria for selecting candidate symbols by reprogramming the ROM.

In this way, the three counters are counted down from the number represented by the received symbol, the content of which is compared with the received symbol and the candidate symbol represented by the content of the received symbol and the candidate sequence symbol generated by the candidate sequence generator. It is determined whether there is a match with the sequence. Each match is determined by a compare circuit and each is counted in a separate counter circuit associated with the candidate sequence generator. The output of the counter circuit is transmitted to a candidate sequence selection circuit, and based on the counted value, the candidate sequence selection circuit determines which of the candidate sequences most corresponds to a predetermined sequence included in the transmission data. (Ie it is to choose the winner). When a candidate is declared or selected as a winner, its final symbol indicates that the received data has completed the synchronization sequence and is followed by a block of information data. The sync signal is generated along with the generation of the final symbol, and signals the start of the data block in the received information.

In the preferred embodiment, the candidate sequence selection circuit has which candidate has the most promising vote selected.
And a logic program that determines whether to select a winner based on that criterion. The logic program also includes logic to make candidate sequence selection decisions based on special conditions such as tie draws by counted votes, minimum passing (winning) votes and landslide victory votes. . This logic of the candidate sequence selection circuit addresses a read only memory (ROM) and reads the candidate sequence from this memory according to an input (voting etc.). This configuration can easily change the criteria for selecting candidate symbols by reprogramming the ROM.

The disclosed preferred scheme is a three-trial three-choice scheme that makes a selection based on the largest number of votes among the three most similar candidates to represent a sequence of transmitted synchronized 7 symbols. The number of symbols in the sequence determines the maximum number of possible votes (6 in this example) for one candidate. The number of trials and the number of candidates chosen to configure the system is a function of the error rate of the transmission channel. Complete correlation between the number of trials required and candidates for a given error rate is difficult to achieve, but statistical simulation of the system and well-known transmission channel error distribution are used to recover the correct synchronization sequence. It is possible to reach an allowable probability distribution.

In general, the greater the number of symbols (trials) in the sequence, and the greater the number of candidates allowed, the greater the probability of correctly reproducing the sync sequence. Therefore, candidates and trials are made until the "reduced return point" is reached until the error rate falls below an acceptable level. The number of candidates tested is selected according to the probability of receiving an erroneous symbol. A "trade-off" is made on whether to add more candidates or more trials.
The former increases the circuitry for the sync signal generation scheme, and the latter increases the "overhead" in the transmitted data, increasing the likelihood that at least some of the symbols will be transmitted in error.

Furthermore, for those schemes in which there is a possibility of replaying a partial sequence or a sequence that has not been wholly erased, the minimum vote count increases the likelihood of replaying the correct sequence. In the overall error rate,
Simulations indicate that if two, three or more symbols are detected in the correct order, they may be detecting the correct sequence. Increasing the minimum number of votes increases the likelihood that a candidate received before being selected will have the detected sequence correct. However, the trade-off increases the minimum vote and reduces the chance of identifying it as a predetermined sequence in the received data.

[Means for Solving the Problem] The sync signal generator of the present invention provides a predetermined sync sequence (20) of N different symbols (A to N) that are integers greater than 2 preceding a data block. A sync signal generator (16) for generating a sync signal representative of the starting time position of a data block (24) of the transmitted data stream including: (a) selected in synchronization with a symbol of said received data stream; A candidate sequence generation means (32) for generating each candidate symbol in a given sequence starting with one of the given identification symbols, and (b) each given identification symbol and said candidate sequence generation means (32) Compare with the generated candidate symbol,
Comparison means (30) that outputs a match signal when these match
(C) counter means (34) for individually counting the number of coincidence signals from each comparing means; and (d) each candidate sequence in accordance with the number of coincidence signals counted by the counter means (34). Candidate sequence selection means (38) for generating a selection signal for identification, and (e) Final symbol detection means for generating a synchronization signal when the final symbol of the candidate sequence selected according to the selection signal is generated. (40) and (f) the candidate sequence for which a candidate sequence is not generated, a start candidate symbol corresponding to the predetermined symbol currently identified according to the coincidence signal and each state of the candidate sequence generation means. And a control means (36) for loading the generation means and clearing the counter means (34).

Also, the synchronization signal generating method of the present invention uses N (an integer greater than 2) different predetermined symbols in a predetermined sequence before the data block to be synchronized to synchronize the timing of the data stream. In the method of identifying a predetermined symbol of the received data stream, generating a candidate sequence of candidate symbols corresponding to symbols in the selected predetermined sequence starting with each selected and identified predetermined symbol, each identified Compared to each temporarily corresponding symbol of each of the candidate sequences, generating each match signal when each symbol matches, and the current identified predetermined symbol temporarily matches the corresponding symbol. If not, the generation of the candidate sequence is started at the candidate symbol corresponding to the current predetermined symbol, and each candidate is generated. Selecting one of the candidate sequences most likely to be in a given transmitted sequence by counting the number of match signals for the sequence and comparing the number of matches counted for each of the candidate sequences, Comprising synchronizing the data blocks at a time identified by the end of the selected candidate sequence.

[Embodiment] FIG. 1 shows a block diagram of a synchronizing signal generating circuit 16 for a serial digital data stream constructed according to the present invention. A generalized format of such serial digital data is shown in FIG. 2 where the data alternately comprises sync sequences 20 and data blocks 24, each sync sequence 20 being adjacent to a data block 24. These data packets are sent asynchronously or synchronously to the sync signal generating circuit 16 via the transmission channel 8, and the sync signal generating circuit 16 synchronizes so as to identify the start of the data block 24 according to the received sync sequence 20. Generate signal 22. A circuit or user equipment (not shown) downstream of the sync signal generation circuit 16 receives the data stream via the data path 18 and uses the sync signal 22 to synchronize the recovered information data of the data block 24.

The sync sequence 20 and the data blocks 24 can be constructed by any number of intermediate bit splits, but for convenience and compatibility with other data schemes, they are typically split into conventional byte or nibble formats. The present invention can be applied to any system for transmitting serial digital data shown in the format of FIG. 2, but the digital format of the figure is an audio data portion to be reproduced by a helical scanning magnetic tape recording / reproducing apparatus. Good.

The sync sequence 20 included in the data stream consists of a plurality of sync units, from a first sync unit 26 to a last sync unit 28. One sync unit is a fixed bit pattern (FP) and one character or one symbol,
For example, A in the synchronization unit 26 and. These symbols are different throughout the sequence and are arranged in a predetermined order for convenience of generation and reproduction, such as a countdown sequence 6,5,4,3,2,1,0. The fixed bit pattern (FP) has the proper number of bits to identify the word boundaries of the symbols and to form the identified sync patterns in the data stream so that each symbol of the sync sequence can be positioned. Each symbol A, B, C, D, ... N of the synchronization unit
Are arbitrary but all different and form a single predetermined set of sequences identified by their order. Further, the synchronization sequence 20 can be extended for a period of time by having fixed bit patterns and symbols in the predetermined sequence. Thus, in reproducing a sync sequence having only a few valid symbols in the correct time sequence, once the valid sequence is recognized, the end of the sequence is generated by the timing circuit in the sync signal generating circuit. Also, if the valid symbol is reproduced earlier than the sync sequence, there is an error in the subsequent portion of this sequence and further detection is done.

Each symbol A, B, C, D ... N is represented by a suitable digital code using a suitable number of bits. This code can check the validity of the symbols because only a selected set of symbols in the synchronization sequence is used. Since errors in the transmission channel affect the reception of sync data, it does a check on the symbols to determine if the correct sync sequence has been reproduced. After the detection of the symbol sequence, the synchronization sequence 20 is effectively detected and the synchronization signal 22 indicating that the following data is information data is generated, and then the data block 24 is identified by the synchronization signal generation circuit 16.

The format of the sync sequence, as shown in FIG. 2, assists in its successful reproduction in a number of ways. First, the fixed bit pattern (FP) is of sufficient length to reliably indicate that one symbol follows. Each symbol A, B, C, D ... N is pre-defined so that if a symbol that is not a known set is reproduced, then this reproduced symbol is known to be erroneous. Furthermore, this symbol becomes a predetermined sequence if a valid symbol is identified and it is recognized that it is in the correct position in the sequence and the rest of the sequence is generated by its known order and duration. . Furthermore, it enables the reproduction of the sequence of symbols within a certain period even if there is an error in the subsequent or last symbol of the received sequence. If the first or middle symbol of the sync sequence is identified as belonging to the set of symbols of the sync sequence and in the correct order, the subsequent symbols are generated. Increasing the length of the synchronization sequence increases the likelihood that the sequence of symbols will be reliably reproduced. The reason is that the more symbols in the sequence, the greater the probability that at least some will be effectively received after transmission.

Returning to FIG. 1 again, the sync signal generating circuit 16 receives a serial data stream from the oscillator (not shown) via the transmission channel 8. This data stream is transmitted in the format shown in FIG.
Given to twelve. The serial-to-parallel converter 12 converts the serial data stream into parallel word form and outputs the serial stream of words to the downstream data path 18. Although the serial-to-parallel converter 12 can convert bit-serial data into a multi-bit word of arbitrary length, an 8-bit word (byte format) is used in one embodiment of the present invention. This partition is compatible with most devices. In this embodiment, the synchronization unit of the synchronization sequence includes FP data of 36 bits and symbol data of 4 bits, but other combinations may be used. In this format, each sync unit is 5 bytes long,
The entire sequence is 35 bytes long for a 7 symbol sequence.

The timing signals needed to detect the boundaries of the words to be converted are produced by the word sync detector 10.
The detector 10 detects the occurrence of each fixed bit pattern (FP) and byte boundary in the data stream and generates a respective word sync timing signal to the serial-to-parallel converter 12 via line 11. The output of the data path 18 is not only a synchronization unit 26 ... 28 in serial word format, but also a data block 24 in serial word format. When the word sync detector 10 detects a fixed bit pattern (FP) in the data stream, it also generates a symbol timing signal on line 13 to enable the valid checker 14.
Send to. These signals are sync symbols A, B, C, D.
.. indicates the boundary of N and indicates the separation of the data in the data block 24 from the symbol.

The symbol timing signal on line 13 enables the valid checker circuit 14 to extract the 4-bit symbol of the sync sequence from the word serial data stream on the data path 18. The effective checker circuit 14 also has a fixed pattern FP.
, The extra 4-bit symbols of and are checked to see if these symbols are part of the character set used in the transmission sequence. This confirmation can be achieved by many techniques.

In this embodiment, the synchronization sequence is "6" to "0".
, And only 3 bits are used to generate these symbols.
The fourth bit is used as an odd parity to identify the correct or valid symbol and the incorrect or invalid symbol is converted by the valid checker 14 to the unused symbol "7". The symbols of the receive sequence are received by the sync signal generation circuit 16 from the valid checker 14 via line 15 and determine the end of the sync signal 20. The sync signal generation circuit 16 generates a block sync signal 22 for use in a circuit in the subsequent stage. The word symbol timing signal provided from the word sync detector 10 to the sync signal generation circuit 16 via the line 19 is a series of clocks generated based on the timing of the bit serial data received by the word sync detector 10 from the transmission line 8. It is a pulse.

FIG. 3 shows word symbol timing signals CT11-CT15 and a reset signal (RESE) generated by the word sync detector 10.
T) is shown. Furthermore, the symbol valid signal CL11 is the validity checker.
It is generated by 14 and is given to the synchronizing signal generating circuit 16 via the line 17.

The sync unit 26 is divided into five 8-bit bytes, the fixed bit pulse (FP) is 4.5 bytes and the symbol A is 0.5 bytes (4 bits). The word symbol timing signals CT11-CT15 are generated by the word sync detector 10 at the five byte boundaries of each sync unit. These word symbol timing signals form a five phase clock to move data through the sync signal generator circuit 16 in one sync unit period. Following the CT11 signal, the symbol valid signal CL11 is generated by the validity checker 14 before the word symbol timing signal CT15. CL11 signal is
Indicates that the validity checker 14 has found an invalid symbol that must be abandoned. The initialization or RESET signal precedes the first timing signal CT11 of the first received symbol. Then, before the circuit is reset again,
Word symbol timing signal at the end of the detection sequence
When CT15 occurs, detection is performed until the sync signal No. 22 occurs.

FIG. 4 shows a detailed block diagram of a preferred configuration of the sync signal generator circuit 16. This circuit detects the sync sequence and generates a sync signal 22. The operation of the synchronization signal generation circuit 16 will be described below.

The sync signal generator circuit 16 includes a controller 36, which receives the timing signals and the plurality of status indicating signals and controls the loading of the plurality of candidate sequence generators 32 and the resetting or clearing of the associated counter circuit 34. The controller 36 operates in a programmed sequence, which receives the first valid symbol and is initialized. After that, until the end of the synchronization sequence is detected, or the controller 36 resets the reset circuit.
The program executes the steps from 43 until reset by a reset signal on line 49.

In general, the controller 36 takes the current symbol from the outputs of the plurality of comparators 30 and the match circuit 45 as one of the candidate sequence generators 32.
First decide whether to load. Each comparator 30 compares the output of the corresponding candidate sequence generator 32 with the symbol sequence received via line 15, and if these two
If the two are equal, a match signal is output. Matching circuit 45 generates a new candidate symbol to controller 36 via line 51 if no match is found and symbol valid signal CL11 on line 17 indicates the presence of a valid symbol.

If none of the comparators 30 indicate a match for the current symbol and that symbol is valid, there is ambiguity in the received sequence that must be resolved. When the match circuit 45 produces a mismatch signal, the controller 36 loads the current symbol into the available candidate sequence generator 32 as needed. This road is
It is controlled by line 41 which determines which candidate sequence generator 32 should load the current received symbol. Line 41 is also used to clear the counter circuit 34 associated with this loaded candidate sequence generator 32. The controller 36 also receives signals from the candidate sequence selection circuit 38 via line 47 and from the candidate sequence generator 32 via line 39, these signals identifying the states of the candidate sequences. The status signal on line 39 indicates when the last symbol of the sequence has reached one of the candidate sequence generators 32 and the status signal on line 47 indicates that one of the candidate sequences is most similar to the transmitted sequence. Indicate when it was selected.

Candidate sequence generator 32 is used to generate the portion of the predetermined transmission sequence that follows each candidate symbol. Therefore, the candidate sequence generator 32 regenerates the portion of the entire transmitted sequence beginning with the particular candidate symbol loaded by the controller 36 and ending with the last symbol of the predetermined sequence. Thus, if one candidate symbol is loaded into one of the candidate sequence generators 32 and reproduced correctly, the output of the candidate sequence generator 32 corresponds exactly to the transmission sequence of the predetermined synchronization pattern. To do. For example, even in the countdown sequence 6,5,4,3,2,1,0, if the symbol "5"
, Is loaded into each candidate sequence generator 32 and outputs the remaining sequence 4,3,2,1,0 at the appropriate time. If symbol "5" was part of the transmit sequence, the rest of this transmit sequence would match the output of candidate sequence generator 32.
However, this is not necessarily the sequence received by the sync signal generation circuit 16 due to transmission errors.

The significance of generating the subsequent symbols of the predetermined sequence from the candidate symbols is that thereby the error in the receiving part of the sequence after the reproduced symbol can be neglected if necessary. Therefore, fewer valid symbols need to be recovered to determine the end of the actual sequence. The controller 36 loads many candidate symbols when there is ambiguity in the received sequence and there are many candidate sequence generators 32 available. The preferred embodiment shown in FIG. 4 is a three-candidate scheme in which the number of candidate sequence generators 32 is three. Increasing the number of candidate sequence generators 32 increases the likelihood that one of the candidate symbols will match the transmitted symbol correctly.

There are many logical sequences and criteria that can be used to determine when a candidate symbol must be loaded into the candidate sequence generator 32 and one of which must be cleared from the device.

The preferred logic sequence performed by controller 36 is described in more detail below. In general, if there is ambiguity, the currently received valid symbol becomes a new candidate. The valid candidate symbols are sequentially counted down to the last symbol, which is cleared from the counter circuit 32 if no candidate sequence is selected before it is generated, i.e. it fails as a candidate.
Furthermore, if the current symbol is the last symbol in the transmitted sequence, it cannot receive any vote. Therefore, it is not loaded into the counter circuit 32 for matching processing. Other criteria such as all candidate sequence selection outputs are used.

The output of the candidate sequence generator 32 is input to each associated comparator 30. Comparator 30 receives from line 15 another input received symbol sequence. The match between the symbol sequence and the candidate sequence causes a match signal, ie, a vote for the candidate symbol that generated this match. These votes are counted in the respective counter circuits 34, and these count values are transmitted to the candidate sequence selection circuit 38.

The candidate sequence selection circuit 38 determines which candidate sequence to select, based on the logic algorithm and the count output of the counter circuit 34, as to which best represents the original transmission synchronization sequence. There are many algorithms by which the closest candidate sequence may be selected based on the voting count value. However, in this example, the minimum total counter value is used to select the tentative winner, and if the sequence of tentative winners reaches the final symbol, other candidate symbols will receive more votes. If not, the candidate sequence is selected to generate sync signal 22.

The final symbol is determined by the selected sequence generator 32.
Is achieved by the gated final symbol detector 40. Upon detection of the final symbol of the selected candidate sequence generator 32, the final symbol detection circuit 40
22 is output.

FIG. 5 shows the preferred logic algorithm performed by the candidate sequence selection circuit 38. V1 is the count number counted by the first counter circuit 34 for the first candidate sequence, and V2 is the second count for the second candidate sequence.
Is a count number counted by the counter circuit 34 of
V3 is a third counter circuit for the third candidate sequence
It is the number of counts counted at 34. These are output from each counter circuit 34. This logic indicates which candidate sequences should be selected based on the voting count value for each candidate sequence.

The selection of candidate sequences is based on candidate sequences that either have a greater number of votes or at least an equal number of votes than other candidate sequences, and have a vote count over at least the total number of votes passed. The pass-vote count is the minimum number of frequencies that must be accumulated before one candidate sequence is selected. In addition, there may be other criteria such that if a candidate sequence counts a number greater than or equal to the count of landslide wins, that candidate sequence is selected. This landslide victory count is the number of votes that guarantees that the candidate sequence is a transmission sequence. For example, a number greater than any two candidate sequences would be such a landslide victory count. In the case of the 7-trial method of this embodiment, the vote count of landslide victory is 4. Other criteria can be used for the number of landslide wins.

This logic selects a candidate sequence based on whether V1 is less than V2, equal to V2, or greater than V2. The same applies to V3.

If V1 is greater than V2, then V1 is further compared to V3 to determine if it is greater than, equal to, or less than V3. For the portion of the second candidate sequence that was deleted, it is determined whether the first or third candidate sequence is selected based on the larger number of votes.

When V1 is the same as V2, the first and third candidates are compared. In the second condition of V1 = V2, V1 is again compared to V3 to determine if V1 is greater than, equal to, or less than V3. If V1 = V2, the first candidate is selected for subsequent candidates. if
If V3 is greater than V1, then the third candidate is selected.

Similarly, under the condition that V1 is less than V2, V2 is compared to V3 to determine if V2 is greater than, equal to, or less than V3. In the case as described above, a decision is made to select either the second candidate sequence or the third candidate sequence depending on which is larger, and in the case of ties, the second candidate sequence is the third candidate sequence. Selected for sequence. Although the case of ties is arbitrarily determined, selecting the previous candidate sequence seems to increase the likelihood of determining the correct sequence.

FIG. 6 is a timing chart showing a two-vote voting system of three candidates of seven trials. Sync symbol sequence is numeric symbol 0
It becomes -6, and the sequence of this sequence is order 6-5-4-
It becomes 3-2-1-0. With these symbols and sequences, the method described above can be implemented particularly easily.

Line A in FIG. 6 shows the original sequence of transmitted symbols. It is assumed that 4,6,4, E, 2,1,3 sync sequences are regenerated from the serial data stream of the transmission channel 8 and provided to the sync signal generating circuit 16 as a plurality of symbols and timing signals. This played sequence is the sixth
It is shown in line B of the figure. The symbol E indicates a reproduced character that is not in the set of symbols, that is, there is an error.

Line C in FIG. 6 shows the contents of the first candidate sequence generator 32. The content of the counter circuit 34 associated with this first candidate sequence generator 32 is the line D immediately below the counter.
Shown in. Similarly, on lines E and G, the second and third
The contents of the candidate sequence generators 32 are shown and their associated counter circuit 34 contents are shown on lines F and H, respectively. In the first, second and third candidate sequence generator 32, the candidate sequence generators are loaded in the order of candidate symbols. Any candidate sequence generator 32 can be the first, second, or third candidate sequence generator because there are many different algorithms for loading the candidate sequence generator.

When the first symbol "4" of the received sequence is input to the first candidate sequence counter 32 on line C, it initializes the candidate sequence operation following the predetermined sequence. Therefore, the first candidate sequence generator starts with the symbol "4", then counts down and ends with the subsequent part of the predetermined sequence, in the order "3-2-1-0" corresponding to the sequence. The comparator 30 corresponding to this candidate symbol compares the input symbol of the received sequence with the sequence symbol generated by the first candidate sequence generator. As can be seen in line D of FIG. 6, the associated counter circuit 34 because the symbols on the received sequence on line B also do not match the symbols generated by the first candidate sequence generation crown on line C.
Does not count votes for this candidate sequence.
When the first sequence generator produces the final symbol "0" and no candidate is selected, this candidate is withdrawn by clearing the first sequence generator so that it can be accessed by other subsequent candidates. Become.

This symbol is ambiguous because the second symbol "6" in the received sequence on line B does not match the second symbol "3" generated by the first candidate sequence generator on line C. Is. Therefore, the symbol "6" is input to the second candidate sequence generator on line E and becomes the second candidate. This allows the second candidate sequence generator to generate a second candidate sequence 6-5-4.
-3-2-1-0 is generated. Similarly, the symbols generated from the second candidate sequence generator are compared in time order with the corresponding symbols sequentially regenerated from the input sequence to make a match comparison.

The third symbol "4" of the received sequence on line B is the same as any of the two possible candidates "2" and "5" generated by the first candidate sequence generator and the second candidate sequence generator. There is no match and therefore the vote is not counted against either the first candidate sequence or the second candidate sequence.

The symbol "4" in the received sequence causes ambiguity because it does not match any candidate sequence and is therefore the third candidate input to the third candidate sequence generator on line G. This time the third candidate "2" of the third candidate sequence generator matches the input symbol of the received sequence on line B. However, the fourth symbol "E" in the receive sequence is invalid and will not cause a vote for any of the three candidates. Thus, the fourth symbol of the received sequence is not counted because it is invalid.

No match occurs until the fifth symbol "2" of the receive sequence is reproduced, and the vote is counted only at the third candidate symbol "2" on line G. Line B
The sixth symbol "1" in the above received sequence is the third
Generate the next vote for the candidate sequence of. The symbol "1" in the received sequence matches the third sequence and no new candidate symbols are inserted or counted in the first candidate sequence generator to cause a vote. This is because no ambiguity was detected.
The last symbol "3" in the received sequence gives no match or vote, but at this point the third candidate sequence has already collected a vote of "2" as shown in line H. This is greater than the votes of the other candidate sequences and equal to or greater than the minimum winning vote count (which is 2 in this example). Therefore, this sequence is selected as the most likely
The sync signal 22 at the time of the last symbol "0" as indicated by the last symbol detection circuit 40 and as shown on line I.
To occur. The symbol "3" that does not give a match is line C
Is inserted into the empty first candidate sequence generator as shown in FIG.

FIG. 7 is an example of a 7-trial, 3-candidate, 2-vote system with a landslide victory in the "4" vote of the present invention. Lines A and B show a transmission sequence and a reception sequence, respectively. Each line CD shows the contents of the first candidate sequence generator 5 and its associated counter circuit. Lines E and F respectively show the contents of the second candidate sequence generator and its associated counter circuit. The first symbol "4" of the received sequence is loaded into the first candidate sequence generator and the second symbol "5" of the first candidate sequence generator.
And the second symbol "3" of the received sequence are compared. Since there is no match at this point, the voting for the candidate symbol is not added to the associated counter circuit, as shown in line D. The second symbol "5" in the received sequence, which represents ambiguity due to the mismatch to the first candidate sequence, becomes the second candidate symbol and is loaded into the second candidate sequence generator on line E. Subsequently, the third symbol "4" of the received sequence matches the second candidate sequence symbol "4" of the second candidate sequence generator, so that a vote occurs for this candidate sequence. No other candidate sequences are selected because the received sequence has no further ambiguity. When a cumulative landslide victory count "4" of votes is generated for the second candidate sequence as shown in line F, it is selected as the most likely candidate sequence and its final symbol "0" is the synchronization signal.
Raises 22. In this way, the second candidate sequence has the smallest voting count and has the largest count among the possible candidate sequences. When the count value of the selected candidate sequence reaches a predetermined value “4”, the landslide victory condition is declared and the selection of the candidate sequence is completed.

While the preferred embodiment of the invention has been illustrated, various modifications and changes can be made without departing from the spirit and scope of the invention as will be apparent to those skilled in the art.

[Effects of the Invention] As described above, according to the present invention, information from a received data stream can be accurately reproduced, so that a highly reliable digital data synchronization device can be obtained.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a system block diagram of a synchronous sequence detecting apparatus for a transmitted digital data stream according to an embodiment of the present invention.

FIG. 2 is a diagram showing a digital serial data stream format including an initial synchronization sequence attached to an information data block.

FIG. 3 shows a synchronizing signal generating circuit CT in the embodiment of FIG.
FIG. 11 is a timing diagram when operating according to the five phase clocks of 11 to CT15.

FIG. 4 is a detailed block diagram of the synchronizing signal generating circuit shown in FIG.

FIG. 5 is a logic diagram of a selection criterion algorithm executed by selecting a candidate sequence in the synchronization signal generating circuit.

FIG. 6 is a timing chart showing a candidate vote of the synchronizing signal generating circuit according to the present invention.

FIG. 7 is a timing chart showing a candidate vote for landslide-like victory selection of the synchronizing signal generating circuit according to the present invention.

10 …… Word sync detector 12 …… Serial-parallel converter 14 …… Effectiveness checker 16 …… Sync signal generation circuit 20 …… Sync sequence 22 …… Sync signal 24 …… Data block 26, 28 …… Sync unit 30 …… Comparator 32 …… Candidate sequence generator 34 …… Counter circuit 36 …… Controller 38 …… Candidate sequence selection circuit 40 …… Final symbol detection circuit 43 …… Reset circuit 45 …… Match circuit

Claims (15)

[Claims] 1. A start of a data block (24) of a transmitted data stream comprising a predetermined synchronization sequence (20) of N different symbols (A to N), which is an integer greater than 2 preceding the data block. A synchronization signal generator (16) for generating a synchronization signal representative of a time position, wherein: (a) during a predetermined sequence starting with one of the predetermined identification symbols selected in synchronism with the symbols of said received data stream. (B) comparing each predetermined identification symbol with the candidate symbol currently generated by the candidate sequence generating means (32),
Comparing means (30) for outputting a coincidence signal when these coincide, (c) counter means (34) for individually counting the number of coincidence signals from each comparing means, and (d) the counter means (34) ), A candidate sequence selecting means (38) for generating a selection signal for identifying each candidate sequence according to the number of coincidence signals counted in (4), and (e) the candidate sequence selected according to the selection signal A final symbol detecting means (40) for generating a synchronization signal when the final symbol occurs, and (f) the predetermined symbol currently identified according to each state of the coincidence signal and the candidate sequence generating means. A control means (36) for loading the corresponding start candidate symbol into the candidate sequence generating means that has not generated a candidate sequence and clearing the counter means (34); A synchronization signal generator characterized by the above. 2. The apparatus according to claim 1, wherein the candidate sequence generating means includes: a presettable counter that counts in a predetermined sequence and is preset corresponding to the candidate symbol. The sync signal generator according to claim 1, wherein the counter outputs a count value corresponding to the candidate symbol according to the candidate sequence, and outputs a carry signal when the final candidate symbol is reached in the candidate sequence. 3. The apparatus according to claim 2, wherein the candidate sequence generating means includes: a plurality of counters associated with each predetermined counter, wherein each counter generates the coincidence signal at each candidate counter. A synchronizing signal generator characterized in that it is stepped every time it is performed. 4. A device according to claim 3, wherein said means for generating said synchronization signal comprises: a plurality of channels connected to the output of said predetermined counter A candidate sequence selecting means for disabling one of the channels in response, a decoding means for generating an enable signal when the last symbol of the selected selected predetermined counter of the sequence is detected, and the enable signal. And a means for outputting a synchronizing signal in a predetermined time relationship in accordance with the above. 5. The apparatus of claim 4, wherein the means for generating the select signal includes: a read only memory having a plurality of addressable locations containing a control word, the read only memory Is addressed by the count output of the counter and adds the control word contained at that position to the candidate sequence selection means, the candidate sequence selection means selecting the channel associated with each given counter according to the control word. A synchronizing signal generator characterized in that. 6. A device according to claim 5, wherein the control means (36) comprises: a read-only memory having a plurality of addressable locations containing a control word, the read-only memory being the selection memory. The control word from the signal applying means, the carry output of the predetermined counter and the control word output before it are addressed to generate the predetermined counter and the control word contained in that position in the counter, the control word being The apparatus characterized in that a candidate symbol corresponding to a currently identified given symbol is loaded into one of the presettable candidate counters and each counter is reset when it reaches the end of each candidate sequence. 7. A method for synchronizing the timing of a data stream using N (integer greater than 2) different predetermined symbols in a predetermined sequence before a data block to be synchronized received. Identifying a given symbol of the data stream and generating a candidate sequence of candidate symbols corresponding to the symbols in said given sequence starting with each selected identified given symbol, each identified symbol each said candidate Compare each temporally corresponding symbol of the sequence and generate each coincidence signal when each symbol coincides, and the current said when the present predetermined symbol does not temporarily coincide with the corresponding symbol. For each candidate sequence, start the generation of said candidate sequence with a candidate symbol corresponding to a given symbol. Select one of the candidate sequences most likely to be in a given transmitted sequence by counting the number of potential signals and comparing the number of matches counted for each said candidate sequence; Synchronizing the data blocks at a time identified by the end of the candidate sequence. 8. The method of claim 7, wherein the selecting step comprises: comparing the number of matches counted for each of the candidate sequences, the candidate sequence having the largest number of matches counted. Said method comprising the step of selecting 9. The method of claim 8, wherein the selecting step further comprises: selecting a candidate sequence having the largest number of matches counted when the number of matches exceeds a minimum value. A method for generating a synchronization signal, comprising: 10. The method according to claim 9, wherein the selecting step is: selecting a candidate sequence having the largest number of matches counted when equal to a predetermined number greater than the minimum number. A method for generating a synchronization signal, comprising: 11. The method of claim 8 wherein the selecting step is: a plurality of candidate sequences is equal to the number of matches counted, and the number is greater than the number of counts for other candidates. , The step of selecting one of the candidate sequences according to a selected order of occurrence of the candidate sequences. 12. The method according to claim 11, wherein the equal number exceeds a minimum number. 13. The method according to claim 7, wherein said generating step is: starting with a candidate symbol and being currently identified when the currently identified symbol does not match a candidate symbol of a previous candidate sequence. And generating a candidate sequence corresponding to a predetermined symbol. 14. The method of claim 13, wherein the generating step comprises: loading a selected number of candidate symbols into a predetermined number of candidate sequence generators for generating each of the candidate sequences; A method of generating a synchronization signal, comprising the step of determining to utilize a candidate sequence generator for said load. 15. The method of claim 13, wherein the generating step comprises: sequentially scanning a candidate sequence generator that has not generated the candidate sequence, the scanning having the selected candidate symbol. A method for generating a synchronization signal, comprising the step of loading at least a first candidate sequence generator available in a sequence.