JPH0691397B2 - Automatic gain control circuit - Google Patents

Automatic gain control circuit

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Publication number
JPH0691397B2
JPH0691397B2 JP4254688A JP4254688A JPH0691397B2 JP H0691397 B2 JPH0691397 B2 JP H0691397B2 JP 4254688 A JP4254688 A JP 4254688A JP 4254688 A JP4254688 A JP 4254688A JP H0691397 B2 JPH0691397 B2 JP H0691397B2
Authority
JP
Japan
Prior art keywords
input
output
gain control
divider
automatic gain
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP4254688A
Other languages
Japanese (ja)
Other versions
JPH01216610A (en
Inventor
幸夫 坂田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP4254688A priority Critical patent/JPH0691397B2/en
Publication of JPH01216610A publication Critical patent/JPH01216610A/en
Publication of JPH0691397B2 publication Critical patent/JPH0691397B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、入力信号レベルが変動しても出力信号レベル
を一定に保つことができる自動利得制御回路に関するも
のである。
Description: TECHNICAL FIELD The present invention relates to an automatic gain control circuit capable of keeping an output signal level constant even if an input signal level fluctuates.

〔従来技術〕[Prior art]

第4図は、従来の自動利得制御回路の構成を示すブロッ
ク図である。従来の自動利得制御回路は図示するよう
に、入力端子1、検波器2、除算器3及び出力端子4と
で構成される。
FIG. 4 is a block diagram showing a configuration of a conventional automatic gain control circuit. As shown, the conventional automatic gain control circuit includes an input terminal 1, a detector 2, a divider 3 and an output terminal 4.

上記構成の自動利得制御回路において、交流信号が入力
端子1に加わると、その信号の一方は検波器2に加えら
れ、もう一方は除算器3の分母入力Aに加えられる。検
波器2に加えられた交流信号は、検波されて直流とな
り、除算器3の分子入力Bに加えられる。除算器3にお
いては分子入力Bと分母入力Aの除算B/A=Cの演算を
行ない出力Cを出力端子4に出力する。検波器2の検波
能率が100%の場合、除算器3の分母入力Aと分子入力
Bは常に等しいため、除算器3の入力レベルの大きさに
関係なく、除算器3の出力Cは一定となり自動利得制御
(AGC)回路として動作する。
In the automatic gain control circuit having the above configuration, when an AC signal is applied to the input terminal 1, one of the signals is applied to the detector 2 and the other is applied to the denominator input A of the divider 3. The alternating current signal applied to the detector 2 is detected to be a direct current, and is applied to the numerator input B of the divider 3. The divider 3 calculates the division B / A = C of the numerator input B and the denominator input A and outputs the output C to the output terminal 4. When the detection efficiency of the detector 2 is 100%, the denominator input A and the numerator input B of the divider 3 are always equal, so the output C of the divider 3 becomes constant regardless of the input level of the divider 3. Operates as an automatic gain control (AGC) circuit.

しかしながら上記自動利得制御回路において、周波数特
性が高域まで精度の良い除算器3は実際にはなく、高域
周波数まで使用可能な自動利得制御回路は得られてなか
った。
However, in the above-mentioned automatic gain control circuit, there is actually no divider 3 which is accurate in frequency characteristics up to high frequencies, and an automatic gain control circuit usable up to high frequencies has not been obtained.

第5図は上記問題を除去し、高域周波数においても使用
可能とする自動利得制御回路の構成例を示すブロック図
である。同図において、第4図と同一符号を付した部分
は同一又は相当部分を示す。以下他図面においても同様
とする。第5図において、5は乗算器、6は基準電圧発
生器である。
FIG. 5 is a block diagram showing a configuration example of an automatic gain control circuit which eliminates the above-mentioned problems and can be used even in a high frequency range. In the same figure, the parts given the same reference numerals as in FIG. 4 indicate the same or corresponding parts. The same applies to other drawings below. In FIG. 5, 5 is a multiplier and 6 is a reference voltage generator.

上記構成の自動利得制御回路において、基準電圧発生器
6の出力電圧を1Vとすると、除算器3の分母入力Aと除
算器3の出力Cは、1/A=Cとなり、除算器3において
分母入力Aの逆数を求めたことになる。
In the automatic gain control circuit with the above configuration, when the output voltage of the reference voltage generator 6 is 1V, the denominator input A of the divider 3 and the output C of the divider 3 are 1 / A = C, and the denominator of the divider 3 is This means that the reciprocal of the input A has been obtained.

乗算器5の入力Dは、入力端子1の信号と同じであり、
乗算器5の入力Cは入力端子1の信号の逆数を求めた直
流の値であるため、乗算器5の出力EはE=D・1/Aと
なる。除算器3の入力Aと乗算器5の入力Dとは交流と
直流の違いだけで値は同じであるため、乗算器5の出力
Eは入力端子1の信号レベルの大きさに関係なく一定の
レベルとなり、自動利得制御回路として動作する。ま
た、除算器3は直流電圧の演算であるため、周波数特性
が高域までのびている必要がなく、一方乗算器5の方は
高域まで周波数特性がのびているものが得られるため、
上記第4図に示す構成の自動利得制御回路のように高域
周波数領域でも精度が悪くなるという問題はない。
The input D of the multiplier 5 is the same as the signal at the input terminal 1,
Since the input C of the multiplier 5 is a DC value obtained by calculating the reciprocal of the signal at the input terminal 1, the output E of the multiplier 5 is E = D · 1 / A. Since the input A of the divider 3 and the input D of the multiplier 5 have the same value only in the difference between AC and DC, the output E of the multiplier 5 is constant regardless of the signal level of the input terminal 1. It becomes a level and operates as an automatic gain control circuit. Further, since the divider 3 is a DC voltage calculation, it is not necessary for the frequency characteristic to extend to a high range, while the multiplier 5 can obtain a frequency characteristic extending to a high range.
Unlike the automatic gain control circuit having the configuration shown in FIG. 4, there is no problem that the accuracy deteriorates even in the high frequency region.

〔発明が解決しようとする課題〕[Problems to be Solved by the Invention]

しかしながら、上記第5図に示す構成の自動利得制御回
路において、分母入力Aの電圧が小さいとき1/A=Cで
あるため、除算器3の出力Cが飽和する。この飽和電圧
は第6図の斜線部分に示すように定まった電圧ではな
い。なお、第6図は入力端子1の入力レベルと除算器3
の出力電圧との関係を示す図である。
However, in the automatic gain control circuit having the configuration shown in FIG. 5, 1 / A = C when the voltage of the denominator input A is small, so that the output C of the divider 3 is saturated. This saturation voltage is not a fixed voltage as shown by the shaded area in FIG. 6 shows the input level of the input terminal 1 and the divider 3
It is a figure which shows the relationship with the output voltage of.

このような状態で使用すると、第7図の斜線部分に示す
ように自動利得制御のかかり始めの電圧が一定でなくな
るとという欠点がある。なお、第7図は入力端子1の入
力レベルと出力端子4の出力レベルとの関係を示す図で
ある。
When used in such a state, there is a drawback that the voltage at the beginning of the automatic gain control is not constant as shown by the hatched portion in FIG. 7. FIG. 7 is a diagram showing the relationship between the input level of the input terminal 1 and the output level of the output terminal 4.

また、除算器3を飽和状態で使用することは該除算器3
を構成するICの特性及び性能等においても好ましくな
い。
Also, using the divider 3 in a saturated state means that the divider 3
It is also unfavorable in terms of the characteristics and performance of the ICs that compose the.

本発明は上述の点に鑑みて成されたもので、上記欠点を
除去し、高域周波数まで使用可能な精度の高い理想的な
自動利得制御回路を提供することにある。
The present invention has been made in view of the above points, and it is an object of the present invention to eliminate the above-mentioned drawbacks and provide an ideal automatic gain control circuit with high accuracy that can be used up to high frequencies.

〔課題を解決するための手段〕[Means for Solving the Problems]

上記課題を解決するため本発明は、第1図に示すよう
に、第5図に示す従来構成の自動利得制御回路の検波器
2の出力と除算器3の分母入力の間に第3図に示すよう
な回路構成の非線形回路7を挿入した。また、この非線
形回路7は後述するように入力端子71に入力される入力
電圧が基準電圧発生器75の基準電圧より小さい場合、出
力端子72の出力電圧が一定となる特性を有している。
In order to solve the above-mentioned problems, the present invention, as shown in FIG. 1, is provided between the output of the detector 2 and the denominator input of the divider 3 of the conventional automatic gain control circuit shown in FIG. A non-linear circuit 7 having a circuit configuration as shown is inserted. Further, this non-linear circuit 7 has a characteristic that the output voltage of the output terminal 72 becomes constant when the input voltage input to the input terminal 71 is smaller than the reference voltage of the reference voltage generator 75 as described later.

〔作用〕[Action]

上記の如く検波器2の出力と除算器3の分母入力の間に
非線形回路7を挿入することにより、利得制御のかかり
始めレベルは基準電圧発生器75の基準電圧となり、この
電圧は安定化させることが容易であるため、利得制御の
かかり始めレベルも安定化すると共に、入力信号が基準
電圧発生器75の基準電圧より小さい時においても除算器
3の分母入力Aには一定電圧が入力されるため、除算器
3の出力が飽和するような状態にならないから、高域周
波数まで使用可能で、且つ精度の高い理想的な自動利得
制御回路が実現できる。
By inserting the non-linear circuit 7 between the output of the detector 2 and the denominator input of the divider 3 as described above, the level at which gain control is started becomes the reference voltage of the reference voltage generator 75, and this voltage is stabilized. Since it is easy to perform gain control, the level at which gain control starts is stabilized, and a constant voltage is input to the denominator input A of the divider 3 even when the input signal is smaller than the reference voltage of the reference voltage generator 75. Therefore, since the output of the divider 3 does not saturate, it is possible to realize an ideal automatic gain control circuit that can be used up to a high frequency band and has high accuracy.

〔実施例〕〔Example〕

以下、本発明の実施例を図面に基づいて説明する。 Embodiments of the present invention will be described below with reference to the drawings.

第1図は本発明に係る自動利得制御回路の構成を示すブ
ロック図である。同図に示すように、検波器2の出力と
除算器3の分母入力Aとの間に非線形回路7が挿入され
ている。
FIG. 1 is a block diagram showing the configuration of an automatic gain control circuit according to the present invention. As shown in the figure, a nonlinear circuit 7 is inserted between the output of the detector 2 and the denominator input A of the divider 3.

第2図は上記自動利得制御回路の非線形回路7の入出力
特性を示す図であり、第3図はこの非線形回路7の回路
構成例を示す図である。
FIG. 2 is a diagram showing input / output characteristics of the non-linear circuit 7 of the automatic gain control circuit, and FIG. 3 is a diagram showing a circuit configuration example of the non-linear circuit 7.

第3図において、R1〜R6は抵抗器、D1,D2はダイオー
ド、71は入力端子、72は出力端子、73,74は演算増幅
器、75は基準電圧発生器である。また、基準電圧発生器
75の出力電圧を−0.1Vに設定し、抵抗器R1〜抵抗器R6
全て同じ値にする。
In FIG. 3, R 1 to R 6 are resistors, D 1 and D 2 are diodes, 71 is an input terminal, 72 is an output terminal, 73 and 74 are operational amplifiers, and 75 is a reference voltage generator. Also, the reference voltage generator
75 of the output voltage is set to -0.1 V, the resistors R 1 ~ resistor R 6 are all the same value.

基準電圧発生器75により、抵抗器R2及び抵抗器R5には電
流i1及び電流i2なる一定電流が流れている。また、i1
i2である。
Due to the reference voltage generator 75, constant currents i 1 and i 2 flow through the resistors R 2 and R 5 . Also, i 1 =
i 2

上記構成の非線形回路7において、入力端子71に、+0.
1Vの電圧が入力された場合、入力電圧による電流i1は抵
抗器R1から抵抗器R2を流れ、基準電圧発生器75に流れ込
むが、入力端子電圧と基準電圧発生器75の電圧が逆極性
で等しい値であるため抵抗器R1と抵抗器R2の結合点の電
圧は0Vとなり、演算増幅器73のマイナス入力点には電圧
が印加されず、演算増幅器73の出力電圧は0Vとなり、従
って抵抗器R4にも電流は流れない、抵抗器R5には電流i2
が流れているが、この電流は演算増幅器74の出力から抵
抗器R6を通って流れる。抵抗器R5=R6のため増幅器74の
出力電圧は基準電圧発生器75の電圧値と同じで極性のみ
反転した+0.1Vの電圧が出力されている。
In the non-linear circuit 7 having the above configuration, +0.
When the voltage of 1V is input, the current i 1 due to the input voltage flows from the resistor R 1 to the resistor R 2 and flows into the reference voltage generator 75, but the input terminal voltage and the voltage of the reference voltage generator 75 are reversed. Since the polarities are equal, the voltage at the connection point between the resistors R 1 and R 2 is 0V, no voltage is applied to the negative input point of the operational amplifier 73, and the output voltage of the operational amplifier 73 is 0V. Therefore, no current flows through the resistor R 4 , and the current i 2 flows through the resistor R 5.
, Which flows from the output of operational amplifier 74 through resistor R 6 . Since the resistor R 5 = R 6 , the output voltage of the amplifier 74 is the same as the voltage value of the reference voltage generator 75, and a voltage of +0.1 V in which only the polarity is inverted is output.

入力端子71の電圧値が+0.1Vよりも小さな値のときは、
抵抗器R1に流れる電流が抵抗器R2に流れる電流i1よりも
小さいため、電流i1の一部は演算増幅器73の出力からダ
イオードD1を通って抵抗器R2に流れることにより補充さ
れる。これにより演算増幅器73の出力電圧はプラスにな
り、ダイオードD2により阻止され、抵抗器R4には電流が
流れない。このことは、入力端子71に+0.1の電圧が加
わった時と同じであり、従って演算増幅器74の出力電圧
は+0.1のまま変化しない。
When the voltage value of input terminal 71 is less than + 0.1V,
Since the current flowing through the resistor R 1 is smaller than the current i 1 flowing through the resistor R 2, a portion of the current i 1 is replenished by flow through the diode D 1 from the output of the operational amplifier 73 to the resistor R 2 To be done. As a result, the output voltage of the operational amplifier 73 becomes positive and is blocked by the diode D 2 , and no current flows through the resistor R 4 . This is the same as when a voltage of +0.1 is applied to the input terminal 71, and therefore the output voltage of the operational amplifier 74 remains +0.1.

一方入力端子71に+0.1Vよりも大きな値の電圧が加わっ
た場合は、抵抗器R1に流れる電流の一部は抵抗器R2を流
れる電流i1となるが残りは抵抗器R3からダイオードD2
通り演算増幅器73の出力に流れ込む。抵抗器R3には、電
圧降下がおき、抵抗器R4との接続点はマイナスの電位と
なる。該電位に応じた電流は抵抗器R4を流れる。この電
流は演算増幅器74の出力から抵抗器R6を通って抵抗器R4
に供給される。抵抗器R6を流れる電流はこの他に抵抗器
R5を流れる電流i2がある。つまり抵抗器、R4を流れる電
流と抵抗器R5を流れる電流の加算されたものが抵抗器R6
を流れる。
On the other hand if the voltage of the large value is applied than + 0.1 V to the input terminal 71, the remaining a part becomes current i 1 flowing through the resistor R 2 of the current flowing through the resistor R 1 is a resistor R 3 It flows into the output of the operational amplifier 73 through the diode D 2 . The resistor R 3, every other drop, a connection point between the resistor R 4 becomes a negative potential. A current corresponding to the potential flows through the resistor R 4 . This current flows from the output of operational amplifier 74 through resistor R 6 to resistor R 4
Is supplied to. The current flowing through resistor R 6 is
There is a current i 2 flowing through R 5 . That is, the sum of the current flowing through the resistor R 4 and the current flowing through the resistor R 5 is the resistor R 6
Flowing through.

入力端子71に電圧が加わったことによる抵抗器R1の電流
から電流i1が引かれた値の電流が抵抗器R3と抵抗器R4
それぞれ流れるが、抵抗器R6にはこの引かれた値と同じ
電流が電流i2として加えられるため、抵抗器R1と抵抗器
R6に流れる電流の絶対値は等しくなり、入力端子71と出
力端子72の電圧は等しくなる。
Although the current of the current i 1 from the current of the resistor R 1 by the voltage applied to the input terminal 71 is pulled value flows respectively and resistor R 3 to the resistor R 4, the argument is the resistor R 6 Since the same current as the current value is added as the current i 2 , the resistor R 1 and the resistor
The absolute values of the currents flowing through R 6 become equal, and the voltages at the input terminal 71 and the output terminal 72 become equal.

以上説明したように、入力端子71の電圧が基準電圧発生
器75の基準電圧値以下の場合は、出力端子72の電圧は基
準電圧発生器75の電圧の極性が反転したと同じ値とな
り、入力端子71の電圧が基準電圧発生器75の電圧値以上
になると入力端子71と出力端子72の電圧が等しくなり、
非線形回路として作動する。
As described above, when the voltage at the input terminal 71 is less than or equal to the reference voltage value of the reference voltage generator 75, the voltage at the output terminal 72 becomes the same value as when the polarity of the voltage of the reference voltage generator 75 is inverted, When the voltage of the terminal 71 becomes more than the voltage value of the reference voltage generator 75, the voltage of the input terminal 71 becomes equal to the voltage of the output terminal 72,
Operates as a non-linear circuit.

上記第3図に示すような構成の回路を第1図の非線形回
路7として使用した場合の動作は、入力端子1の信号レ
ベルが小さい時は非線形回路7の出力電圧は一定な直流
電圧となる。この値が除算器3の分母入力Aに入り、除
算器3の出力Cは一定な値となり、乗算器5の入力Cに
入力される。そして入力端子1に入っている入力信号と
乗算されるがこの状態では入力端子1のレベルと出力端
子4のレベルは比例している。
When the circuit having the configuration shown in FIG. 3 is used as the non-linear circuit 7 of FIG. 1, the output voltage of the non-linear circuit 7 becomes a constant DC voltage when the signal level of the input terminal 1 is small. . This value enters the denominator input A of the divider 3, the output C of the divider 3 becomes a constant value, and is input to the input C of the multiplier 5. Then, the level of the input terminal 1 and the level of the output terminal 4 are proportional to each other in the state where they are multiplied by the input signal input to the input terminal 1.

入力信号レベルが第3図に示す構成の非線形回路7の基
準電圧発生器75の電圧値を越えると非線形回路7は線形
回路となるため、第5図の自動利得制御回路の動作と同
じになり、自動利得制御回路として動作する。
When the input signal level exceeds the voltage value of the reference voltage generator 75 of the non-linear circuit 7 having the configuration shown in FIG. 3, the non-linear circuit 7 becomes a linear circuit, and the operation is the same as that of the automatic gain control circuit in FIG. , Operates as an automatic gain control circuit.

以上、上記実施例においては、利得制御のかかり始めレ
ベルは第3図の基準電圧発生器75の発生電圧と同じであ
り、この電圧は安定化することが容易なため、利得制御
のかかり始めのレベルも安定したものが得られる。ま
た、第5図に示す自動利得制御回路とは異なり、入力信
号が小さい時において、乗算器3の分母入力Aには一定
な電圧が加わっているため、除算器3の出力が飽和する
ような状態にならないから、高域周波数まで使用可能な
精度の高い理想的な自動利得制御回路となる。
As described above, in the above embodiment, the level at which the gain control is started is the same as the voltage generated by the reference voltage generator 75 in FIG. 3, and this voltage is easy to stabilize. You can get a stable level. Further, unlike the automatic gain control circuit shown in FIG. 5, when the input signal is small, a constant voltage is applied to the denominator input A of the multiplier 3, so that the output of the divider 3 is saturated. Since it is not in a state, it becomes an ideal automatic gain control circuit with high accuracy that can be used up to high frequencies.

〔発明の効果〕〔The invention's effect〕

以上説明したように本発明によれば、下記のような優れ
た効果が得られる。
As described above, according to the present invention, the following excellent effects can be obtained.

即ち、検波器の出力と除算器の分母入力の間に入力信号
レベルが所定値以下の時は一定の出力レベルとなる非線
形回路を挿入するので、利得制御が該所定値からかかり
始めることになり、この所定値を安定化させることが容
易であるから利得制御のかかり始めレベルが安定すると
共に、入力信号が前記所定値より小さい時においても除
算器の分母入力には一定電圧が加わっているため除算器
の出力が飽和するような状態にならない。従って、高域
周波数まで使用可能で、且つ精度の高い理想的な自動利
得制御回路が実現できる。
That is, since a non-linear circuit is inserted between the output of the detector and the denominator input of the divider to maintain a constant output level when the input signal level is less than or equal to a predetermined value, the gain control will start from that predetermined value. Since it is easy to stabilize this predetermined value, the level at which gain control starts is stable, and a constant voltage is applied to the denominator input of the divider even when the input signal is smaller than the predetermined value. The output of the divider does not saturate. Therefore, it is possible to realize an ideal automatic gain control circuit that can be used up to a high frequency and has high accuracy.

【図面の簡単な説明】[Brief description of drawings]

第1図は本発明に係る自動利得制御回路の構成を示すブ
ロック図、第2図は非線形回路の入出力特性を示す図、
第3図はこの非線形回路の回路構成例を示す図、第4図
は従来の自動利得制御回路の構成を示すブロック図、第
5図は従来の高域周波数においても使用可能な自動利得
制御回路の構成例を示すブロック図、第6図は第5図の
除算器の入力端子レベルと出力電圧との関係を示す図、
第7図は第5図の自動利得制御回路の入力レベルと出力
レベルとの関係を示す図である。 図中、1……入力端子、2……検波器、3……除算器、
4……出力端子、5……乗算器、6……基準電圧発生
器、7……非線形回路。
FIG. 1 is a block diagram showing the configuration of an automatic gain control circuit according to the present invention, and FIG. 2 is a diagram showing input / output characteristics of a non-linear circuit,
FIG. 3 is a diagram showing a circuit configuration example of this non-linear circuit, FIG. 4 is a block diagram showing a configuration of a conventional automatic gain control circuit, and FIG. 5 is a conventional automatic gain control circuit usable even at a high frequency. Is a block diagram showing an example of the configuration of FIG. 6, FIG. 6 is a diagram showing the relationship between the input terminal level and the output voltage of the divider of FIG.
FIG. 7 is a diagram showing the relationship between the input level and the output level of the automatic gain control circuit of FIG. In the figure, 1 ... input terminal, 2 ... detector, 3 ... divider,
4 ... Output terminal, 5 ... Multiplier, 6 ... Reference voltage generator, 7 ... Non-linear circuit.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】検波器、基準電圧発生器、除算器及び乗算
器を具備し、入力端子を前記乗算器の一方の入力に接続
すると共に前記検波器の入力に接続し、前記除算器の分
母入力に該検波器の出力を入力すると共に分子入力に前
記基準電圧発生器の出力を入力し、該除算器の出力を前
記乗算器の他方の入力に接続し、該乗算器の出力を出力
端子に接続した構成の自動利得制御回路において、前記
検波器の出力と前記除算器の分母入力の間に入力信号レ
ベルが所定値以下の時は一定の出力レベルとなる非線形
回路を挿入したことを特徴とする自動利得制御回路。
1. A denominator of the divider comprising a detector, a reference voltage generator, a divider and a multiplier, the input terminal of which is connected to one input of the multiplier and the input of the detector. The output of the detector is input to the input, the output of the reference voltage generator is input to the numerator input, the output of the divider is connected to the other input of the multiplier, and the output of the multiplier is output terminal. In the automatic gain control circuit of the configuration connected to, a non-linear circuit is inserted between the output of the detector and the denominator input of the divider when the input signal level is equal to or lower than a predetermined value. And automatic gain control circuit.
JP4254688A 1988-02-24 1988-02-24 Automatic gain control circuit Expired - Lifetime JPH0691397B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4254688A JPH0691397B2 (en) 1988-02-24 1988-02-24 Automatic gain control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4254688A JPH0691397B2 (en) 1988-02-24 1988-02-24 Automatic gain control circuit

Publications (2)

Publication Number Publication Date
JPH01216610A JPH01216610A (en) 1989-08-30
JPH0691397B2 true JPH0691397B2 (en) 1994-11-14

Family

ID=12639055

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4254688A Expired - Lifetime JPH0691397B2 (en) 1988-02-24 1988-02-24 Automatic gain control circuit

Country Status (1)

Country Link
JP (1) JPH0691397B2 (en)

Also Published As

Publication number Publication date
JPH01216610A (en) 1989-08-30

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