JPH0691233B2 - Method for manufacturing semiconductor light receiving element - Google Patents
Method for manufacturing semiconductor light receiving elementInfo
- Publication number
- JPH0691233B2 JPH0691233B2 JP59254156A JP25415684A JPH0691233B2 JP H0691233 B2 JPH0691233 B2 JP H0691233B2 JP 59254156 A JP59254156 A JP 59254156A JP 25415684 A JP25415684 A JP 25415684A JP H0691233 B2 JPH0691233 B2 JP H0691233B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- separation groove
- forming
- receiving element
- light receiving
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims description 48
- 238000000034 method Methods 0.000 title claims description 18
- 238000004519 manufacturing process Methods 0.000 title claims 7
- 238000000926 separation method Methods 0.000 claims description 36
- 239000012535 impurity Substances 0.000 claims description 23
- 239000000758 substrate Substances 0.000 claims description 19
- 238000009792 diffusion process Methods 0.000 claims description 12
- 239000000969 carrier Substances 0.000 claims description 9
- 239000013078 crystal Substances 0.000 claims description 7
- 230000007547 defect Effects 0.000 claims description 7
- 230000035515 penetration Effects 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 150000002500 ions Chemical class 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims 2
- 230000001590 oxidative effect Effects 0.000 claims 2
- 238000002955 isolation Methods 0.000 description 13
- 230000010354 integration Effects 0.000 description 12
- 230000003287 optical effect Effects 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 238000003384 imaging method Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 230000031700 light absorption Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 238000009751 slip forming Methods 0.000 description 2
- 229910052786 argon Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14643—Photodiode arrays; MOS imagers
- H01L27/14654—Blooming suppression
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Electromagnetism (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Solid State Image Pick-Up Elements (AREA)
- Element Separation (AREA)
- Light Receiving Elements (AREA)
Description
【発明の詳細な説明】 ［発明の技術分野］ 本発明は、光検出素子を含む複数または多数の素子を半
導体基板（ウエハ）上に集積化する際、各素子を電気的
に分離する方法で、特にＵ字型溝切りおよび溝充填法を
用いる分離帯形成方法に関するものである。Description: TECHNICAL FIELD OF THE INVENTION The present invention provides a method of electrically separating each element when a plurality of or a large number of elements including a photodetection element are integrated on a semiconductor substrate (wafer). In particular, the present invention relates to a method for forming a separator using a U-shaped groove cutting and groove filling method.
［先行技術の説明］ 従来、PN接合などから成る光電変換部を有する光検出素
子を含む半導体装置、例えば、半導体撮像装置では、各
光検出素子つまり各画素間の光により生成される電荷
（キャリア）の分離を良くし、解像度特性を向上させる
ため、接合分離法を用いていた。第７図に示す例では、
PIN構造を有する光電変換部から成る画素1,1′、光電変
換により電荷を発生させる主たる領域２、基板３、およ
び、分離領域４より構成される光半導体装置を示す。こ
こで、画素１および１′の間の分離特性を良くするため
には、即ち、１に貯えられた電荷が１′に移らないため
には、分離領域の横幅を大きくとることや、不純物濃度
を高くすることにより、４に入りこんでくる電荷を再結
合させて消滅させてしまうことが必要である。[Description of Prior Art] Conventionally, in a semiconductor device including a photo-detecting element having a photoelectric conversion unit formed of a PN junction or the like, for example, in a semiconductor imaging device, in each photo-detecting element, that is, charge (carrier ) Was improved and the resolution characteristics were improved, the junction separation method was used. In the example shown in FIG.
1 shows an optical semiconductor device composed of pixels 1, 1 ′ composed of a photoelectric conversion part having a PIN structure, a main region 2 for generating charges by photoelectric conversion, a substrate 3, and an isolation region 4. Here, in order to improve the isolation characteristic between the pixels 1 and 1 ', that is, in order that the charge stored in 1 does not move to 1', the width of the isolation region is increased and the impurity concentration is increased. It is necessary to recombine the charges that enter 4 and eliminate them by increasing the value of.
しかし、この方法では、例えば分離領域の不純物濃度を
約1020cm-3以上に大きくし、かつ、集積化のため画素部
（P+シリコン）と分離領域（N+シリコン）との距離を小
さくとった場合、両者が重なったり微小な結晶欠陥の影
響を受けやすくなり、接合リーク電流の増加や耐圧の低
下を招き特性や歩留りを悪くする。一方逆に、耐圧やリ
ークを軽減するため分離部の不純物濃度を1017〜1018cm
-3程度に下げた場合、光キャリアを隣接する画素に移る
前に再結合させるために分離帯の幅を極めて大きくとる
必要があり、集積化が困難であった。However, in this method, for example, the impurity concentration of the isolation region is increased to about 10 20 cm -3 or more, and the distance between the pixel portion (P + silicon) and the isolation region (N + silicon) is reduced for integration. If they are taken, they are easily overlapped with each other and are susceptible to minute crystal defects, which leads to an increase in junction leak current and a decrease in withstand voltage, which deteriorates the characteristics and yield. On the other hand, on the contrary, in order to reduce the breakdown voltage and leakage, the impurity concentration of the isolation part is 10 17 to 10 18 cm.
When it is lowered to about -3, the width of the separation band needs to be extremely large in order to recombine the photocarriers before moving to the adjacent pixel, which makes integration difficult.
従って、従来はある程度集積化した素子においては、こ
の画素間のストローク即ち隣接画素への信号電荷のもれ
が約10％程度にも達する不具合があった。Therefore, conventionally, in a device having a certain degree of integration, there is a problem that the stroke between the pixels, that is, the leakage of the signal charge to the adjacent pixel reaches about 10%.
［発明の目的］ 本発明は、上記従来技術の欠点を克服し、半導体撮像装
置などの光検出素子を含む複数の素子を半導体基板上に
形成した半導体装置において、素子間分離特性を格段に
向上させ、しかも高集積化が可能な素子分離帯を形成す
る方法を提供することを目的とする。[Object of the Invention] The present invention overcomes the above-mentioned drawbacks of the prior art, and in a semiconductor device in which a plurality of elements including a photodetection element are formed on a semiconductor substrate, such as a semiconductor imaging device, the isolation characteristics between elements are significantly improved. It is an object of the present invention to provide a method for forming an element isolation band that allows high integration.
［発明の概要］ 本発明の第１の特徴は、所望の分離個所に１〜３μｍ幅
のＵ字型溝切りおよび充填法により分離帯を形成する
際、溝切りの深さを、入射光の波長で決まる侵入深さお
よび溝切り部底部付近のキャリアの拡散長に応じて変え
ることにより、光入射により過剰に発生したキャリアを
当該素子以外の部分に拡散する前に再結合により消し去
ることにより、素子間の分離特性を向上させるものであ
る。[Summary of the Invention] A first feature of the present invention is that when a separation band is formed at a desired separation position by a U-shaped groove having a width of 1 to 3 μm and a filling method, the depth of the groove is determined by the incident light. By changing according to the penetration depth determined by the wavelength and the diffusion length of carriers near the bottom of the grooved part, carriers generated excessively by light incidence can be eliminated by recombination before diffusing to other parts. , To improve the isolation characteristics between elements.
本発明の第２の特徴は、溝切り部底部に更に高濃度に不
純物を添加してやり、キャリアの拡散長をより短かくす
ることにより、その効果を一層高めることにある。The second feature of the present invention is to further increase the effect by adding impurities at a higher concentration to the bottom of the grooved portion to further shorten the carrier diffusion length.
本発明の第３の特徴は、溝切り部底部に更にアルゴン，
酸素，窒素などのイオンを打込んでやり、結晶欠陥をつ
くることによりキャリアの拡散長をより短かくすること
で、その効果を一層高めようとするものである。The third feature of the present invention is that the bottom of the groove is further filled with argon,
By implanting ions such as oxygen and nitrogen to create crystal defects, the diffusion length of carriers is further shortened to further enhance the effect.
本発明の第４の特徴は、素子領域を連続的に形成後に、
分離帯を形成することにより、マスク合せ部分をなくす
ことで、集積度を一層高めようとするものである。A fourth characteristic of the present invention is that after the element regions are continuously formed,
By forming the separation band, the mask matching portion is eliminated to further increase the integration degree.
本発明の第５の特徴は、フォトダイオードまたはイメー
ジセンサ用受光素子の分離に適用することにより高集積
度，高分離特性の光半導体装置を得るようにするもので
ある。A fifth feature of the present invention is to obtain an optical semiconductor device having a high degree of integration and a high isolation characteristic by applying to the isolation of a photodiode or a light receiving element for an image sensor.
［発明の実施例］ 本発明の一実施例に係るＵ字形型分離帯の形成方法をPI
Nフォトダイオードを含む半導体装置に適用した例につ
き、第１図（Ａ）〜（Ｅ）の工程図を参照して説明す
る。[Embodiment of the Invention] A method for forming a U-shaped separator according to an embodiment of the present invention will be described with reference to FIG.
An example applied to a semiconductor device including an N photodiode will be described with reference to the process diagrams of FIGS. 1 (A) to 1 (E).
（Ａ） N+シリコン基板11にN-層12をエピタキシャル成
長により設ける。(A) to the N + silicon substrate 11 N - layer 12 is provided by epitaxial growth.
（Ｂ） CVDSiO2膜を形成し、フォトエッチングにより
１〜３μｍ幅に溝切り用マスクを形成し、CCl4やCCl2F2
ガスを用いた反応性イオンエッチングにより、溝切り部
13を所望の深さまでエッチングする。このときの溝の深
さは、後述するように光キャリアの拡散長と、入射光の
波長に関係する光の侵入距離とに応じて決定する。一
方、溝幅は、集積度や加工精度を考慮して上記のように
１〜３μｍ幅に形成する。このときの溝幅はエッチング
の異方性により全域にわたりマスクとほぼ同寸法に垂直
に形成することができる。また、必要に応じて溝切り部
13の底部にはN+型不純物（As,P,sb等）をイオン注入に
より添加して底部付近の不純物濃度を高くしたり、ある
いは、Ar+,O+,N+などをイオン注入して結晶欠陥14を故
意に形成する。(B) A CVDSiO 2 film is formed, and a grooving mask is formed with a width of 1 to 3 μm by photoetching. CCl 4 or CCl 2 F 2
Groove cut by reactive ion etching using gas
Etch 13 to desired depth. The depth of the groove at this time is determined according to the diffusion length of the optical carrier and the light penetration distance related to the wavelength of the incident light as described later. On the other hand, the groove width is formed to have a width of 1 to 3 μm as described above in consideration of the degree of integration and processing accuracy. At this time, the groove width can be formed perpendicular to the same dimension as the mask over the entire area due to etching anisotropy. Also, if necessary, groove
N + -type impurities (As, P, sb, etc.) are added to the bottom of 13 by ion implantation to increase the impurity concentration near the bottom, or Ar + , O + , N + etc. are ion-implanted. Crystal defects 14 are formed intentionally.
（Ｃ） 洗浄，熱酸化し表面にSiO2膜15を付けた後に、
LPCVDなどによりポリシリコン16にて充填した後、表面
についたポリシリコンのCF4ガスを用いてプラズマエッ
チングにより除去する。(C) After cleaning and thermal oxidation and applying the SiO 2 film 15 on the surface,
After being filled with polysilicon 16 by LPCVD or the like, it is removed by plasma etching using CF 4 gas of polysilicon attached to the surface.
（ｄ） 表面を再び熱酸化し、P+領域形成用のフォトエ
ッチングを行ない、B+のイオン注入，ドライブイン酸化
し、P+領域17を形成する。(D) The surface is again thermally oxidized, photo-etching for P + region formation is performed, and B + ion implantation and drive-in oxidation are performed to form a P + region 17.
（Ｅ） 所要のコンタクトホールを形成し、Al等により
配線18を形成する。裏面電極19もAu等により形成する。(E) A required contact hole is formed, and the wiring 18 is formed of Al or the like. The back electrode 19 is also formed of Au or the like.
PIN構造の光検出部を有するフォトダイオードアレイ
に、上記の如きＵ字型分離帯を形成することにより、第
７図に示した従来構造に比べて集積度および素子分離特
性が格段に優れたフォトダイオードアレイが得られる。By forming the U-shaped separation band as described above in the photodiode array having the photodetection section of the PIN structure, a photodiode having a much higher degree of integration and element separation characteristics than the conventional structure shown in FIG. 7 is obtained. A diode array is obtained.
即ち、第７図に示した従来構造の場合、クロストクやブ
ルーミングを防止するには、P+領域から漏れ出す光キャ
リアが隣接する画素間に移動する間に消滅させる必要が
あり、キャリアのN+領域中の行程をキャリアの拡散長ａ
以上にする必要がある。従って、この場合の分離幅は、
N+の横方向拡散により、N-層の長さをｉとして約2i＋ａ
となる。That is, in the case of the conventional construction shown in FIG. 7, to prevent Kurosutoku and blooming, it is necessary to extinguish while the optical carrier leaking from P + region moves between adjacent pixels, the carrier N + Carrier diffusion length a
It is necessary to be above. Therefore, the separation width in this case is
Due to the lateral diffusion of N +, the length of the N − layer is about 2i + a
Becomes
これに対して、本発明によるＵ字型分離帯の場合は、第
２図の要部断面図で示す如く、キャリアは溝の下部を通
って隣接画素に流れ込むので、拡散流ａ＝2b＋ｃを満足
するように溝幅および溝の深さを決めれば良く、溝をあ
る程度深くすることにより溝幅即ち分離幅は１〜３μｍ
と極めて狭くすることができる。On the other hand, in the case of the U-shaped separator according to the present invention, as shown in the cross-sectional view of the main part of FIG. 2, the carriers flow into the adjacent pixels through the lower part of the groove, so that the diffusion flow a = 2b + c is satisfied. The groove width and the groove depth may be determined so that the groove width, that is, the separation width is 1 to 3 μm.
And can be extremely narrow.
ところで入射光が赤外線などのような長波長成分を含む
場合、直接N+層11まで侵入してキャリア20を発生する。
この場合、上述の場合に比べて相対的にキャリアの行程
が短かくなる。一方、Siの光吸収係数αについてはGrov
e著の“Physics and Technolagy of Semiconductor
Devices"（Nuw Youk;Wiley 1967年）によると、第
３図のようになり、光の侵入距離ｌを1/αにとると、例
えば、0.8μｍの近赤外光ではｌ÷10μｍとなる。従っ
て、この場合はａ＝ｂ＋（ｉ＋ｂ−ｌ）＋ｃを満足する
ように溝幅および溝深さを決めれば良く、溝の深さは上
述の場合よりも多少深くする必要はあるが、このような
場合を考慮しても溝幅即ち分離幅は１〜２μｍとするこ
とは可能である。By the way, when the incident light contains a long wavelength component such as infrared rays, it directly penetrates into the N + layer 11 to generate the carriers 20.
In this case, the carrier travel becomes relatively shorter than that in the above case. On the other hand, regarding the light absorption coefficient α of Si, Grov
"Physics and Technolagy of Semiconductor" by e
According to Devices "(Nuw Youk; Wiley 1967), the result is as shown in FIG. 3, and if the light penetration distance l is 1 / α, for example, 0.8 μm near-infrared light is 1/10 μm. Therefore, in this case, the groove width and the groove depth may be determined so as to satisfy a = b + (i + b-1) + c, and the groove depth needs to be slightly deeper than the above case. Even in such a case, the groove width, that is, the separation width can be set to 1 to 2 μm.
一方、上記溝の深さをあまり深くすることができない場
合は前述したように溝切り部13の底部に高濃度不純物領
域を形成したり、あるいは、結晶欠陥を故意に作り、こ
の部分のみキャリアの拡散長を小さくすることにより、
キャリアの消滅を効果的に行ない分離特性をより良くす
ることも可能である。On the other hand, when the depth of the groove cannot be made too deep, a high-concentration impurity region is formed at the bottom of the grooved portion 13 as described above, or a crystal defect is intentionally created, and only this portion of the carrier By reducing the diffusion length,
It is also possible to effectively eliminate the carriers and improve the separation characteristics.
このようにして、Ｕ字型分離帯を形成することにより本
実施例の場合には、従来構造に比べて、N-層12の圧さを
如何によらず、十分集積度良く分離帯を形成することが
できるようになる。By thus forming the U-shaped separator, in the case of the present embodiment, the separator is formed with a sufficient degree of integration as compared with the conventional structure, regardless of the pressure of the N − layer 12. You will be able to.
一例として、光検出部の画素寸法37×37μｍ、基板不純
物濃度１×1018cm-3、N-層厚さ５μｍの場合で、溝切り
寸法として幅２μｍ、深さ10μｍとなるように分離帯を
形成し、各画素間のクロストークを測定した結果、クロ
ストークは0.1％以下であり、従来の約10％に比べ、100
分の１以下に減少し、極めて良い分離特性が得られた。As an example, in the case where the pixel size of the photodetector is 37 × 37 μm, the substrate impurity concentration is 1 × 10 18 cm -3 , and the N - layer thickness is 5 μm, the width of the groove is 2 μm and the separation band is 10 μm. As a result, the crosstalk between each pixel was measured, and as a result, the crosstalk was 0.1% or less, which was 100% compared to the conventional 10%.
It was reduced to less than one-third, and extremely good separation characteristics were obtained.
尚、分離帯の形成は上記実施例のみに限られることな
く、例えば第４図に示すように、Ｐ型基板21にN+埋込層
を形成した上にN-エピタキシャル層を形成した構造にも
適用することができ、入射光波長，キャリアの拡散長に
よっては、溝切り深さをN+埋込層を貫通し、Ｐ型基板中
まで入ることもあり得ることは勿論である。Incidentally, the formation of the separation band is not limited to the above-mentioned embodiment, and for example, as shown in FIG. 4, a structure in which the N + buried layer is formed on the P type substrate 21 and the N − epitaxial layer is formed is also used. Of course, depending on the wavelength of incident light and the diffusion length of carriers, the groove cutting depth may penetrate the N + buried layer and reach the P-type substrate.
また、上記の例ではP+N-N+構造およびP+N-N+P構造につ
いてのみ述べたが、第５図（Ａ），（Ｂ）のように、P+
N構造およびP+NP構造構造についてもP+N接合にできる空
乏層22を上記例のN-に置き換えてやれば全く同様に入射
光の侵入深さ、および、キャリアの拡散長に応じて溝切
りの深さを決めることができる。以上の例を各々導電型
を逆にした場合、更にはシリコン以外の他の半導体の場
合にも本発明は適用できることは明白である。Further, in the above example P + N - N + structure and P + N - mentioned only the N + P structure, FIG. 5 (A), as (B), P +
Even for the N structure and the P + NP structure, if the depletion layer 22 that can be a P + N junction is replaced with N − in the above example, the groove will be exactly the same depending on the penetration depth of incident light and the diffusion length of carriers. You can decide the cutting depth. It is obvious that the present invention can be applied to the cases in which the conductivity types are reversed, and further to semiconductors other than silicon.
更に付け加えるに、P+領域と分離領域は必ずしも離れて
形成する必要はなく、集積度を更に上げるためには第６
図のようにP+領域を連続的に形成してから分離帯を形成
すれば、マスク合せに必要な寸法だけ、縮小できるので
更に集積度を上げることができる。In addition, it is not always necessary to form the P + region and the isolation region separately, and in order to further increase the integration degree, the sixth
As shown in the figure, if the P + region is continuously formed and then the separation band is formed, the size can be reduced by a dimension required for mask alignment, so that the degree of integration can be further increased.
［発明の効果］ 以上のように本発明によれば、極めて集積度が高く、か
つ、分離特性（低クロストーク，耐ブルーミング性）に
優れた半導体装置が得られる。また、本発明を検出部お
よび増幅回路，スイッチ回路等を同一基板上に含む光信
号処理用IC等低クロストーク性の要求される半導体装置
に適用すれば、その性能向上に極めて大きく寄与するこ
とができる。[Advantages of the Invention] As described above, according to the present invention, a semiconductor device having an extremely high degree of integration and excellent isolation characteristics (low crosstalk and blooming resistance) can be obtained. Further, if the present invention is applied to a semiconductor device requiring low crosstalk such as an optical signal processing IC including a detection unit, an amplifier circuit, a switch circuit and the like on the same substrate, it can greatly contribute to the performance improvement. You can
第１図（Ａ）〜（Ｅ）は本発明の一実施例に係るＵ字型
分離帯形成方法を説明するための工程図、第２図は第１
図により形成されたＵ分離帯の作用効果を説明するため
の半導体装置の要部概念図、第３図は波長と光吸収係数
との関係図、第４図、第５図（Ａ），（Ｂ）、第６図
は、それぞれ本発明の他の実施例を示すＵ字型分離帯の
形成された半導体装置の要部概念図、第７図は従来の分
離帯構造を有する半導体装置の要部概念図である。 1,1′……画素、２……領域、３……基板、４……分離
領域、11……N-シリコン基板、12……N-層、13……溝切
り部、14……結晶欠陥、15……SiO2膜、16……ポリシリ
コン、17……P+領域、18……配線、19……裏面電極、20
……キャリア、21……N+基板、22……空乏層。1 (A) to 1 (E) are process drawings for explaining a U-shaped separator forming method according to an embodiment of the present invention, and FIG.
FIG. 3 is a conceptual diagram of a main part of a semiconductor device for explaining the function and effect of a U separation band formed by the figure, FIG. 3 is a relationship diagram between wavelength and light absorption coefficient, FIG. 4, FIG. 5 (A), ( B) and FIG. 6 are conceptual views of a semiconductor device in which a U-shaped separator is formed according to another embodiment of the present invention, and FIG. 7 is a schematic view of a semiconductor device having a conventional separator structure. FIG. 1,1 '... Pixel, 2 ... Region, 3 ... Substrate, 4 ... Separation region, 11 ... N - silicon substrate, 12 ... N - layer, 13 ... Groove, 14 ... Crystal Defects, 15 …… SiO 2 film, 16 …… Polysilicon, 17 …… P + region, 18 …… Wiring, 19 …… Backside electrode, 20
…… Carrier, 21 …… N + substrate, 22 …… Depletion layer.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 イシユトヴアン・バールシヨニ 静岡県浜松市篠ヶ瀬町586番地 (56)参考文献 特開 昭58−82532（ＪＰ，Ａ) 特開 昭59−188966（ＪＰ，Ａ) 特公 昭48−37232（ＪＰ，Ｂ１) ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Ishiyuttovan Burshiyoni 586 Shinogase Town, Hamamatsu City, Shizuoka Prefecture (56) References JP-A-58-82532 (JP, A) JP-A-59-188966 (JP, JP, 188966) A) Japanese Patent Publication Sho 48-37232 (JP, B1)
Claims (6)
体層を表面に有する半導体基板上に、第１導電型低不純
物密度の半導体層を形成する工程と、 前記低不純物密度の半導体層を島状に分離すべく、入射
光によって形成される光キャリアの拡散長をａとしたと
き、 ａ＝2b＋ｃ なる関係を満足するように、前記低不純物密度の半導体
層の表面から前記低不純物密度の半導体層を貫通し、か
つ、所望の分離個所の前記半導体基板に、深さｂ、幅ｃ
の分離溝を形成する工程と、 前記低不純物密度の半導体層の表面ならびに前記分離溝
の表面を熱酸化する工程と、 前記分離溝を溝充填法により充填する工程と、 前記低不純物密度の半導体層上部に第２導電型の半導体
領域を形成して受光素子となす工程と、 前記半導体領域に対する所望のコンタクトホールを形成
して金属配線を形成する工程とを有することを特徴とす
る半導体受光素子の製造方法。1. A step of forming a semiconductor layer having a first conductivity type and a low impurity density on a semiconductor substrate having at least a semiconductor layer having a first conductivity type and a high impurity density on a surface thereof; In order to separate the light carriers from the surface of the low impurity density semiconductor layer so that the diffusion length of photocarriers formed by the incident light is a, the relationship of a = 2b + c is satisfied. A layer having a depth b and a width c in the semiconductor substrate passing through the layer and at a desired separation position.
Forming a separation groove, a step of thermally oxidizing the surface of the low-impurity-density semiconductor layer and the surface of the separation groove, a step of filling the separation groove by a groove filling method, and a semiconductor having a low impurity density A semiconductor light receiving element comprising: a step of forming a second conductivity type semiconductor region on the upper part of the layer to form a light receiving element; and a step of forming a desired contact hole for the semiconductor region and forming a metal wiring. Manufacturing method.
み選択的に前記分離溝底部の半導体基板と同導電型の不
純物を添加する工程を有することを特徴とする特許請求
の範囲第１項記載の半導体受光素子の製造方法。2. The method according to claim 1, further comprising a step of selectively adding an impurity having the same conductivity type as that of the semiconductor substrate at the bottom of the separation groove to only the bottom of the separation groove after forming the separation groove. 2. A method for manufacturing a semiconductor light receiving element according to item 1.
み選択的にイオンを打ち込んで、前記分離溝底部の半導
体基板にのみ結晶欠陥を誘起させる工程を有することを
特徴とする特許請求の範囲第１項記載の半導体受光素子
の製造方法。3. After the formation of the separation groove, there is a step of selectively implanting ions only in the bottom of the separation groove to induce crystal defects only in the semiconductor substrate at the bottom of the separation groove. 2. A method of manufacturing a semiconductor light receiving element according to claim 1.
体層を表面に有する半導体基板上に第１導電型低不純物
密度の半導体層を形成する工程と、 前記低不純物密度の半導体層を島状に分離すべく、前記
低不純物密度の半導体層の厚さをｉ、入射光の波長によ
って決まる光の進入距離を１、入射光によって形成され
る光キャリアの拡散長をａとしたとき、 ａ＝ｂ＋（ｉ＋ｂ−１）＋ｃ なる関係を満足するように、前記低不純物密度の半導体
層の表面から前記低不純物密度の半導体層を貫通し、か
つ、所望の分離個所の前記半導体基板に、深さｂ、幅ｃ
の分離溝を形成する工程と、 前記低不純物密度の半導体層の表面ならびに前記分離溝
の表面を熱酸化する工程と、 前記分離溝を溝充填法により充填する工程と、 前記低不純物密度の半導体層上部に第２導電型の半導体
領域を形成して受光素子となす工程と、 前記半導体領域に対する所望のコンタクトホールを形成
して金属配線を形成する工程とを有することを特徴とす
る半導体受光素子の製造方法。4. A step of forming a semiconductor layer having a first conductivity type and a low impurity density on a semiconductor substrate having at least a semiconductor layer having a first conductivity type and a high impurity density on a surface thereof, and the semiconductor layer having the low impurity density is island-shaped. In order to separate into the following, when the thickness of the low impurity density semiconductor layer is i, the light penetration distance determined by the wavelength of the incident light is 1, and the diffusion length of the photocarrier formed by the incident light is a, a = b + (i + b-1) + c so that the surface of the low-impurity-density semiconductor layer penetrates the low-impurity-density semiconductor layer and a desired depth of the semiconductor substrate has a depth. b, width c
Forming a separation groove, a step of thermally oxidizing the surface of the low-impurity-density semiconductor layer and the surface of the separation groove, a step of filling the separation groove by a groove filling method, and a semiconductor having a low impurity density A semiconductor light receiving element comprising: a step of forming a second conductivity type semiconductor region on the upper part of the layer to form a light receiving element; and a step of forming a desired contact hole for the semiconductor region and forming a metal wiring. Manufacturing method.
択的に前記分離溝底部の半導体基板と同導電型の不純物
を添加する工程を有することを特徴とする特許請求の範
囲第４項記載の半導体受光素子の製造方法。5. The method according to claim 4, further comprising a step of selectively adding an impurity having the same conductivity type as that of the semiconductor substrate at the bottom of the separation groove to only the bottom of the separation groove after forming the separation groove. A method for manufacturing a semiconductor light receiving element according to the item 1.
択的にイオンを打ち込んで、前記分離溝底部の半導体基
板にのみ結晶欠陥を誘起させる工程を有することを特徴
とする特許請求の範囲第４項記載の半導体受光素子の製
造方法。6. The method according to claim 6, further comprising the step of selectively implanting ions only at the bottom of the separation groove after the formation of the separation groove to induce crystal defects only in the semiconductor substrate at the bottom of the separation groove. A method of manufacturing a semiconductor light receiving element according to claim 4.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59254156A JPH0691233B2 (en) | 1984-12-03 | 1984-12-03 | Method for manufacturing semiconductor light receiving element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59254156A JPH0691233B2 (en) | 1984-12-03 | 1984-12-03 | Method for manufacturing semiconductor light receiving element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61133659A JPS61133659A (en) | 1986-06-20 |
| JPH0691233B2 true JPH0691233B2 (en) | 1994-11-14 |
Family
ID=17261000
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59254156A Expired - Fee Related JPH0691233B2 (en) | 1984-12-03 | 1984-12-03 | Method for manufacturing semiconductor light receiving element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0691233B2 (en) |
Families Citing this family (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6133615A (en) * | 1998-04-13 | 2000-10-17 | Wisconsin Alumni Research Foundation | Photodiode arrays having minimized cross-talk between diodes |
| JP2003004855A (en) * | 2001-06-26 | 2003-01-08 | Hamamatsu Photonics Kk | Radiation detector |
| JP4707885B2 (en) * | 2001-06-26 | 2011-06-22 | 浜松ホトニクス株式会社 | Photodetector |
| JP4482253B2 (en) * | 2001-09-12 | 2010-06-16 | 浜松ホトニクス株式会社 | Photodiode array, solid-state imaging device, and radiation detector |
| JP4394904B2 (en) * | 2003-06-23 | 2010-01-06 | 浜松ホトニクス株式会社 | Manufacturing method of photodiode array |
| US7960202B2 (en) | 2006-01-18 | 2011-06-14 | Hamamatsu Photonics K.K. | Photodiode array having semiconductor substrate and crystal fused regions and method for making thereof |
| US7528458B2 (en) * | 2006-03-02 | 2009-05-05 | Icemos Technology Ltd. | Photodiode having increased proportion of light-sensitive area to light-insensitive area |
| JP2010500766A (en) * | 2006-08-10 | 2010-01-07 | アイスモス・テクノロジー・リミテッド | Method for manufacturing photodiode array with through-wafer via |
| WO2012169053A1 (en) | 2011-06-09 | 2012-12-13 | トヨタ自動車株式会社 | Semiconductor device and method for producing semiconductor device |
| JP2015056622A (en) * | 2013-09-13 | 2015-03-23 | 株式会社リコー | Semiconductor device |
| JP6311468B2 (en) * | 2014-06-12 | 2018-04-18 | 株式会社ソシオネクスト | Semiconductor device and integrated circuit |
| JP2016092178A (en) * | 2014-11-04 | 2016-05-23 | 株式会社リコー | Solid state imaging device |
| JP2017183403A (en) * | 2016-03-29 | 2017-10-05 | ルネサスエレクトロニクス株式会社 | Semiconductor device and method of manufacturing the same |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4837232A (en) * | 1971-09-15 | 1973-06-01 | ||
| JPS5882532A (en) * | 1981-11-11 | 1983-05-18 | Toshiba Corp | Element separation method |
| JPS59188966A (en) * | 1983-04-12 | 1984-10-26 | Matsushita Electronics Corp | Manufacture of solid-state image pickup device |
-
1984
- 1984-12-03 JP JP59254156A patent/JPH0691233B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61133659A (en) | 1986-06-20 |
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