JPH0691087B2 - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device

Info

Publication number
JPH0691087B2
JPH0691087B2 JP18048986A JP18048986A JPH0691087B2 JP H0691087 B2 JPH0691087 B2 JP H0691087B2 JP 18048986 A JP18048986 A JP 18048986A JP 18048986 A JP18048986 A JP 18048986A JP H0691087 B2 JPH0691087 B2 JP H0691087B2
Authority
JP
Japan
Prior art keywords
via hole
semiconductor device
pulse width
layer
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP18048986A
Other languages
Japanese (ja)
Other versions
JPS6337634A (en
Inventor
良一 向井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP18048986A priority Critical patent/JPH0691087B2/en
Publication of JPS6337634A publication Critical patent/JPS6337634A/en
Publication of JPH0691087B2 publication Critical patent/JPH0691087B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Description

【発明の詳細な説明】 〔概要〕 本発明は半導体装置の製造方法において、 ビアホール(コンタクトホール及びスルーホールの総
称)をパルスレーザ光照射によるアルミニウム(Al)堆
積膜の溶融によって埋込む際、Si基板との接触部におい
て誘起されるAl/Si反応によるジャンクションのつきぬ
け、多層Al配線構造では下層Al配線の熱破壊をもたらす
不都合をなくすため、 パルスレーザ光のパルス幅を100ns以下に設定して照射
することにより、 上記の如き過度なAl/Si反応や下層Al配線の破壊をもた
らすことなくビアホールの埋込みを行ない得るようにし
たものである。
DETAILED DESCRIPTION OF THE INVENTION [Outline] In a method for manufacturing a semiconductor device according to the present invention, when a via hole (a generic term for a contact hole and a through hole) is buried by melting an aluminum (Al) deposited film by pulse laser light irradiation, Si Irradiation with pulse width of 100 ns or less is set in order to eliminate the inconvenience of junction breakage due to Al / Si reaction induced at the contact with the substrate and thermal destruction of the lower Al wiring in the multilayer Al wiring structure. By doing so, the via hole can be filled without causing the excessive Al / Si reaction and the destruction of the lower layer Al wiring as described above.

〔産業上の利用分野〕[Industrial application field]

本発明は半導体装置の製造方法、特に、ビアホールをパ
ルスレーザ光照射によるAl堆積膜の溶融によって埋込む
半導体装置の製造方法に関する。
The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device in which a via hole is buried by melting an Al deposited film by pulse laser light irradiation.

〔技術の背景〕[Background of technology]

第3図はビアホールにAlが堆積された状態の断面図を示
す。1はSi基板、2は層間絶縁膜、2aはビアホールであ
る。このビアホール2aにAl3を堆積するに際し、スパッ
タや蒸着等の方法を用いると、特に、アスペクト比(深
さ/直径)の高いビアホールでは、同図に示すようにビ
アホール側壁への付着率が悪く、Si基板1との接続不良
を生じ易い。同様にして多層Al配線構造では、上層Al配
線と下層Al配線との接続不良を生じ易い。
FIG. 3 is a sectional view showing a state in which Al is deposited in the via hole. Reference numeral 1 is a Si substrate, 2 is an interlayer insulating film, and 2a is a via hole. When depositing Al3 in the via hole 2a, if a method such as sputtering or vapor deposition is used, particularly in a via hole having a high aspect ratio (depth / diameter), the adhesion rate to the sidewall of the via hole is poor, as shown in FIG. Poor connection with the Si substrate 1 is likely to occur. Similarly, in the multilayer Al wiring structure, a connection failure between the upper layer Al wiring and the lower layer Al wiring is likely to occur.

このような接続不良を生じないようにするには、Al3の
上方からパルスレーザ光を照射することによってAl3を
溶融してビアホール2a内を埋込む方法が考えられる。し
かしながら、このパルスレーザ光の照射によるが加熱時
間を例えばμsオーダの比較的長い時間に設定すると、
Si基板1との接触部において過度なAl/Si反応を誘起し
たり、多層Al配線構造では下層Al配線の熱破壊をもたら
す不都合がある。
In order to prevent such connection failure, a method of irradiating a pulsed laser beam from above Al3 to melt Al3 and fill the via hole 2a is conceivable. However, if the heating time is set to a relatively long time, for example, on the order of μs, depending on the irradiation of this pulsed laser light,
There is a disadvantage that an excessive Al / Si reaction is induced in the contact portion with the Si substrate 1 or the lower Al wiring is thermally destroyed in the multilayer Al wiring structure.

〔発明の手段〕[Means for Invention]

本発明になる半導体装置の製造方法は、第1図に示す如
く、 アルミニウム3、又はアルミニウム合成物をパルス幅10
0ns以下のパルスレーザ光4で溶融してビアホール2aを
埋込む。
As shown in FIG. 1, the semiconductor device manufacturing method according to the present invention uses aluminum 3 or an aluminum compound with a pulse width of 10
The via hole 2a is filled by melting with the pulsed laser light 4 of 0 ns or less.

〔作用〕[Action]

パルス幅が100ns以下と比較的短いため、ジャンクショ
ン破壊を起す様な過度なAl/Si反応を誘起したり、下層A
l配線の熱破壊を生じることはない。
Since the pulse width is relatively short (100 ns or less), it induces excessive Al / Si reaction that causes junction breakdown, and lower layer A
l Does not cause thermal damage to the wiring.

〔実施例〕〔Example〕

第1図は本発明になる半導体装置の製造方法の一実施例
を示す断面図であり、同図中、第3図と同一構成部分に
は同一番号を付してその説明を省略する。第1図(A)
に示す如く、Al3の上方から照射するパルスレーザ光4
を例えばArF(波長λ=193nm)のエキシマレーザとし、
そのバスル幅を100ns以下の比較的短いオーダに設定す
る。このパルスレーザ光4の照射によってAl3は溶融さ
れ、第1図(B)に示すようにビアホール2a内を一様に
埋込んでAl層3aとを形成する。
FIG. 1 is a sectional view showing an embodiment of a method of manufacturing a semiconductor device according to the present invention. In FIG. 1, the same components as those in FIG. 3 are designated by the same reference numerals and the description thereof will be omitted. Fig. 1 (A)
As shown in, pulsed laser light 4 emitted from above Al3
Is, for example, an ArF (wavelength λ = 193 nm) excimer laser,
Set the bassle width to a relatively short order of 100ns or less. The irradiation of the pulsed laser beam 4 melts Al3, and as shown in FIG. 1 (B), the via hole 2a is uniformly buried to form an Al layer 3a.

このパルスレーザ光4は、第2図のパルス幅対Si反応層
の深さ特性図に示す如く、100ns以下のパルス幅を照射
する限りではSi層は高々0.3μmまでの深さしか反応し
ない。従って、Si基板1との接触部においてジャンキシ
ョン破壊を示す様な過度なAl/Si反応を誘起することは
ない。又、照射時間が短いので、多層Al配線構造に適用
しても下層Al配線を熱破壊してしまうようなことはな
い。
As shown in the pulse width vs. depth characteristic diagram of the Si reaction layer in FIG. 2, the pulsed laser light 4 causes the Si layer to react only up to a depth of 0.3 μm as long as a pulse width of 100 ns or less is applied. Therefore, the excessive Al / Si reaction that shows the junction breakdown is not induced in the contact portion with the Si substrate 1. Further, since the irradiation time is short, the lower Al wiring will not be thermally destroyed even when applied to the multi-layer Al wiring structure.

第2図に示す如くパルス幅が長い程、Si反応層の深さは
増加する。パルス幅100nsで約0.33μmの深さのSi反応
層が形成される。この0.33μm層の深さは現在製品化さ
れているMOSFETで構成されるLSIのソース,ドレインの
深さに相当しており、100nsのパルス幅が許容限界であ
ることになる。ソース,ドレインの深さはLSIの高集積
化に伴ってより浅くなっていく故、短いパルス幅のパル
スレーザ光を用いる必要性が増す。
As shown in FIG. 2, the longer the pulse width, the greater the depth of the Si reaction layer. A Si reaction layer having a pulse width of 100 ns and a depth of about 0.33 μm is formed. The depth of the 0.33 μm layer corresponds to the depth of the source and drain of LSIs made up of currently commercialized MOSFETs, and the pulse width of 100 ns is the allowable limit. Since the depth of the source and drain will become shallower as the integration of LSI becomes higher, it becomes necessary to use pulsed laser light with a short pulse width.

なお、ビアホール2aに埋込む物質としては純粋のAlの
他、Alと他の物質との合成物でもよい。
The substance to be buried in the via hole 2a may be pure Al or a compound of Al and another substance.

〔発明の効果〕〔The invention's effect〕

本発明によれば、アルミニウム、又は、アルミニウムと
他の物質との合成物をパルス幅100ns以下のパルスレー
ザ光で溶融してビアホールに埋込むようにしたため、レ
ーザ光照射時間としては比較的短く、これにより、Si基
板との接触部において過度なAl/Si反応を誘起すること
はなく、又、多層Al配線構造に適用しても下層Al配線を
熱破壊してしまうようなことはなく、高品質の半導体装
置を得ることができ、LSIの高集積化に伴ってソース,
ドレインの深さが浅くなっていく現状にも十分対処し得
る等の特長を有する。
According to the present invention, since aluminum or a composite of aluminum and another substance is melted with a pulsed laser light having a pulse width of 100 ns or less and embedded in a via hole, the laser light irradiation time is relatively short, As a result, an excessive Al / Si reaction is not induced in the contact area with the Si substrate, and even when applied to a multilayer Al wiring structure, it does not cause thermal damage to the lower layer Al wiring. It is possible to obtain high-quality semiconductor devices.
It has features such as being able to sufficiently cope with the present situation where the depth of the drain becomes shallow.

【図面の簡単な説明】[Brief description of drawings]

第1図は本発明方法の一実施例を示す断面図、 第2図はパルスレーザ光のパルス幅対Si反応層深さ特性
図、 第3図はビアホールにAlが堆積された状態を示す断面図
である。 図において、 1はSi基板、 2は層間絶縁膜、 2aはビアホール、 3はAl、 3aは溶融後のAl層、 4はパルスレーザ光である。
FIG. 1 is a sectional view showing an embodiment of the method of the present invention, FIG. 2 is a characteristic diagram of pulse width of pulsed laser light versus Si reaction layer depth, and FIG. 3 is a sectional view showing a state in which Al is deposited in a via hole. It is a figure. In the figure, 1 is a Si substrate, 2 is an interlayer insulating film, 2a is a via hole, 3 is Al, 3a is an Al layer after melting, and 4 is a pulsed laser beam.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】アルミニウム(3)、又は、アルミニウム
と他の物質との合成物をパルス幅100ns以下のパルスレ
ーザ光(4)で溶融してビアホール(2a)に埋込むこと
を特徴とする半導体装置の製造方法。
1. A semiconductor characterized in that aluminum (3) or a compound of aluminum and another substance is melted by a pulse laser beam (4) having a pulse width of 100 ns or less and embedded in a via hole (2a). Device manufacturing method.
JP18048986A 1986-07-31 1986-07-31 Method for manufacturing semiconductor device Expired - Lifetime JPH0691087B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18048986A JPH0691087B2 (en) 1986-07-31 1986-07-31 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18048986A JPH0691087B2 (en) 1986-07-31 1986-07-31 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPS6337634A JPS6337634A (en) 1988-02-18
JPH0691087B2 true JPH0691087B2 (en) 1994-11-14

Family

ID=16084127

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18048986A Expired - Lifetime JPH0691087B2 (en) 1986-07-31 1986-07-31 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JPH0691087B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5250465A (en) * 1991-01-28 1993-10-05 Fujitsu Limited Method of manufacturing semiconductor devices

Also Published As

Publication number Publication date
JPS6337634A (en) 1988-02-18

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