JPH0686180A - Solid-state image pickup device - Google Patents

Abstract

PURPOSE:To make it possible to prevent irregularity of an image by always enabling a fixed exposure time by making the time till when a reading pulse is outputted after a trigger pulse is supplied constant. CONSTITUTION:In a solid-state image pickup device which is provided with an electronic shutter function and outputs a reading pulse for reading electric charge stored in a CCD image sensor 5 by counting the number of pulse of a horizontal synchronizing signal by a presribed number, a modulation HD preparation circuit 10 performs the delay of fixed time for an internal horizontal synchronizing signal to be supplied from a signal generator 8 and supplies this to a timing generator 11 when a trigger pulse is supplied from the outside. The timing generator 11 counts the number of pulse of the horizontal synchronizing signal by the prescribed number and outputs the reading pulse.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used, for example, in a camera device mainly used for industrial purposes for detecting the position of an object which moves at a high speed and for imaging the object in synchronization with the position detection information. The present invention relates to a suitable solid-state image pickup device, and more particularly, to a solid-state image pickup device that can make the exposure time of a solid-state image pickup element constant and always perform image pickup with the same set exposure time.

[0002]

2. Description of the Related Art Conventionally, the applicant of the present invention has filed Japanese Patent Application No. 2-238.
In the specification and the drawings of No. 930, a solid-state imaging device having an electronic shutter function for performing exposure adjustment without using an iris mechanism by controlling a charge storage time of a field storage type solid-state imaging device (CCD image sensor) is disclosed. is suggesting.

This solid-state image pickup device uses a high level image read pulse shown in FIG. 7B which is output during a vertical blanking period (VBLK) in which the vertical blanking signal shown in FIG. , Read out the charge accumulated in the CCD image sensor. The charge storage time of the CCD image sensor is controlled by the reset pulse shown in FIG. 7C, and the CCD image sensor sweeps the stored charge to the overflow drain when the reset pulse is supplied. ing. Therefore, while the reset pulse is being supplied (charge sweep-away period), no charge is accumulated in the CCD image sensor. Therefore, from the time when the reset pulse supplied to the CCD image sensor is stopped, the C
Since charges are accumulated in the CD image sensor, the charge accumulation time of the CCD image sensor, that is, the shutter speed can be controlled by controlling the timing of stopping the reset pulse.

By using such an electronic shutter function, the solid-state image pickup device can change the shutter speed according to the movement of the subject, so that the resolution of a moving image can be particularly improved. .

Here, there is known a solid-state image pickup device which is mainly used for industrial purposes and which picks up an image of a moving object. This solid-state imaging device has a configuration as shown in FIG. 8, for example, and when the object 101 moving on the moving path 100 moves in front of the imaging unit 102, the position detection unit 103 detects it. , A low-level trigger pulse shown at time t11 in FIG. 9A is supplied to the shutter pulse generation circuit 104.

The shutter pulse generation circuit 104 supplies a low level shutter pulse to the CCD control circuit 105 when a high level trigger pulse is supplied, and when the low level trigger pulse is supplied, the shutter pulse generation circuit 104 shown in FIG.
A high-level shutter pulse is supplied to the CCD control circuit 105 as shown at time t11 in (b).

The CCD control circuit 105 supplies a reset pulse for sweeping away charges accumulated in the CCD image sensor 106 while the low level shutter pulse is supplied. As a result, the CCD image sensor 106 does not capture an image while the reset pulse is being supplied. However, when the high level shutter pulse is supplied, the reset pulse supplied to the CCD image sensor 105 is stopped. As a result, the charge accumulation in the CCD image sensor 106 is started.

In the CCD control circuit 105, the synchronization signal generating circuit 107 outputs from the time t11 to the time t1 in FIG. 9C.
The low level vertical synchronizing signal shown in FIG. 2 and the horizontal synchronizing signal shown in FIG. When the shutter pulse is supplied to the CCD control circuit 105, the CCD control circuit 105 shown in FIG.
Time t1 when the vertical synchronizing signal shown in (c) falls.
1, the number of pulses of the horizontal synchronizing signal shown in FIG. 3D is counted, for example, 9 and then several hundred clock pulses are counted, and then the high-level read pulse shown at time t13 in FIG. It is supplied to the CCD image sensor 106. Accordingly, from the time when the shutter pulse is supplied to the CCD image sensor 106 at time t11 in FIG. 9B to the time when the read pulse is supplied to the CCD image sensor 106 at time t13 in FIG. 9E. During this period, electric charges corresponding to the imaging light emitted through the imaging lens 108 are accumulated in the CCD image sensor 106, and the shutter speed is between time t11 and time t13.

The charges are read from the CCD image sensor 106 from time t11 to time t11 shown in FIG. 9 (f).
It is performed during the vertical blanking period which is between time t14.

The charges read from the CCD image sensor 106 are used as an image pickup signal in the image pickup signal processing circuit 10.
9 is supplied. The image pickup signal processing circuit 109 performs signal processing such as adding a synchronization signal to the image pickup signal and outputs the signal through the output terminal 110. This output terminal 1
The imaging signal output via 10 is supplied to, for example, the display screen of the analyzer. This makes it possible to analyze the state and the like of the object 101 when the object 101 is moved.

[0011]

However, the phase relationship between the vertical synchronizing signal and the horizontal synchronizing signal in the industrial solid-state imaging device is that the horizontal synchronizing signal is at time t in FIG. 7 (a).
While it falls at 15, time t17, and time t22,
A phase relationship in which the vertical synchronizing signal falls several clocks before and after the falling of the horizontal synchronizing signal so that the vertical synchronizing signal falls at time t16 or time t18 in FIG. Has become.

The vertical synchronizing signal is the same as that shown in FIG.
As shown at time t20 in (a), the phase relationship is such that it falls at several clocks (time t19 or time t21) before and after the fall of the horizontal synchronizing signal and the next fall. .

Therefore, in order to latch the vertical synchronizing signal used in this solid-state image pickup device, a pulse which is supplied after the trigger pulse and whose frequency is the same as the frequency of the horizontal synchronizing signal or whose frequency is the horizontal synchronizing signal is used. It is necessary to use a pulse with twice the frequency.

On the other hand, the CCD control circuit 105
Is configured to count the number of pulses of the horizontal sync signal from the falling edge of the vertical sync signal 9 times and then to count the clock pulse several hundreds before outputting the read pulse. Figure 8 (a)
If it is supplied at time t25, the above-mentioned counting is started from the horizontal sync signal shown in FIG. 7B immediately after time t26, which is the fall of the vertical sync signal shown in FIG. The Rukoto.

Similarly, if the trigger pulse is supplied at time t27 in FIG. 9A, the horizontal synchronizing signal shown in FIG. 9B is the falling edge of the vertical synchronizing signal shown in FIG. 9C. The above counting is started from the horizontal synchronizing signal immediately after time t28.

As described above, since the trigger pulse is randomly supplied to the solid-state image pickup device, the trigger pulse is supplied at any time during the supply of the first horizontal synchronizing signal and the next horizontal synchronizing signal. Or not specified.

Therefore, the CCD image sensor 10 described above is used.
The charge storage time (exposure time) of No. 6 fluctuates according to the timing at which the trigger pulse is supplied, resulting in unevenness in the image even when image pickup is performed at the same shutter speed.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a solid-state imaging device capable of preventing image unevenness by keeping the exposure time of the solid-state imaging device constant. .

[0019]

The solid-state image pickup device according to the present invention is a read-out device for reading out the accumulated charge from the time when the supply of the reset pulse for sweeping away the charge accumulated in the solid-state image-pickup device is stopped. An electric shutter function is provided to control the charge storage time of the solid-state image sensor by controlling the timing of stopping the supply of the reset pulse, with the charge storage time being the period until the pulse is supplied to the solid-state image sensor. And the read pulse is
A solid-state imaging device for counting a predetermined number of pulses of a horizontal synchronization signal from a time when a vertical synchronization signal is supplied and supplying the pulses to the solid-state imaging device. When a trigger pulse is externally supplied, the reset pulse is supplied. Shutter pulse forming means for forming and outputting a shutter pulse for stopping, and synchronizing signal generating means for forming and outputting a vertical synchronizing signal and a horizontal synchronizing signal when a trigger pulse is supplied from the outside, When a trigger pulse is supplied from the outside,
The horizontal synchronizing signal supplied from the synchronizing signal generating means is delayed by a certain time and then output, and the number of pulses of the horizontal synchronizing signal supplied from the delaying means is counted. The above-mentioned problem is solved as a configuration characterized in that it has a read pulse forming means for forming the read pulse and supplying the read pulse to the solid-state imaging device.

[0020]

The solid-state image pickup device according to the present invention counts a predetermined number of pulses of the horizontal synchronizing signal from the time when the vertical synchronizing signal is supplied, and outputs a read pulse when the count value reaches a predetermined value. However, when the trigger pulse is supplied from the outside, the delay means delays the horizontal synchronizing signal supplied from the synchronizing signal generating means by a fixed time and outputs it.

As a result, regardless of the timing at which the vertical synchronizing signal is supplied, the period from the supply of the trigger pulse to the start of counting the horizontal synchronizing signal can be made constant.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the solid-state image pickup device according to the present invention will be described below with reference to the drawings. The solid-state imaging device according to the present embodiment supplies the read pulse for reading the accumulated charge to the solid-state image sensor from the time when the supply of the reset pulse for sweeping away the charge accumulated in the solid-state image sensor is stopped. The electronic shutter function is provided to control the charge storage time of the solid-state image sensor by controlling the timing of stopping the supply of the reset pulse, and the read pulse is A solid-state imaging device that counts a predetermined number of pulses of a horizontal synchronization signal from the time when a synchronization signal is supplied and supplies the pulses to the solid-state imaging device. For example, as shown in FIG. The position detector 3
Can be used as an industrial solid-state image pickup device that picks up an image of the object 2 in synchronization with an external trigger pulse that is a position detection signal from the position detection section 3.

As a concrete configuration, as shown in FIG. 1, the phases of an external vertical synchronizing signal and an external horizontal synchronizing signal supplied from the outside are adjusted and output as an internal vertical synchronizing signal and an internal horizontal synchronizing signal, respectively. And a signal generator 8 which is a synchronization signal generating means for outputting a pulse (f _CK / 4) having a cycle four times as long as the clock pulse (f _CK ).
When the trigger pulse is supplied from the position detecting unit 3, the shutter speed can be specified, and the phase of the internal horizontal synchronizing signal (HD) of the signal generator 8 is changed according to the specified shutter speed. Modulation H, which is a delay means for modulating and forming a modulated horizontal synchronizing signal, and delaying and outputting the modulated horizontal synchronizing signal for a predetermined time
And a D creating circuit 10.

The solid-state image pickup device detects and outputs a phase difference between an external horizontal synchronizing signal supplied from the outside through the signal generator 8 and an internal horizontal synchronizing signal supplied from the signal generator 8. And a low-pass filter (LP) that forms and outputs a control DC voltage from the phase comparison output from the comparator 13.
F) 14 and a voltage controlled oscillator (VCO) 15 that oscillates in response to the control DC voltage from the LPF 14.

The solid-state image pickup device supplies the clock pulse (f _CK ) to the signal generator 8 and also the internal vertical synchronizing signal and the modulated horizontal synchronizing signal (or the internal horizontal synchronizing signal) supplied from the signal generator 8. Signal), a timing generator 11 which is a read pulse forming means for outputting a read pulse or the like for reading the charges accumulated in the CCD image sensor 5, and the CCD image sensor in response to the pulse from the timing generator 11. C driving 5
It has a CD drive circuit 12.

Further, in the solid-state image pickup device, when the trigger pulse is supplied, a reset pulse for sweeping away the electric charge accumulated in each pixel, which is supplied from the CCD drive circuit 12 to the CCD image sensor 5. Shutter creating circuit 16 which is a shutter pulse forming means for supplying a shutter pulse for stopping the operation to the CCD drive circuit 12.
And an image pickup signal processing circuit 17 which performs signal processing such as adding a synchronizing signal to the image pickup signal which is the electric charge read from the CCD image sensor 5 and supplies the signal to an analyzer for image analysis or the like. ing.

Next, the operation of the solid-state image pickup device of the embodiment having such a configuration will be described. First, in FIG. 1, for example, when it is desired to analyze the moving state of the object 2 moving at high speed, the moving path 1 is controlled so as to move the object 2 at high speed.

The position detecting section 3 outputs a trigger pulse when it detects that the object 2 moving on the moving path 1 is positioned in front of the CCD image sensor 5. This trigger pulse is generated by the signal generator 8 and the modulation HD.
It is supplied to the creating circuit 10, the timing generator 11, and the shutter creating circuit 16.

On the other hand, the comparator 13 detects the phase difference between the external horizontal synchronizing signal supplied from the outside via the signal generator 8 and the internal horizontal synchronizing signal supplied from the signal generator 8, and LPF14
Supply to. The LPF 14 forms a control DC voltage from the phase comparison output from the comparator 13 and outputs it to VC.
Supply to O15. The VCO 15 is the LPF 14
A clock pulse (2f _CK ) having, for example, twice the frequency of the clock pulse (f _CK ) supplied from the timing generator 11 to the signal generator 8 is formed according to the control DC voltage from Supply to the generator 11.

The timing generator 11 latches the internal vertical synchronizing signal from the signal generator 8 with the clock pulse having the doubled frequency, and forms the internal vertical synchronizing signal as shown in FIG. 3A, for example. Then, this is supplied to the CCD image sensor 5 via the CCD drive circuit 12.

The shutter forming circuit 16 forms and outputs the reset pulse until the trigger pulse is supplied. This reset pulse is the above-mentioned CCD
It is supplied to the CCD image sensor 5 via the drive circuit 12. The CCD image sensor 5 is adapted to sweep away the accumulated charges to the overflow drain while the reset pulse is being supplied. Therefore, while the reset pulse is being supplied, no charge is accumulated in the CCD image sensor 5 and no image pickup signal is output.

However, when the shutter pulse is supplied, the shutter forming circuit 16 forms a shutter pulse and supplies it to the CCD drive circuit 12. C above
When the shutter pulse is supplied, the CD drive circuit 12 stops the reset pulse supplied to the CCD image sensor 5. As a result, the CCD image sensor 5 starts accumulating charges according to the imaging light emitted through the imaging lens 4.

On the other hand, when the signal generator 8 is supplied with the trigger pulse, it forms a pulse (f _CK / 4) having a quadruple cycle from the clock pulse (f _CK ) supplied from the timing generator 11, Modulate this H
It is supplied to the D creating circuit 10.

The modulation HD creation circuit 10 is shown in FIG.
The pulse having the quadruple cycle is supplied to the clock terminal of the counter 25 via the input terminal 20 of the modulated HD creating circuit 10.

The mono-multi circuit 28 forms the reset pulse shown in FIG. 3B from the internal vertical synchronizing signal shown in FIG. Supply. The counter 25 is reset by the reset pulse from the mono-multi circuit 28 from the trailing edge of the internal vertical synchronizing signal, outputs the ripple carry signal by counting, for example, 16 pulses of the quadruple cycle.

The ripple carry signal is then output in hexadecimal operation.

Next, the data of the D flip-flop 29 is set to "H" in advance, and when the reset pulse is supplied from the mono-multi circuit 28 as shown in FIG. Output is "H" (high level signal)
To "L" (low level signal), and after reset, changes from "L" to "H" again at the first rising edge of the clock input. The output signal from the D flip-flop 29 is supplied to the reset terminal of the counter 26.

Since the ripple carry signal from the counter 25 is supplied to the clock terminal of the counter 26, when the output signal from the D flip-flop 29 is supplied to the counter 26, the counter 26 is reset and reset. A period corresponding to a cycle of 4 × 16 × 16 times the clock,
A ripple carry signal is output after "L" continues.

Next, the other stage of the D flip-flop 29 is reset by being supplied with the reset pulse from the mono-multi circuit 28, and is supplied with the ripple carry signal from the counter 26 at the clock input.
As a result, the D flip-flop 29 shown in FIG.
An output signal as shown in (d) is output. The output signal from the D flip-flop 29 is supplied to the load terminal of the counter 27.

When the output signal is supplied from the D flip-flop 29, the counter 27 is preset with preset data (P0 to P3) while the "L" ripple carry signal is supplied to the load terminal. The selected data is output via the output terminals of Q0 to Q3. By this preset data, after the ripple carry signal of "L" is supplied to the load terminal of the counter 27,
The ripple carry signal output from the counter 27 rises after 9 counts of the input clock. The ripple carry signal from the counter 27 is supplied to the clock input terminal of the D flip-flop 30.

Since the D flip-flop 30 is reset in advance by the reset pulse from the mono-multi circuit 28, when the ripple carry signal is supplied from the counter 27, it is as shown in FIG. Output the output signal.

The NAND gates 32 and 33 are the same as those shown in FIG.
By synthesizing the output signal from the D flip-flop 29 shown in (d) and the output signal from the D flip-flop 30 shown in (e) of the figure, the synthesized signal shown in (f) of the figure is output. . This combined signal is supplied to the NAND gate 34.

In addition to the synthesized signal, the NAND gate 34 is supplied with the pulse of the quadruple cycle via the input terminal 20, and the NAND gate 34 is supplied with the pulse as shown in FIG. 3 (k). Then, the pulse of the quadruple cycle is output only during the period when the composite signal becomes "H". At this time, the rising timing of the ripple carry signal output from the counter 27 after 9 clocks of the input clock is included in the period in which a pulse of a quadruple cycle is output from the NAND gate 34. The output signal from the D flip-flop 30 is low-pass filtered and supplied to the NAND gate 32.

The pulse of the quadruple cycle output from the NAND gate 34 is supplied to one input terminal of the NAND gate 37.

On the other hand, the modulation HD concerned is input via the input terminal 24.
The internal horizontal synchronizing signal supplied to the creating circuit 10 is the NAN.
It is supplied to each clock input terminal of the two-stage D flip-flop 31 and the other input terminal of the NAND gate 36 via the D gate 35.

The output signal output from the D flip-flop 30 has timing information obtained by counting 9 pulses of a quadruple cycle, and the output data obtained by inverting the output signal is the D flip-flop 31 in the first stage. It is supplied to the reset terminal of. As a result, the D flip-flop 31 outputs an output signal as shown in FIG. The output signal from the D flip-flop 31 is supplied to the second-stage D flip-flop 31.

The second-stage D flip-flop 31 is
When the output signal from the D flip-flop 31 is supplied, an output signal as shown in FIG. 3 (h) is formed and supplied to one input terminal of the NAND gate 36.

The NAND gate 36 is supplied with the output signal from the second-stage D flip-flop 31 shown in FIG. 3 (h) and the internal horizontal terminal supplied via the input terminal 24 shown in FIG. 3 (i). The sync signal and the sync signal are combined to form an output signal as shown in FIG. 3 (j), which is supplied to the other input terminal of the NAND gate 37.

As described above, the NAND gate 37 is supplied with a pulse having a quadruple cycle from the NAND gate 34 at one input terminal thereof.
Is generated by synthesizing the pulse of the quadruple period shown in FIG. 3K and the output signal from the NAND gate 36 shown in FIG. A modulated horizontal sync signal having a frequency higher than that of the sync signal is formed and output.

That is, the modulated horizontal synchronizing signal output from the NAND gate 37 is the output signal from the second-stage D flip-flop 31 shown in FIG. 3 (h).
By setting it to "L", the internal horizontal synchronizing signal during this period is erased as shown in FIG. 7 (h), and instead of this erased internal horizontal synchronizing signal, 9 high frequency waves are generated as shown in FIG. A signal is formed and combined with the internal horizontal synchronizing signal.

The modulated horizontal synchronizing signal output from the NAND gate 37 has a predetermined bit length by the NAND gate 38 and is supplied to the timing generator 11 shown in FIG.

The timing generator 11 counts the modulated horizontal synchronizing signal (or internal horizontal synchronizing signal) 9 times, counts several hundred clock pulses to form a read pulse, and supplies this to the CCD drive circuit 12. To do.

The CCD drive circuit 12 drives the CCD image sensor 5 so as to read the electric charge accumulated in the CCD image sensor 5 in response to the read pulse. The charges read from the CCD image sensor 5 are supplied to the image pickup signal processing circuit 17 as an image pickup signal.

The image pickup signal processing circuit 17 performs signal processing such as adding a synchronizing signal to the image pickup signal, and supplies it to the monitor device of the analyzer, for example, through the output terminal 18.

As a result, an image of the object 2 moving on the moving path 1 is displayed on the monitor device, and the object can be analyzed.

Here, the timing generator 11
Counts the modulated horizontal synchronizing signal (or internal horizontal synchronizing signal) 9 times and then outputs a read pulse by counting hundreds of clock pulses. The timing generator 11 counts the internal horizontal synchronizing signal 9 times. rear,
The read pulse cannot be output if the timing of the next internal horizontal synchronizing signal supplied is early.

Therefore, the output signal of the D flip-flop 31 having the two-stage configuration is "L" by the output signal shown in FIG. 3 (h).
During the period, the internal horizontal synchronizing signal shown in (i) of the figure is prevented from being supplied to the timing generator 11 and is output from the D flip-flop 31 of the two-stage configuration during the period. Depending on the output signal, the above 4
By setting the interval from the 9th pulse of the double-cycle pulse to the supply of the next internal horizontal synchronizing signal to 1H (the phase of the normal internal horizontal synchronizing signal) or more, the timing generator 11 can reliably perform the operation. A read pulse is output.

The counter 26 is reset and then
A period corresponding to a cycle of 4 × 16 × 16 times the clock,
A ripple carry signal is output after "L" continues. This means that, after the trigger pulse is supplied, the pulse having the quadruple cycle is generated after elapse of a certain period of 1H or more, for example.

Therefore, no matter what phase the internal vertical synchronizing signal is generated with respect to the trigger pulse, counting of the modulated horizontal synchronizing signal (and internal horizontal synchronizing signal) is started from the falling edge of the internal vertical synchronizing signal. The exposure time can be kept constant even if the trigger pulse is generated at random timing, and a uniform image can be displayed on the monitor device.

Further, since an interval of 1H or more is provided before and after the timing at which the modulated horizontal synchronizing signal is output,
The read pulse is output earlier than a predetermined timing, and is caused by the effective pixels being read earlier,
It is possible to prevent an optical black pixel portion (OPB) provided to obtain a reference black level at the lower end portion of the display screen of the analyzer from being displayed outside, and to prevent the read pulse from being displayed. It is possible to prevent the OPB from being displayed outside the upper end portion of the display screen, which is caused by the output later than the predetermined timing and the effective pixels being read out later.

Since the modulated horizontal sync signal has a higher frequency than the internal horizontal sync signal of the normal frequency as described above, the count of the modulated horizontal sync signal is greater than that of the internal horizontal sync signal counted by the timing generator 11. Can be ended earlier, the read pulse can be output earlier correspondingly, and a high-speed shutter can be realized.

Further, since the frequency of the modulated horizontal synchronizing signal formed by the modulated HD creating circuit 10 can be varied, a desired shutter speed can be achieved.

Specifically, the shutter speed can be controlled by controlling the frequency of the modulated horizontal synchronizing signal or the length of a fixed time until the pulse of the quadruple cycle is generated.

That is, the time until the pulse having the quadruple cycle is generated is 1H, and the period of the pulse having the quadruple cycle is 7 hours.
With 0 ns, the shutter speed can be set to 64 μs + 0.07 × 8 μ + 42 μ = 106.56 μs≈1 / 9400 s.

When the internal vertical synchronizing signal is latched by the clock pulse (2f _CK ) having the double frequency in the timing generator 11 as described above, the time until the pulse of the quadruple cycle is generated is 1 Since it can be set to / 2H or more, the shutter speed can be set to 32 μs + 0.07 × 8 μ + 42 μ = 74.56 μs≈1 / 13000 s, which enables a high-speed shutter.

Therefore, an image of an object moving at high speed can be clearly and easily captured, which can contribute to industrial use and the like.

The solid-state image pickup device is the same as the conventional solid-state image pickup device having the existing timing generator 11 which counts the horizontal synchronizing signal 9 times and then counts several hundred clock pulses to output a read pulse. Since only the modulation HD creation circuit 10 is provided, changes in the conventional circuit configuration can be minimized.

The technical idea according to the present invention is that a solid-state image pickup device provided with an electronic shutter function and picking up an image in synchronization with a trigger pulse which is randomly supplied has a predetermined period after the trigger pulse is supplied. The exposure time of the solid-state imaging device is made constant by outputting a horizontal synchronizing signal after a lapse of a period, counting a predetermined number of the horizontal synchronizing signal, and then outputting a read pulse.

Therefore, the circuit configuration is not limited to those shown in the above-described embodiments, and it goes without saying that various modifications can be made without departing from the technical idea described above.

[0070]

The solid-state image pickup device according to the present invention counts the number of pulses of the horizontal synchronizing signal by a predetermined number from the time when the vertical synchronizing signal is supplied, and outputs the read pulse when the count value reaches the predetermined value. When the trigger pulse is supplied from the outside, the delay means delays the horizontal synchronizing signal supplied from the synchronizing signal generating means by a certain time and outputs the horizontal synchronizing signal.

As a result, regardless of the timing of supplying the vertical synchronizing signal, the period from the supply of the trigger pulse to the start of counting the horizontal synchronizing signal can be made constant, and the solid-state image sensor The exposure time of can always be constant.

Therefore, it is possible to prevent image nonuniformity of the image picked up by the solid-state image pickup device and contribute to analysis of the picked-up image.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment when the solid-state imaging device according to the present invention is applied to an industrial solid-state imaging device that performs imaging in synchronization with a trigger pulse supplied at random timing.

FIG. 2 is a circuit diagram showing a specific configuration of a modulation HD creation circuit provided in the solid-state imaging device of the above embodiment.

FIG. 3 is a time chart for explaining the operation of the solid-state imaging device of the above embodiment.

FIG. 4 is a time chart for explaining the operation of a conventional solid-state imaging device having an electronic shutter function.

FIG. 5 is a block diagram of a conventional industrial solid-state imaging device that performs imaging in synchronization with a trigger pulse supplied at random timing.

FIG. 6 is a time chart for explaining the operation of the conventional industrial solid-state imaging device.

FIG. 7 is a time chart for explaining a phase relationship between a horizontal synchronizing signal and a vertical synchronizing signal of the conventional industrial solid-state imaging device.

FIG. 8 is a time chart for explaining the timing at which the CCD control circuit provided in the conventional industrial solid-state imaging device starts counting a predetermined number of horizontal synchronization signals.

FIG. 9 is a time chart for explaining the timing at which the CCD control circuit provided in the conventional industrial solid-state imaging device starts counting a predetermined number of horizontal synchronization signals.

[Explanation of symbols]

1 ... Movement 2 ... Object 3 ...・ ・ ・ Position detector 4 ・ ・ ・ Imaging lens 5 ・ ・ ・ ・ ・ CCD image sensor 8 ・ ・ ・・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ Signal generator 10 ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ Modulation HD creation circuit 11 ・ ・ ・ ・ ・ ・ ・ ・・ Timing generator 12 ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ CCD drive circuit 13 ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ Comparator 14 ・ ・ ・ ・・ ・ ・ ・ ・ ・ Low-pass filter (LPF) 15 ・ ・ ・ ・ ・ ・ Voltage-controlled oscillator (VCO) 16 ・ ・ ・ ・ ・ ・Shutter creation circuit 17 ... ..... Imaging signal processing circuit

Claims (1)

[Claims] 1. From the time when the supply of a reset pulse for sweeping away the charges accumulated in the solid-state image sensor is stopped,
The charge storage time of the solid-state image sensor is controlled by controlling the timing at which the supply of the reset pulse is stopped until the read pulse for reading the accumulated charge is supplied to the solid-state image sensor. An electronic shutter function for controlling is provided, and the read pulse is a solid-state imaging device that counts a predetermined number of pulses of a horizontal synchronization signal from the time when a vertical synchronization signal is supplied and supplies the pulses to the solid-state imaging device. , A shutter pulse forming means for forming and outputting a shutter pulse for stopping the supply of the reset pulse when a trigger pulse is supplied from the outside, and a vertical synchronization signal when the trigger pulse is supplied from the outside, A synchronizing signal generating means for forming and outputting a horizontal synchronizing signal, and a trigger pulse supplied from the outside as described above, The horizontal synchronizing signal supplied from the signal generating means is delayed by a certain time and output, and the number of pulses of the horizontal synchronizing signal supplied from the delay means is counted, and the count value becomes a predetermined number. By the way, a solid-state image pickup device comprising a read pulse forming means for forming the read pulse and supplying the read pulse to the solid-state image sensor.