JPH0685636A - Output circuit - Google Patents

Abstract

PURPOSE:To shorten the rise and fall times of an output waveform by detecting a fixed section of the rise and fall of an output circuit based on the output voltage and supplying the sufficient drive current to the base of an output stage transistor TR. CONSTITUTION:An output circuit consists of a PNP TR 1, an NPN TR 3, a constant current circuit, and a control circuit which actuates both TR 1 and 3 in a state opposite to each other. The output is transmitted from an output terminal 5 synchronously with the input supplied from an input terminal 13. When the output is set at a high level, the state of the terminal 5 is detected by an NPN TR 21 and a diode 22. If the terminal 5 has the output voltage less than a prescribed level, the TR 21 is turned on and the base current of the TR 1 is supplied.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output circuit, and more particularly to an output circuit advantageous for driving a capacitive load such as an input of a C-MOS integrated circuit.

[0002]

2. Description of the Related Art As shown in FIG. 5, a conventional output circuit is composed of an output stage, a constant current circuit and a control circuit.

In this output stage, the emitter of the PNP transistor 1 is connected to the power supply terminal 2, the emitter of the NPN transistor 3 is connected to the ground terminal 4, and the PNP transistor 1 is connected.
And the collector of the NPN transistor 3 are commonly connected to the output terminal 5, and the base of each transistor is used as an input.

The constant current circuit connects the constant current source 6 to the collector and base of the PNP transistor 7, and at this point the PNP is connected.
The bases of the transistors 8 and 9 are connected, and the emitters of the PNP transistors 7, 8 and 9 are resistors 10, 11, and 1, respectively.
It is configured to be connected to the power supply terminal 2 via 2.

The control circuit operates from the input terminal 13 to the resistor 14,
The NPN transistors 16 and 17 are connected to the bases of the NPN transistors 16 and 17, respectively, and the emitters of the NPN transistors 16 and 17 are connected to the ground terminal 4 via the resistors 18 and 19, respectively.
The collector of the PN transistor 16 is connected to the collector of the PNP transistor 8 and the base of the NPN transistor 3, and the collector of the NPN transistor 17 is connected to the collector of the PNP transistor 9 and the base of the PNP transistor 1. The resistor 20 is a PN
It is provided to prevent insufficient driving of the PNP transistor 8 due to saturation of the P transistor 9.

Next, as the operation of this output circuit, a waveform synchronized with the pulse signal input to the input terminal 13 is output to the output terminal 5. For example, when the input terminal 13 becomes high level, the NPN transistor 16 is turned on, the collector current of the PNP transistor 8 is drawn, and the NPN transistor is turned off. On the other hand, the NPN transistor 17 turns on, supplies the base current of the PNP transistor 1 and turns on, and the output terminal 5 becomes high level.

When the input terminal 13 becomes low level,
The operation is reversed, the NPN transistor 3 is turned on, and the output terminal becomes low level.

[0008]

The output circuit of this type is
When an input stage of a C-MOS integrated circuit or the like is connected as a load, it becomes a capacitive load. Therefore, the rise time tr and the fall time tf of the output waveform are calculated by the load capacitance C
When L and the output voltage change width ΔV are constant, it is determined by the output current value.

Tr = (CL · ΔV) / Io source tf = (CL · ΔV) / Io sink {where CL: load capacity (100PF), ΔV: output voltage change width (10V), Io source: output discharge current , Io sink: output sink current} When the rise time tr and the fall time tf of the output waveform are slow, when an input such as a C-MOS integrated circuit is connected to the output terminal 5, the output voltage near the input threshold is The noise margin is insufficient, and external circuits or the like malfunction the circuits in the subsequent stages.

As a countermeasure against this, in order to increase the output current value, the current value of the constant current circuit is increased so that the output waveform rises as shown by the dotted line in FIG.
Although a method of shortening the fall time has been adopted, as shown in FIG. 6 as the current of the power supply terminal 2 and the current of the ground terminal 4, the circuit current is also large as shown by the dotted line.

As described above, conventionally, there has been a problem that the circuit current must be increased in order to shorten the rise time and the fall time of the output waveform. Further, when the circuit current is reduced, there is also a problem that a malfunction occurs due to noise near the threshold of the input circuit connected to the output terminal 5.

Therefore, an object of the present invention is to provide an output circuit capable of advancing the rise time and fall time of an output waveform without increasing the circuit current.

[0013]

To achieve the above object, in the present invention, a drive circuit for supplying a current to the base of the transistor in the output stage is connected only while the output terminal reaches a prescribed level. .

In the present invention, the first output stage PNP transistor is replaced with an NPN transistor, and the emitter of the NPN transistor as the first output stage and the collector of the second output stage NPN transistor are output terminals. Totem pole type output stage and the first output stage N
A control circuit for inverting the PN transistor and the second output-stage NPN transistor in opposite states is provided.

[0015]

The base current of the output stage transistor is supplied to the conventional output circuit only in the section in which the output terminal rises and falls to a specified level.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION The output circuit of the present invention includes an output stage in which the emitters of a first output stage PNP transistor and a second output stage NPN transistor are connected to a power supply terminal and a ground terminal, respectively, and an output terminal is used as a common collector. In an output circuit equipped with a control circuit for operating the first output stage PNP transistor and the second output stage NPN transistor in opposite states, the output stage is increased and decreased to a specified level only in the output stage. It is characterized in that a drive circuit for additionally supplying the base current of the transistor is added.

In the above invention, the drive circuit for supplying the base current uses the NPN transistor having the collector connected to the collector of the first output stage PNP transistor and the collector connected to the base, and the emitter as the power supply terminal, and the base connected to the base. The collector of the second output stage NPN transistor has a collector and the base of the second output stage NPN transistor has a collector common to the base of the output stage PNP transistor and has a collector connected to the NPN transistor through 0 to several diodes. The PNP transistor is connected, the emitter is a ground terminal, the base is common with the base of the output stage NPN transistor, and the collector is an NPN transistor connected to the PNP transistor through 0 to several diodes.

Embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram according to an embodiment of the present invention. FIG. 2 is an input / output waveform diagram thereof. 3 and 4 show
It is explanatory drawing of the other Example of this invention. Note that the same parts as those of the conventional example shown in FIG.

In this embodiment, as shown in FIGS. 1 and 4,
NPN transistor 2 in which the collector of the first output stage PNP transistor 1 is connected to the emitter and the base is connected to the collector
1 and a diode 22 having a cathode connected to the base of the NPN transistor 21.

Further, a collector is connected to the anode of the diode 22, the emitter is connected to the power supply terminal 2 via the resistor 23, and the base is connected to the base of the first output stage PNP transistor 1 via the resistor 24 in common. A PNP transistor 25 is added.

Similarly, the second output stage NPN transistor 3
P with the emitter connected to the collector and the collector connected to the base
An NP transistor 26, a diode 27 having an anode connected to the base of the PNP transistor 26, a collector connected to the cathode of the diode 27, an emitter connected to the ground terminal 4 via a resistor 28, and a base connected to the ground terminal 4 via a resistor 29. An NPN transistor 30 connected in common with the base of the second output stage NPN transistor 3 is added.

The circuit operation of this embodiment is similar to that of the conventional example, but the input terminal 13 changes from low level to high level, and NP
When the N transistor 17 is turned on, the PNP transistor 1 is turned on, and the output terminals 5 and 5 ′ rise, the PNP transistor 25 is also turned on, and the NP transistor 25
The N-transistor 21 is turned on, and the PNP transistor 1
Is further supplied with a base current to increase the discharge current Io source flowing from the output terminal 5 to the load to obtain an output waveform with a fast rise time tr as shown by the waveform of the input terminal 5 in FIG.

Further, the potential of the output terminal 5 is the prescribed potential V ₁
The NPN transistor 21 is operating up to the section of rising. The prescribed V ₁ can be changed by shorting the diode 22 or by making a plurality of diodes 22. V ₁ is Vcc-Vs
is almost equal to at-V _BE21 . (However, Vcc: voltage of power supply terminal 2, Vsat: saturation voltage of transistor 25,
(Vf: forward voltage of the diode 22, V _BE21 : voltage between the base and emitter of the transistor 21) Therefore, when the potential of the output terminal 5 rises above V ₁ , the output discharge current Io source becomes small and the circuit current Also less.

When the input terminal 13 changes from the high level to the low level, the NPN transistor 16 is turned off, the transistor 3 is turned on, the output terminal 5 is lowered, the NPN transistor 30 is turned on, and the PNP transistor 26 is turned on. When turned on, the base current is further supplied to the NPN transistor 3 to shorten the fall time tf of the output terminal 5.
Further, the specified potential V at this time is almost equal to Vsat + V _BE26 .

(However, Vsat: transistor 30
Saturation voltage, V _BE26 : base of transistor 26,
As described above, in this example,
In the conventional output circuit, the output terminal rises to the specified level,
Since the base current of the output-stage transistor is supplied only during the falling period, the circuit current does not rise due to the supply of the base current necessary for accelerating the rise and fall times of the output waveform. Further, the rise and fall times can be made sufficiently fast, so that malfunctions due to noise near the threshold of the circuit connected to the output terminal 5 can be eliminated with low current consumption.

In the example shown in FIG. 3, the first output stage PNP transistor 1 in the examples of FIGS. 1 and 4 is replaced with an NPN transistor 39, and the NPN transistor 39 serves as the emitter of the first output stage. , A control for reversing the totem pole type output stage using the collector of the second output stage NPN transistor 3 as an output terminal and the first output stage NPN transistor 39 and the second output stage NPN transistor 3 in opposite states. It has a circuit. This control circuit, as shown in FIG.
, A diode 22, an NPN transistor 37, resistors 35, 36 and the like.

[0027]

As described above, it is possible to provide an output circuit capable of accelerating the rise time and the fall time of the output waveform without increasing the circuit current.

[Brief description of drawings]

FIG. 1 is a diagram illustrating an output circuit diagram according to the present invention.

FIG. 2 is a diagram illustrating input / output waveforms of an output circuit according to the present invention.

FIG. 3 is an explanatory diagram of an output circuit diagram according to another embodiment of the present invention.

FIG. 4 is an explanatory diagram of an output circuit diagram according to another embodiment of the present invention.

FIG. 5 is an explanatory diagram of an output circuit diagram according to a conventional technique.

FIG. 6 is a diagram illustrating input / output waveforms of an output circuit according to a conventional technique.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 PNP transistor 2 Power supply terminal 3 NPN transistor 5 Output terminal 13 Input terminal 21 NPN transistor 26 which comprises a drive circuit 26 PNP transistor which comprises a drive circuit

Claims (2)

[Claims] 1. A constant current circuit, a first output stage PNP transistor, and a second output stage NPN transistor are provided in series between a power supply terminal and a ground terminal, and the collectors of the transistors are common. A drive current is supplied to the output stage used as the output terminal, the bases of the first output stage PNP transistor and the second output stage NPN transistor in accordance with the level of the input terminal, and the first output stage PNP transistor and , An output circuit having a control circuit for operating the second output stage NPN transistor in a contradictory state, a drive circuit for supplying current to the base of the transistor of the output stage only while the output terminal reaches a prescribed level. An output circuit characterized by being connected. 2. The output circuit according to claim 1, wherein the first output stage PNP transistor is replaced by an NPN transistor, the emitter of the NPN transistor serving as the first output stage and the second output stage NPN. A totem pole type output stage having a collector of the transistor as an output terminal, a first output stage NPN transistor and a second output stage N
An output circuit comprising a control circuit for inverting a PN transistor in an opposite state.