JP2998311B2 - Logic circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used for a circuit for improving the driving capability of a logic circuit. In particular, the output high-level potential (hereinafter, referred to as
Say "H". ) To an emitter follower circuit with an active pull-down circuit (hereinafter referred to as an APD circuit type logic circuit) for shortening the transition time from a low level potential (hereinafter referred to as “L”).

[0002]

2. Description of the Related Art FIG. 3 is a circuit diagram of a conventional logic circuit.

Conventionally, a logic circuit has an inverter circuit as shown in FIG.
And the operation as described below.

[0004] In FIG. 3, (usually is often used -1.1 V) reference potential terminal 2 to the base of the input terminal 1 of the transistor Q ₁ is connected to the base of the transistor Q ₂ from the "L" ( For example, about -1.4 V) when the input transistor Q ₁ is cut-off state (hereinafter, "off"
I say. ), And its collector potential rises to the ground potential, the output terminal 5 forward base-emitter voltage of the transistor Q ₃ from the potential (hereinafter, referred to as V _BEQ3.)
That is, a potential which is lowered by the amount of “H” (about −0.8 V). Here, when the input voltage is inverted from “L” to “H”, the transistor Q ₁ is turned on (hereinafter, referred to as “on”), and the transistor Q ₂ is turned “off”.
The collector potential of the transistor Q ₁ to the minus potential drop due to the ground potential and a resistor R ₁ constant current I ₁ and the potential (approximately -0.6 V), and the further V to the output terminal 5
A potential lower by _BEQ3, that is, "L" is generated.

As described above, the inverter circuit generates "H" at the output terminal 5 when the input terminal 1 is "L" and generates "L" at the output terminal 5 when the input terminal 1 is "H". ing.

Also, the transistor Q ₄ and the active transistor Q of the APD circuit (active pull town circuit)
_5, capacitor C ₁ and resistor R ₃ performs the following operation. The collector potential of by transitioning the transistor Q ₁ of the input terminal 1 potential to "H" from "L" transitions from "H" to "L", the output terminal 5 changes from "H" to "L".

[0007] At this time the transient charging current flows collector potential of the transistor Q ₂ is the base of the active transistor Q ₅ through capacitance C ₁ to transition from the "L" to "H", an active transistor Q ₅ "on"
Let it. Thereby increasing the discharge of the load capacitance C ₂ of the output terminal 5. That is, the circuit speeds up the transition time of the output from “H” to “L” (hereinafter referred to as t _PHL ).

The reference potential terminal 3 connected to the base of the transistor Q ₄ (usually, about -1.6 V is often used) and the resistor R ₃ are the base current of the active transistor Q ₅ in a steady state, that is for setting the emitter current, the discharge capacity of the load capacitance base current of the active transistor Q ₅ is greater increases.

[0009]

[SUMMARY OF THE INVENTION However, in the logic circuit of the conventional example, when the load capacitance of the output is reduced active transistor Q ₅ of the collector suction capacity (hereinafter,
It is called sink ability. ) Is large, the undershoot at the time of the transition of the output from “H” to “L” becomes large. As a result, the logic circuit of the next stage malfunctions or the output “L” becomes low.
However, there is a disadvantage that the transition time from "H" to "H" (hereinafter, referred to as _tPLH ) becomes long. Moreover, unnecessary current through the emitter follower transistor Q ₃ has a drawback that flows current consumption in the active transistor Q ₅ becomes larger by even the ground potential after the load capacitor has discharged all for this sink capacity is large.

SUMMARY OF THE INVENTION The present invention solves the above-mentioned drawbacks, and suppresses an undershoot at the time of transition from a high-level potential to a low-level potential of an output to prevent a malfunction of a next-stage logic circuit, and to reduce a low level of an output. It is an object to provide a logic circuit which can prevent an increase in transition time from a potential to a high-level potential.

[0011]

According to the present invention, there is provided an emitter follower circuit for outputting a current to an output terminal when the input potential rises, the emitter follower circuit including a load capacitor connected to the output terminal and the input. In a logic circuit including an active pull-down circuit that discharges the load capacitance when the potential falls, the emitter follower circuit includes a detecting unit that detects a fall of the potential of the output terminal, and a detecting unit that detects the falling of the potential of the output terminal. Control means for controlling the discharge of the active pull-down circuit based on the result.

Further, according to the present invention, the emitter follower circuit includes an emitter follower transistor having a base connected to the input potential, a collector connected to a ground terminal, and an emitter connected to the output terminal, and the output terminal is connected to a load. The active pull-down circuit is connected to a power supply terminal via a capacitor, the collector is connected to the ground terminal, the base is connected to a predetermined potential, and the emitter is connected to a potential falling at the rise of the input potential via a coupling capacitor. It may include a connected transistor and an active transistor having a base connected to the emitter of the transistor, a collector connected to the output terminal, and an emitter connected to the power supply terminal.

Further, according to the present invention, the detecting means includes a p-channel MOS transistor having a source connected to the ground terminal and a gate connected to the output terminal, and a source connected to the power supply terminal and a gate connected to the output terminal. And a first n-channel MOS transistor having a gate connected to the gate of the p-channel MOS transistor, the control means including a source connected to the power supply terminal and a gate connected to the drain of the p-channel MOS transistor. And a second n-channel MOS transistor having a drain connected to the base of the active transistor.

[0014]

The emitter follower circuit detects the fall of the potential of the output terminal by the detection means, and controls the discharge of the active follower circuit based on the detection result of the detection means by the control means.

As described above, undershoot at the time of transition of the output from the high-level potential to the low-level potential is suppressed to prevent a malfunction of the next-stage logic circuit, and the transition time of the output from the low-level potential to the high-level potential is reduced. An increase can be prevented.

[0016]

Embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram of a logic circuit according to one embodiment of the present invention.

In FIG. 1, the logic circuit includes an inverter circuit, which has an input terminal 1, a reference potential terminal 2, transistors Q ₁ and Q ₂ , a resistor R ₁ ,
And a R _2, transistors to Q ₁ is connected to a collector provided with an emitter follower circuit for outputting a current to the output terminal 5 to the rise of the potential of the input, the emitter follower circuit is the load capacitance C ₂ connected to the output terminal 5 and the potential of the input contains an active pull-down circuit which performs discharging of the load capacitance C ₂ when the fall of.

Here, it is a feature of the present invention that the emitter follower circuit includes a detecting means for detecting a fall of the potential of the output terminal 5 and a discharge of the active pull-down circuit based on a detection result of the detecting means. And control means for controlling.

The emitter follower circuit includes an emitter follower transistor Q ₃ having a base connected to the collector of the transistor Q _1, a collector connected to the ground terminal 4, and an emitter connected to the output terminal 5.
Is connected to a power supply terminal 6 via a load capacitor C ₂ , the active pull-down circuit has a collector connected to the ground terminal 4, a base connected to the reference potential terminal 3 having a specified potential, and an emitter connected to the collector of the transistor Q ₂ . Coupling capacity C ₁
A transistor Q ₄ which is connected via a base and an active transistor Q ₅ of the emitter collector connected to the emitter of the transistor Q ₄ is connected to the output terminal 5 is connected to the power supply terminal 6.

Further, the detecting means includes a p-channel MOS transistor P ₁ having a source connected to the ground terminal 4 and a gate connected to the output terminal 5, and a source connected to the power supply terminal 6 and a gate connected to the output terminal 5. n-channel MO as the first n-channel MOS transistor having a gate connected to the gate of the p-channel MOS transistor P ₁ is
S and a transistor N _2, a second n-channel and the control means for drain connected to the drain of the source gate connected to the power supply terminal 6 is p-channel MOS transistor P ₁ is connected to the base of the active transistor Q ₅ as MOS transistor and an n channel MOS transistor n _1.

The operation of the logic circuit having such a configuration will be described.

[0022] In FIG. 1, and it is different from the conventional circuit, the circuit connecting the n-channel MOS transistor N ₁ in place of the resistor R ₃ to determine the base-emitter potential of the active transistor Q ₅ is used, also, the output level detection circuit comprises p-channel MOS transistors P ₁ and n-channel MOS transistor n _2, both MOS
The gate of the transistor is connected to the output terminal 5, the source of the p-channel MOS transistor P ₁ is connected to the ground terminal 4, the source of the n-channel MOS transistor N ₂ is connected to the power supply terminal 6, the drain of the MOS transistor is active It is connected to the gate of n-channel MOS transistors n ₁ of the control circuit of the pull-down circuit.

[0023] Now, the output "H" for setting the input terminal 1 to the "L" transistor Q ₁ is to "off", p-channel output level detection circuit MOS transistors P ₁ and n-channel MOS transistor N ₁ The output of the inverter circuit composed of
Channel MOS transistor N ₂ has a base current comparable to the conventional APD circuit of an active transistor Q ₅ in the "off" state.

[0024] Now, the transistor Q ₂ If you set the input terminal 1 from "L" to "H" is made from "L" to "H",
Active transistor Q ₅ transient charging current flows to the base of the active transistor Q ₅ through capacitance C ₁
Is turned on. For this, the load capacitance C ₂ is discharged by the collector current of the active transistor Q _5,
The output terminal 5 changes from “H” to “L”. p-channel MO
Inverter output power level detection circuit constituted by S transistors P ₁ and n-channel MOS transistor N ₂ is "H" n-channel MOS transistor N ₁ is "on". Therefore, unnecessary active transistor Q _{5 is provided} by n-channel MOS transistor N _2.
The base drive transient current is extracted. The input terminal 1
Is changed from “H” to “L”, the same operation as the conventional circuit is performed.

FIG. 2 is a circuit diagram of a logic circuit according to another embodiment of the present invention. Example differs from Figure 1 by adding the active transistor Q ₆ in the active transistor Q ₅ to increase the transition time t _PHL "L" from "H" of the output, the current amplification factor by a common collector of the Darlington connection This is an example in which the present invention is applied to an APD circuit in which the driving capability with respect to the load is increased. Conventionally, in this type of circuit, when the output load capacity is small because the load driving capability is large (the sink capability is large), the undershoot at the time of the output transitioning from "H" to "L" is smaller than that of the circuit shown in FIG. Although there was a major problem, the present invention has solved this problem. Next, the operation of this circuit will be described. Active transistor Q ₂ flows transient charging current to the base of the active transistor Q ₅ through capacitance C ₁ of FIG. 2 to be "on" is the same as the logic circuit with the conventional APD circuit. Active transistor Q ₅ is "on" Then the active transistor Q
First with load capacitance C ₂ is discharged by ₅ of the collector current to drive the base of active transistor Q ₆ by its emitter current, to discharge the load capacitance C ₂ by the collector current of the active transistor Q _6. The operation of the output level detection circuit after the output terminal goes to "L" is shown in FIG.
And an unnecessary active transistor Q by n-channel MOS transistors N ₂ and N _3.
5, base drive transient current of Q ₆ is withdrawn. For example, the current source current I _CS = 0.2 mA, R ₁ = R ₂
= 4 kΩ, C ₁ = 50 pF, the transition time from “H” to “L” of the output is about 550 ps when the load capacitance C is 1 pF, and 800 ps when C ₂ = ₂ pF.
, And undershoot hardly occurs within 10 mV.

In this embodiment, the EC including the APD circuit is used.
Although the inverter circuit of the L circuit (emitter-coupled logic circuit) has been described, a similar effect can be obtained by a NOR circuit (a NOR circuit), and an APD circuit is also provided for an OR circuit (logical OR circuit). same effect by connecting a capacitor C ₁ to the signal output and the negative phase is obtained.

[0027]

As described above, the present invention suppresses the undershoot at the time of transition from the high-level potential of the output to the low-level potential, prevents the malfunction of the logic circuit of the next stage, and reduces the low level of the output. There is an excellent effect that the transition time from the potential to the high level potential can be prevented from increasing.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a logic circuit according to one embodiment of the present invention.

FIG. 2 is a circuit diagram of a logic circuit according to another embodiment of the present invention.

FIG. 3 is a circuit diagram of a conventional logic circuit.

[Explanation of symbols]

1 input terminal 2, 3 reference potential terminal 4 ground terminal 5 output terminal 6 power supply terminal C ₁ coupling capacitance C ₂ load capacitance N ₁ , N ₂ , N ₃ n-channel MOS transistor P ₁ p-channel MOS transistor Q ₁ , Q ₂ , Q ₄ transistor (NPN type) Q ₃ emitter follower transistor (NPN type) Q _5, Q ₆ active transistor (NPN _{type) R 1, R 2, R} 3 resistors

Claims (3)

(57) [Claims] 1. An emitter follower circuit for outputting a current to an output terminal when the input potential rises, wherein the emitter follower circuit detects a load capacitance connected to the output terminal and the input follower when the input potential falls. In a logic circuit including an active pull-down circuit for discharging a load capacitance, the emitter follower circuit includes a detection unit that detects a fall of the potential of the output terminal, and an active pull-down circuit based on a detection result of the detection unit. And a control means for controlling discharge. 2. The emitter follower circuit includes an emitter follower transistor having a base connected to the input potential, a collector connected to a ground terminal, and an emitter connected to the output terminal, and the output terminal connected via a load capacitor. The active pull-down circuit is connected to a power supply terminal, the collector is connected to the ground terminal, the base is connected to a predetermined potential, and the emitter is connected via a coupling capacitor to a potential falling at the rise of the input potential. 2. The logic circuit according to claim 1, further comprising: an active transistor having a base connected to the emitter of the transistor, a collector connected to the output terminal, and an emitter connected to the power supply terminal. 3. The detecting means includes a p-channel MOS transistor having a source connected to the ground terminal and a gate connected to the output terminal, and a gate having a source connected to the power supply terminal and a gate connected to the output terminal. Includes a first n-channel MOS transistor connected to the gate of the p-channel MOS transistor, and the control means includes a source connected to the power supply terminal, a gate connected to the drain of the p-channel MOS transistor, and a drain connected to the 2. The logic circuit according to claim 1, further comprising a second n-channel MOS transistor connected to a base of the active transistor.