JPH0685558A - Semiconductor device - Google Patents

Abstract

PURPOSE:To provide a bias circuit capable of self-controlling the fluctuation of a bias point even when the saturated drain current of an FET formed on a semi-insulated compound semiconductor substrate is dispersed. CONSTITUTION:One of gate side voltage dividing resistors is replaced with a sub FET (2) 10 formed on the same substrate as a main FET (1) 1, and the constant current characteristic of the FET 10 is utilized. On the other hand, the individual resistor or inductance of a high impedance is provided to prevent a high frequency signal from leaking into the bias circuit in the case of impressing this bias voltage to the main FET (1) 1. Thus, the fluctuation of the bias point caused by fluctuation in the pinch-off voltage of the FET (1) 1 can be relaxed, and the time of adjustment at a resistance dividing circuit can be shortened.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
The present invention relates to ET bias control, and more particularly to a bias circuit that self-adjusts a gate voltage so that a drain current becomes constant.

[0002]

2. Description of the Related Art FIG. 5 is a circuit showing a conventional high frequency signal amplifier circuit using a depletion type FET formed on a semi-insulating compound semiconductor substrate, in which the FET is biased by using a resistance dividing circuit. 6 and 6 are diagrams showing the locus of the bias point of the drain current due to the variation of the pinch-off voltage of the FET.

In the figure, 1 is a depletion type FET (1) which is a main FET for handling high frequency signals formed on a semi-insulating compound semiconductor substrate, and 2 is an FET (1).
1 is the load resistance RD on the drain side, 3 is the drain DC voltage VDD for FET (1) 1, 4 is the gate side bias resistance RG for FET (1) 1, 5 is the gate DC voltage for FET (1) 1. VGG, 6, 7 are voltage dividing resistors R1, for the gate DC voltage VGG
R2 and 8 are high frequency signal inputs RFin, and 9 is a high frequency signal output RFout.

Next, the operation will be described. As a semiconductor circuit using an FET that amplifies a high frequency signal, the source ground circuit of FIG. 5 is often used. Depletion type FET
FET (1) is made of a compound semiconductor and has a unique process, and recess current adjustment for etching the active layer is used to adjust the drain-source current ID1. Therefore, this recess current adjustment causes the pinch-off voltage Vt0 of the FET (1) 1 to fluctuate, resulting in a fluctuation in the saturated drain current. To determine the gate bias point of FET (1) 1, apply the drain DC voltage VDD3 to FET (1) 1,
At this time, in order to make the drain current ID1 flowing through the drain load resistor RD2 constant, the gate DC voltage VGG5
When the voltage is kept constant, the resistance ratio of the voltage dividing resistors R1, R2 6, 7 is adjusted, and the divided voltage is applied to the gate of the FET (1) 1 through the gate bias resistor 4RG so that the FET 1) Control the drain current ID1 of 1.

[0005]

Since the bias circuit in the conventional grounded source circuit for amplifying high-frequency signals is constructed as described above, the saturation drain current becomes IDDS1 of FIG. 6 due to the variation of the pinch-off voltage of the FET (1). , IDDS2,
When the voltage dividing signal by the voltage dividing resistors R1 and R2 is fixed and VGS1 is constant as in IDDS3, the bias point changes as shown in FIG. 6 and the voltage dividing ratio is changed at this bias point. When adjusting by this
It is necessary to examine the current characteristic of T (characteristic of FIG. 6), and there is a problem that adjustment takes time.

The present invention has been made to solve the above problems, and a high frequency signal amplification capable of automatically adjusting the variation of the bias point even if the saturation drain current of the main FET varies. The purpose is to obtain a bias circuit in the circuit.

[0007]

In the bias circuit according to the present invention, one of the gate side dividing resistors is replaced with a sub second FET formed on the same substrate as the main first FET, The gate bias point is self-adjusted by utilizing the constant current characteristic of the second FET. Further, in order to prevent the high frequency signal from leaking into the bias circuit when the bias voltage is applied to the main FET, a high impedance individual resistor or inductance or a series circuit of both of them is provided.

[0008]

In the bias circuit according to the present invention, since the sub FET is formed on the same substrate as the main depletion type FET on the semi-insulating compound semiconductor substrate, the bias circuit can be formed on the same substrate even if there are process variations. Since the variation of both FETs formed in the above is small and the saturation drain current of the main FET is proportional to the gate width of the sub FET, when the recess current of the main FET is small, the sub FET
Also the gate voltage of the main FET is made shallower and the bias point is moved in the direction of increasing the drain current, while when the recess current of the main FET is large, the gate voltage of the main FET is increased. Is deepened and the bias point is moved in the direction of decreasing the drain current, and thus the bias point can be automatically adjusted.

[0009]

EXAMPLES Example 1. An embodiment of the present invention will be described below with reference to the drawings. 1 shows the structure of a bias circuit according to an embodiment of the present invention. In FIG. 1, the same reference numerals as those in FIG. 5 designate the same or corresponding parts. 10 is the main FET (1)
This is a sub-FET (2) formed on the same substrate as the above, and its gate electrode and source electrode are connected to each other. This bias circuit replaces this with the resistor 7 of the resistance division circuit of FIG. It is used.

FIG. 2 shows the FET in this bias circuit.
Bias points VGS1, VGS2, of FET (1) when the saturation drain current of (1) varies with IDSS1, IDSS2, IDSS3
FIG. 3 shows the locus of VGS3, FIG. 3 shows the constant current characteristic (VDS2-ID2 characteristic) of the sub-FET (2) with a small gate width formed on the same substrate as the FET (1), and FIG. The drain current ID1 of the main FET (1) in the case of each of the resistance division circuit and the bias circuit with respect to the voltage VGG when the pinch-off voltage Vt0 = -3V, -2.5V, -2.0V is shown. There is.

Next, the operation of the bias circuit of the present invention will be described. The main FET (1) 1 in FIG. 1 has a gate width Wg.
Has 1. Sub FET with a small gate width on the same semi-insulating compound semiconductor substrate as this main FET (1) 1.
(2) Form 10. The FET (2) 10 has a structure in which the gate electrode and the source electrode are shared. And FET
When the gate widths Wg1 and Wg2 of (1) and the FET (2) are in a proportional relationship, the saturated drain currents of these FETs are also in a proportional relationship. If this property is used, FET (2) 1
The drain current ID2 of 0 can be expressed by the following equation.

[0012]

[Equation 1]

Here, ID1 is a drain current flowing through the FET (1) 1. The gate bias voltage of FET (1) 1 is

[0014]

[Equation 2]

The following relationship is obtained. Therefore, in the bias circuit of this embodiment, as shown in FIG.
When the saturation drain current of T (1) varies from IDSS1 to IDSS2 or IDSS3, the drain current of FET (1) decreases and the drain current of FET (2) also decreases and the gate bias of FET (1) decreases. VGS1 to VGS
2 shallow and VGS3 deep, resulting in FET
(1) The drain current IDS of 1 can be kept almost constant, or can be suppressed within a certain range.

FIG. 4 shows FET (1) 1 and FET
(2) The gate width of 10 is set to 50: 1, and the pinch-off voltage Vt0 of the FET is -2.5V.
ID1 when VGG is changed at V and -2.0V
Shows the change of. From this result, VGG = -5V (VDD is V
When the drain current is set with DD = 5V, the following Table 1
The result is as follows. From this, it is understood that the change of the bias point with respect to the change of Vt0 is significantly smaller in the present bias circuit than in the conventional case.

[0017]

[Table 1]

In this bias circuit, the high-frequency signal of the main FET (1) 1 is prevented from leaking with respect to the voltage obtained from the connection point of the sub FET (2) 10 and the resistor R1 (6). In order to prevent this, the two are connected via a gate resistor 4RG which is a high impedance resistor.

Example 2. In the second embodiment, the both are connected via a high impedance inductance instead of the high resistance 4RG.

Example 3. In the third embodiment, the both are connected via a series circuit of a high impedance inductance and a resistance.

[0021]

As described above, according to the bias circuit of the present invention, the main FET actually operating on the semi-insulating compound semiconductor substrate and the sub FET on the same substrate are used.
Since the gate bias point of the main FET can be self-adjusted by using the constant current characteristic, the fluctuation of the bias point due to the fluctuation of the pinch-off voltage of the main FET can be alleviated. This has the effect of shortening the time required for adjustment by the resistance division circuit.

[Brief description of drawings]

FIG. 1 is a diagram showing a circuit configuration of a bias circuit according to an embodiment of the present invention.

FIG. 2 is a diagram showing a locus of bias points according to an embodiment of the present invention.

FIG. 3 is a diagram showing a constant current characteristic of an FET (2) used in one embodiment of the present invention.

FIG. 4 is a diagram showing VGG dependence of a bias point by an embodiment of the present invention and a conventional resistance division circuit.

FIG. 5 is a diagram showing a configuration of a bias circuit using a conventional resistance division circuit.

FIG. 6 is a diagram showing a locus of bias points by a conventional resistance division circuit.

[Explanation of symbols]

1 FE which is a depletion type field effect transistor
T (1) 2 Drain side load resistance 3 Drain DC voltage 4 Gate side bias resistance 5 Gate DC voltage 6,7 VGG voltage dividing resistors R1, R2 8 High frequency input 9 High frequency output 10 FE which is a depletion type field effect transistor
T (2)

Claims (4)

[Claims] 1. A semiconductor device having a main first field effect transistor (hereinafter referred to as FET) for handling depletion type high frequency signals formed on a semi-insulating compound semiconductor substrate, wherein the same substrate is used. A second FET having a gate width different from that of the first FET is formed on the first FET, the gate electrode and the source electrode of the second FET are short-circuited, and a voltage source is connected to the second FET to form a constant current source. A resistor is connected between the drain electrode of the FET and the ground or another power supply potential, and the voltage at the connection point between the second FET and the resistor is applied to the gate electrode of the first FET to obtain the gate voltage. Is controlled to automatically adjust the bias point. 2. The connection point between the second FET serving as the constant current source and the resistor and the gate of the first FET are connected via a series circuit of a resistor and an inductor having high impedance. Claim 1 characterized in that
The semiconductor device described. 3. A connection point between the second FET serving as the constant current source and the resistor and a gate of the first FET are connected via only a high resistance. Item 1. The semiconductor device according to item 1. 4. The connection point between the second FET serving as the constant current source and the resistor and the gate of the first FET are connected only via an inductance having a high impedance. The semiconductor device according to claim 1.