JPH0685271A - Transistor - Google Patents

Abstract

PURPOSE:To maintain the sufficient surge voltage strength of a transistor while a fine chip structure is realized. CONSTITUTION:An unevenness is formed on one of the surfaces of a high impurity concentration N<+>-type substrate 109. An N<->-type epitaxial region 113 is formed on the uneven surface of the high impurity concentration N<+>-type substrate 109. P-type base regions 107 are formed inward from the surface of the N<->-type epitaxial region 113 so as to be brought into contact with the protrusions of the high impurity concentration N<->-type substrate 109. With this constitution, a long distance can be maintained between a diode 2 composed of the base region 107 and the N<->-type epitaxial region 113 and the recess of the high impurity concentration N<+>-type substrate 109, so that the breakdown strength of the diode D2 can be sufficiently higher than the breakdown strength of a diode D1 composed of the protrusion of the high impurity concentration N<+>-type substrate 109 and the base region 107.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transistor structure.

[0002]

2. Description of the Related Art As a conventional technique, for example, there is one shown in a sectional view of FIG.

A description will be given below with reference to FIG.

An N ⁻ type epitaxial region 513 is formed on a high concentration N ⁺ type substrate 509. From the surface of the N ⁻ type epitaxial region 513, the P type base region 507
And the P-type base region 50 deeper than the P-type base region 507
8 is formed, and the deep P type base region 508 is formed so as to be in contact with the high concentration N ⁺ type substrate 509. And a deep P type base region 508 and a high concentration N ⁺ type substrate 509.
The diode D1 is formed by and, and the P-type base region 507 is formed.
And the N ⁻ type epitaxial region 513 form a diode D2.
Are formed. A high concentration N ⁻ type source region 503 is formed in the P type base region 507.

Reference numeral 505 denotes a gate electrode, which is covered with an insulating film and is not in contact with any portion. 511 is a drain electrode, which is formed on the surface of the high concentration N ⁺ type substrate 509. A source electrode 501 is connected to the high concentration N ⁺ type source region 503 and the P type base region 507.

In this structure, the P-type base region 507 is used.
The junction breakdown voltage of the deep P type base region 508 and the high concentration N ⁺ type substrate 509 is lower than the junction breakdown voltage of the N ⁻ type epitaxial region 513. That is, the breakdown voltage of the diode D1 is lower than that of the diode D2.

Therefore, when a surge voltage occurs between the drain electrode 511 and the source electrode 501, the diode D1 breaks down prior to the diode D2 to pass an avalanche current, so that the N ⁻ type epitaxial region 513 and the P type The potential difference does not change between the base region 507 and the parasitic NPN transistor formed by the high-concentration N ⁺ type source region 503, the P type base region 507, and the N ⁻ type epitaxial region 513, and turns on. It can be prevented and surge resistance can be improved.

[0008]

SUMMARY OF THE INVENTION Such conventional MO
In the SFET, it is possible to reduce the distance between the gate electrodes in order to miniaturize the device. However, since the P-type base region 507 is formed by diffusing the implanted ions using the gate electrode 505 as a mask, the area where the ions are implanted becomes smaller as the distance between the gate electrodes is reduced.

As a result, the channel portion of the P-type base region 507 and the deep base region 508 overlap with each other, and the impurity concentration of this channel portion increases, resulting in the MOS.
Since the threshold voltage of the FET rises, it becomes impossible to control the threshold to a desired value. In order to control this threshold value to a desired value, it is conceivable to make the deep base region 508 not too deep so as to reduce the overlap between the P-type base region 507 and the deep base region 508. However, when the deep base region 508 is formed shallowly, the junction surface between the P-type base region 507 and the N ⁻ -type epitaxial region 513 approaches the high-concentration N ⁺ -type substrate 509, so that the breakdown voltage of the diode D2 decreases. Therefore, when a surge occurs, a surge current flows not only in the diode D1 but also in the diode D2, and the high concentration N
^{Since the} parasitic bipolar transistor including the ⁺ type source region 503, the P type base region 507, and the N ⁻ type epitaxial region 513 is turned on and latch-up occurs, the surge resistance is reduced. The present invention has been made to solve the above problems, and an object of the present invention is to provide a transistor having a sufficient surge withstanding capability even when miniaturized.

[0010]

In order to achieve the above object, the invention described in claim 1 has a first surface in which one surface is formed in an uneven shape and a drain electrode is formed in the other surface.
A first semiconductor region of a conductivity type, a second semiconductor region of a first conductivity type formed on the one surface of the first semiconductor region and having an impurity concentration lower than that of the electrical first semiconductor region; 2 a second conductivity type base region formed from the surface of the semiconductor region into the region and having a bottom portion in contact with the convex portion of the first semiconductor region; and a region formed from the surface of the base region into the region. A first conductivity type source region, a gate electrode formed on a surface of the base region sandwiched at least by the source region and the second semiconductor region via a gate insulating film, and electrically connected to the source region. A transistor was formed by the source electrode connected to.

[0011]

When a voltage is applied to the drain electrode and the gate electrode, a current flows from the drain electrode through the first semiconductor region, the second semiconductor region, the base region, the source region, and the source electrode. Flows.

When a surge voltage is generated between the drain electrode and the source electrode, the base region and the second electrode
The diode formed by the convex portion of the first semiconductor region, which has a sufficiently lower breakdown voltage than the diode formed by the semiconductor region, that is, the impurity concentration of the constituent region is high, and the base region breaks down. Therefore, since the avalanche current flows from the convex portion of the first semiconductor region to the source electrode through the base region, the second semiconductor region having a low impurity concentration, that is, a large electric resistance does not flow.

[0013]

1 is a sectional view of a first embodiment of the present invention.

A first embodiment will be described below with reference to the drawings. Reference numeral 109 is a high-concentration N ⁺ -type substrate as a first conductivity type first semiconductor region, and 113 is a high-concentration N ⁺ -type substrate 1.
On the other surface of the high-concentration N ⁺ -type substrate 109, which is the N ⁻ -type epitaxial region as the first-conductivity-type second semiconductor region formed on one surface of the drain electrode 1.
11 is formed. 107 denotes a second layer formed in the region 113 from the surface of the N ⁻ type epitaxial region 113.
This is a P ⁺ type base region as a conductivity type base region, and the base region 107 and the N ⁻ type epitaxial region 113 form a diode D2. 108
Is a N ⁺ type substrate 109 having a higher concentration than the surface of the base region 107.
Is a P ⁺ -type deep base region as a second conductivity type deep base region formed in contact with the convex portion of the diode D1 and the deep base region 108 and the high-concentration N ⁺ -type substrate 109 form the diode D1. ing. 103 is the base region 1
This is an N ⁺ type source region as a first conductivity type source region formed in the base region 107 from the surface of 07.
105 is a gate electrode covered with a gate insulating film,
Reference numeral 101 is a source electrode formed on the source region 103.

In this embodiment, the high concentration N ⁺ type substrate 1 is used.
09 is used as a mask to form a concave portion by etching, a concave portion is formed, and an N ⁻ -type element is epitaxially grown on the concave-convex surface of this high-concentration N ⁺ -type substrate 109, and finally, the concave-convex shape is formed. N ⁻ type epitaxial region 1 by lapping the upper surface of the epitaxial layer
13 is formed. Then, N ⁻ type epitaxial region 1
A predetermined portion of the surface 13 is masked and P ⁺ type ions are implanted and thermally diffused to reach the convex portion of the high concentration N ⁺ type substrate 109 to form the deep base region 108. Then N
^An oxide film serving as a gate insulating film is formed on the surface of the ⁻ type epitaxial region 113, and a gate electrode 105 is formed of polysilicon on the surface of the gate insulating film. After that, P ⁺ -type ions are implanted using the gate electrode as a mask and the base region 107 is formed by thermal diffusion. Next, the gate electrode 10
The source region 103 is formed using 5 as a part of the mask, and the source electrode 101 is formed.

In this embodiment, since the high-concentration N ⁺ type substrate 109 has a convex portion, this convex portion and the deep base region 1 are formed.
The diode D1 is formed by 08 and the base region 1
The diode D2 is formed by 07 and the N ⁻ type epitaxial region 113. Since the concave portion of the high-concentration N ⁺ type substrate 109 is formed in the portion where the PN junction between the base region 107 and the N ⁻ type epitaxial region 113 is formed, the base region 107 and the N ⁻ type epitaxial region 113 are formed. The distance from the joining portion to the base region 107 becomes long. Therefore, the breakdown voltage of the diode D2 becomes high. Therefore, since the threshold value is set to a desired value when miniaturized, the breakdown voltage of the diode D2 can be increased even if the deep base region 108 cannot be formed too deep.
When a surge is input, a surge current can be passed through D1 and the surge withstand capability can be improved.

FIG. 2 shows a sectional view of the second embodiment.

The same parts as those of the first embodiment shown in FIG. 1 are designated by the same reference numerals, and the description thereof will be omitted. In the second embodiment, the deep base region 10 in the first embodiment is used.
8 is formed so that the convex portion of the high-concentration N ⁺ type substrate 109 directly contacts the base region 107, and the diode D2 is formed by the P type base region 107 and the N ⁻ type epitaxial region 113. P-type base region 107
A diode D1 is formed by the high-concentration N ⁺ type substrate 109.

In the second embodiment, although the deep base region 108 in the first embodiment is not formed, the base region 107 is in contact with the N ^-- type epitaxial region 113 and the high concentration N ⁺ -type. Since the distance to the concave portion of the substrate 109 is large, the diode D1 and the diode D
The withstand voltage difference from 2 is sufficiently large.

Moreover, in the second embodiment, since the deep base region 108 is not formed, the threshold voltage of the MOSFET does not increase even if the distance between the gate electrodes is shortened. Also, there is an effect peculiar to this embodiment that further miniaturization becomes easier.

FIG. 3 shows a sectional view of the third embodiment.

The same parts as those of the first embodiment shown in FIG. 1 are designated by the same reference numerals, and the description thereof will be omitted. In the third embodiment, the high concentration N ⁺ type substrate 1 in the first embodiment is used.
The number of convex portions of 09 is increased, and a high concentration N ⁺ type region 301 is formed inside the surface of the N ⁻ type epitaxial region 113 above the increased convex portion 303.

In this embodiment, the surge withstand capability can be improved as in the first embodiment. Further, during normal operation, that is, when the MOSFET is turned on (turned on) and a current flows through the source / drain, the current increases from the convex portion 303 to the N ⁻ type epitaxial region 113 and the high concentration N ⁺ type region. 301, an N ⁻ type epitaxial region 113 between the high concentration N ⁺ type region 301 and the P type base region 107, a channel induced in the P type base region 107 directly below the gate electrode 105, and a source region 103. The high concentration N ⁺ type region 301 and the increased convex portion 303 are the N ⁻ type epitaxial region 113.
Since the resistance is smaller than that of the MOSFET, the distance passing through the high resistance portion in the path of the current flowing between the source and the drain when the MOSFET is turned on becomes short, so that the ON resistance can be reduced. effective.

In a high voltage power transistor,
The resistance of the epitaxial region may occupy 50% or more of the resistance of the entire power transistor, and this embodiment is particularly effective for reducing the on-resistance of the high breakdown voltage power transistor.

FIG. 4 shows a sectional view of the fourth embodiment.

The same parts as those of the first embodiment shown in FIG. 1 are designated by the same reference numerals, and the description thereof will be omitted.

[0027] In this embodiment, a flat high-concentration N ⁺ -type substrate 109 and the N ^- from the boundary portion between the type epitaxial region 113 N ^- into the interior -type epitaxial region 113, so as to reach into the deep base region 108, a high concentration An N ⁻ type buried region 401 is formed.

In the MOSFET of this embodiment, N ⁺ type ions are partially implanted into the surface of the high-concentration N ⁺ type substrate 109 to form N ^−.
-Type epitaxial region 113 in the process of epitaxial growth, the N ⁺ high concentration type ions by thermal diffusion N ⁺
A high-concentration N ⁺ -type buried region 401 is formed by spreading from the boundary between the mold substrate 109 and the N ⁻ -type epitaxial region 113 to the inside of the N ⁻ -type epitaxial region 113. After that, a predetermined portion of the surface of the N ⁻ type epitaxial region 113 is masked and P ⁺ type ions are implanted to thermally diffuse to reach the high concentration N ⁺ type buried region 401 to form the deep base region 108. Let Next, an oxide film to be a gate insulating film is formed on the surface of the N ⁻ type epitaxial region 113, and a gate electrode 105 is formed of polysilicon on the surface of this gate insulating film. After that, P-type ions are implanted using the gate electrode as a mask and the base region 107 is formed by thermal diffusion.
To form. Next, the source region 103 is formed using the gate electrode 105 as a part of the mask, and the source electrode 101 is formed.

In the present embodiment, in addition to the effect of improving the surge resistance, it is not necessary to form the convex portion of the high-concentration N ⁺ type substrate 109, so that the N ⁻ type epitaxial region 1 is formed.
Since the high-concentration N ⁺ type buried region 401 is formed at the same time as the formation of 13, the chip manufacturing process can be simplified and the manufacturing cost can be reduced, which is a unique effect of this embodiment.

..

As described above, according to the present invention, even when the device is miniaturized, the diode from the second semiconductor region and the base region to the first semiconductor region is formed. Since the distance can be increased, the surge resistance of the device can be sufficiently improved.

[Brief description of drawings]

FIG. 1 is a sectional view of a first embodiment.

FIG. 2 is a sectional view of a second embodiment.

FIG. 3 is a sectional view of a third embodiment.

FIG. 4 is a sectional view of a fourth embodiment.

FIG. 5 is a sectional view of a conventional MOS transistor.

[Explanation of symbols]

101 ... source electrode 103 ... source region 105 ... gate electrode 107 ... base region 109 ... high-concentration N ⁺ -type substrate 111 ... drain electrode 113 ... N ^- -type epitaxial region 301 ... high-concentration N ⁺ -type region 303 ... more convex portions 401 ... High-concentration N ⁺ type embedded region

Claims (1)

[Claims] 1. A first-conductivity-type first semiconductor region having one surface formed in an uneven shape and a drain electrode formed on the other surface, and an electric field formed on the one surface of the first semiconductor region. A second semiconductor region of the first conductivity type having an impurity concentration lower than that of the first semiconductor region, and a bottom portion formed from the surface of the second semiconductor region into the region and in contact with the convex portion of the first semiconductor region. A second conductive type base region formed as described above, a first conductive type source region formed in the region from the surface of the base region, and at least sandwiched between the source region and the second semiconductor region. A transistor comprising: a gate electrode formed on the surface of the base region via an insulating film; and a source electrode electrically connected to the source region.