JPH0684796A - Method for growing semiconductor crystal - Google Patents

Method for growing semiconductor crystal

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Publication number
JPH0684796A
JPH0684796A JP23791992A JP23791992A JPH0684796A JP H0684796 A JPH0684796 A JP H0684796A JP 23791992 A JP23791992 A JP 23791992A JP 23791992 A JP23791992 A JP 23791992A JP H0684796 A JPH0684796 A JP H0684796A
Authority
JP
Japan
Prior art keywords
substrate
group
crystal
plane
compound semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23791992A
Other languages
Japanese (ja)
Inventor
Takayoshi Anami
隆由 阿南
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP23791992A priority Critical patent/JPH0684796A/en
Publication of JPH0684796A publication Critical patent/JPH0684796A/en
Pending legal-status Critical Current

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  • Crystals, And After-Treatments Of Crystals (AREA)
  • Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)

Abstract

PURPOSE:To grow a high-quality crystal by suppressing the elimination of group V molecules during the course of molecular beam epitaxy of a III-V compound semiconductor. CONSTITUTION:In the title method by which a III-V compound crystal containing arsenic or phosphorus is grown on a compound semiconductor substrate having its plane orientation in (100) plane by molecular beam epitaxy the crystal is grown by using such a substrate that its plane orientation is inclined by 0.5 deg.-6 deg. in an arbitrary direction under a growing condition where the elimination of group V molecules occurs on the surface of a substrate having accurate plane orientation in (100) plane. On the surface having accurate plane orientation in (100) plane, a high-quality crystal in which the elimination of group V molecules hardly occurs can be obtained even under a growing condition where the surface morphology of the substrate becomes rough.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、化合物半導体の結晶成
長方法に関し、特に分子線エピタキシー法による結晶成
長方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a crystal growth method for a compound semiconductor, and more particularly to a crystal growth method by a molecular beam epitaxy method.

【0002】[0002]

【従来の技術】分子線エピタキシー法を用いた結晶成長
では、V 族分子、III 族原子を別々のリース源から供給
し、基板に照射している。この際、結晶の品質は、照射
されるV 族分子とIII 族原子の数の比であるV /III
比、並びに基板温度に大きく依存する。V 族分子の数が
少ないと、結晶のストイキオメトリーが保たれず、荒れ
た表面となる。この場合、V /III 比を大きくするとV
族の脱離が抑制されることはよく知られている(例え
ば、ジャーナル,オブ,アプライド・フィジクス,朝日
一,他1981年,52巻,2852ページ)。
2. Description of the Related Art In crystal growth using a molecular beam epitaxy method, group V molecules and group III atoms are supplied from separate leasing sources and irradiated onto a substrate. At this time, the crystal quality is V / III, which is the ratio of the number of irradiated group V molecules and group III atoms.
It depends largely on the ratio and the substrate temperature. When the number of group V molecules is small, the stoichiometry of the crystal is not maintained and the surface becomes rough. In this case, increasing the V / III ratio results in V
It is well known that the detachment of the tribe is suppressed (for example, Journal, Of, Applied Physics, Asahi K, et al., 1981, 52, 2852).

【0003】[0003]

【発明が解決しようとする課題】この従来の成長方法で
は、基板温度が高温では、必要となるV /III 比も非常
に大きくする必要がある。例えば、分子線エピタキシー
法を用いた選択成長では、SiO2 上と半導体上との間
に大きな結晶成長選択性が必須となるが、これには、高
温成長が必須であり、高V /III 比が必要となる(アプ
タイド・フィジクス・レター,1987年,51巻,1
512ページ,岡本 明,他)。しかし照射可能なV 族
分子数には装置構成上、上限がある為、高温成長の上限
は、このV族分子の脱離温度に制限される。このように
高温度で高品質の結晶を得ることには問題があった。
In this conventional growth method, the required V / III ratio must be made very large when the substrate temperature is high. For example, in the selective growth using the molecular beam epitaxy method, a large crystal growth selectivity between SiO 2 and a semiconductor is indispensable, but high temperature growth is indispensable for this, and a high V / III ratio is required. Is required (Aptide Physics Letter, 1987, Volume 51, 1
512 pages, Akira Okamoto, et al.). However, there is an upper limit on the number of group V molecules that can be irradiated due to the device configuration, so the upper limit of high temperature growth is limited by the desorption temperature of this group V molecule. Thus, there is a problem in obtaining high quality crystals at high temperature.

【0004】本発明の目的は、分子線エピタキシー法に
おいて高温でもV 族脱離の少ない高品質の化合物半導体
結晶成長を可能とする成長方法を提供することにある。
An object of the present invention is to provide a growth method capable of growing a high-quality compound semiconductor crystal with little group V elimination even at high temperatures in the molecular beam epitaxy method.

【0005】[0005]

【課題を解決するための手段】本発明による半導体結晶
成長方法は、化合物半導体基板上にIII −V 族化合物結
晶を分子線エピタキシー法により成長させる方法におい
て、正確な(100)面方位基板上でV 族脱離を生じる
成長条件下で、基板面方位が(100)面から任意方向
に0.5度〜6度の範囲で傾斜した基板を用いて成長す
ることに特徴がある。
A method for growing a semiconductor crystal according to the present invention is a method for growing a group III-V compound crystal on a compound semiconductor substrate by a molecular beam epitaxy method. It is characterized in that the growth is performed using a substrate whose substrate plane orientation is tilted in an arbitrary direction from the (100) plane within a range of 0.5 to 6 degrees under a growth condition that causes group V desorption.

【0006】[0006]

【実施例】次に本発明の実施例について図面を参照して
説明する。図1及び図2は、それぞれ、本発明名を用い
て成長した半導体結晶膜の表面モホロジーを示す顕微鏡
写真と、従来技術を用いて成長した半導体結晶膜の表面
モホロジーを示す顕微鏡写真である。図1の試料は、I
nP基板として(100)面方位で(111)A方向へ
2°傾斜させた基板を用い、また図2の従来例の試料は
正確に(100)面方位を有する基板を用いた。それぞ
れの基板は通常の表面化学エッチング後同じ基板ホルダ
ー上にInで固定し、分子線エピタキシャル成長装置に
導入後、InP結晶を1μm成長した。InP結晶の成
長は、ガスソース分子線エピタキシ法により、固定In
ソース及びフォスフィンをクラッキングセルで950℃
で分解したP2 分子を用いて行った。フォスフィン流量
は13sccm、基板温度は545℃,成長速度は、
0.4μm/hourであった。
Embodiments of the present invention will now be described with reference to the drawings. 1 and 2 are a micrograph showing a surface morphology of a semiconductor crystal film grown using the present invention name and a micrograph showing a surface morphology of a semiconductor crystal film grown using a conventional technique, respectively. The sample of FIG.
As the nP substrate, a substrate tilted by 2 ° in the (111) A direction in the (100) plane direction was used, and the sample of the conventional example in FIG. 2 was a substrate having an accurate (100) plane direction. Each substrate was fixed on the same substrate holder with In after ordinary surface chemical etching and introduced into a molecular beam epitaxial growth apparatus, and then an InP crystal was grown to 1 μm. The growth of the InP crystal is performed by using a gas source molecular beam epitaxy method to grow fixed In
Sauce and phosphine in cracking cell at 950 ℃
Was carried out using the P 2 molecule decomposed in step 1. The phosphine flow rate is 13 sccm, the substrate temperature is 545 ° C., and the growth rate is
It was 0.4 μm / hour.

【0007】図2の半導体結晶膜では、リン分子の脱離
によると見られる表面荒れが見られたが、図1の半導体
結晶膜では、そのような表面荒れは観察されず鏡面成長
であった。このように、正確に(100)面方位を有す
る基板への結晶成長ではV 族原子の脱けによる表面モホ
ロジー劣化が生じる成長条件下でも、本発明によれば、
表面モホロジーが鏡面である高品質エピタキシャル膜が
成長できることが明らかである。
In the semiconductor crystal film of FIG. 2, surface roughness which is considered to be due to desorption of phosphorus molecules was observed, but in the semiconductor crystal film of FIG. 1, such surface roughness was not observed and mirror surface growth was observed. . As described above, according to the present invention, even under the growth condition in which the surface morphology is deteriorated due to the elimination of the group V atom in the crystal growth on the substrate having the accurate (100) plane orientation,
It is clear that high quality epitaxial films with a mirror surface morphology can be grown.

【0008】本実施例では、InP基板上のInPを例
にとって説明を行ったが、基板はGaAs基板やInA
s基板であってもよいし、また、エピタキシャル成長膜
も、InPに限定されず、GaAs,InAs,InG
aAs,InAlAs等、砒素やリンを含むIII −V 族
化合物半導体であればよい。また成長方法は、ガスソー
ス分子線エピタキシー法に限らず固体ソース分子線エピ
タキシー法、ケミカルビームエピタキシー法等、分子線
エピタキシー法であればよい。また微傾斜角度も0.5
度から6度までの範囲で上記、高品質Tr膜の成長が可
能である。
In this embodiment, InP on the InP substrate has been described as an example, but the substrate is a GaAs substrate or InA.
The epitaxial growth film is not limited to InP, but may be GaAs, InAs, InG.
Any III-V group compound semiconductor containing arsenic or phosphorus such as aAs or InAlAs may be used. The growth method is not limited to the gas source molecular beam epitaxy method, and may be a molecular beam epitaxy method such as a solid source molecular beam epitaxy method or a chemical beam epitaxy method. In addition, the fine tilt angle is 0.5
The above high-quality Tr film can be grown in the range of 6 to 6 degrees.

【0009】[0009]

【発明の効果】以上説明したように本発明は、正確な
(100)面方位から0.5度から6度の範囲で傾斜し
た面方位の基板を用いることにより、III −V 族化合物
半導体成長において高い温度まで高品質な結晶を成長で
きる。
As described above, according to the present invention, by using a substrate having a plane orientation inclined in the range of 0.5 to 6 degrees from the accurate (100) plane orientation, III-V compound semiconductor growth is achieved. High quality crystals can be grown up to high temperature.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明による半導体結晶膜の表面モホロジーの
顕微鏡写真を示す図。
FIG. 1 is a view showing a microscope photograph of surface morphology of a semiconductor crystal film according to the present invention.

【図2】従来技術による半導体結晶膜の表面モホロジー
の顕微鏡写真を示す図。
FIG. 2 is a view showing a micrograph of a surface morphology of a semiconductor crystal film according to a conventional technique.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】III −V 族化合物半導体結晶を構成する元
素を原子あるいは分子の状態で化合物半導体基板表面に
供給して前記化合物半導体基板上に前記III−V 族化合
物半導体結晶を分子線エピタキシー法により成長させる
方法において、正確な(100)面方位基板上でV 族原
子が脱離を生じる成長条件下で、基板面方位が(10
0)面に対して任意方向に0.5度〜6度の範囲で傾斜
した、化合物半導体基板にIII 族およびV 族の原子ある
いは分子を供給することを特徴とする半導体結晶成長方
法。
1. An element constituting a III-V group compound semiconductor crystal is supplied to the surface of the compound semiconductor substrate in the form of an atom or a molecule, and the III-V group compound semiconductor crystal is placed on the compound semiconductor substrate by a molecular beam epitaxy method. In the method of growing by (10), the substrate plane orientation is (10)
(0) A method for growing a semiconductor crystal, which comprises supplying a group III or V group atom or molecule to a compound semiconductor substrate tilted in an arbitrary direction with respect to the (0) plane within a range of 0.5 to 6 degrees.
JP23791992A 1992-09-07 1992-09-07 Method for growing semiconductor crystal Pending JPH0684796A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23791992A JPH0684796A (en) 1992-09-07 1992-09-07 Method for growing semiconductor crystal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23791992A JPH0684796A (en) 1992-09-07 1992-09-07 Method for growing semiconductor crystal

Publications (1)

Publication Number Publication Date
JPH0684796A true JPH0684796A (en) 1994-03-25

Family

ID=17022396

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23791992A Pending JPH0684796A (en) 1992-09-07 1992-09-07 Method for growing semiconductor crystal

Country Status (1)

Country Link
JP (1) JPH0684796A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998044539A1 (en) * 1997-03-28 1998-10-08 Sharp Kabushiki Kaisha Method for manufacturing compound semiconductors

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998044539A1 (en) * 1997-03-28 1998-10-08 Sharp Kabushiki Kaisha Method for manufacturing compound semiconductors
US6358822B1 (en) 1997-03-28 2002-03-19 Sharp Kabushiki Kaisha Method of epitaxially growing III-V compound semiconductor containing nitrogen and at least another group V element utilizing MBE

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