JPH0684783A - Manufacture of semiconductor device and semiconductor manufacturing device used for it - Google Patents

Abstract

PURPOSE:To form a fine pattern with high dimensional accuracy by using a chemically amplified resist. CONSTITUTION:In the title manufacturing method, a developing process is performed after a baking process and catalyst inactivating process. In the catalyst inactivating process, a chemically amplified resist 2 is exposed to a basic atmosphere composed of HMDS, etc. As a result, a catalytic substance 3 is removed from the resist 2 or the function of the substance 3 as a catalyst disappears, because the substance 3 existing in the exposed and diffused parts 21 and 22 of the resist 2 are bonded to each other as a result of a neutralization reaction which occurs between them. In the manufacturing device 5 used for this method, in addition, a catalyst inactivating section 52 filled with the vapor of HMDS is provided in the semiconductor wafer 1 carrying route between a baking unit 50 and developing unit 51.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing technique and a technique particularly effective when applied to a lithography technique for forming a fine pattern with high dimensional accuracy. For example, a chemically amplified resist utilizing a catalytic reaction is used. The present invention relates to a technique useful when used to manufacture a highly integrated semiconductor device.

[0002]

2. Description of the Related Art In recent years, so-called chemical amplification having high sensitivity and excellent resolution performance has been achieved in a lithography technique for forming a fine pattern on a semiconductor wafer in order to further increase the integration of an LSI (Large Scale Integrated Circuit Device). It has been considered to use a type resist as a photosensitive film (“Preliminaly
Lithographic Characters of an All-organic
Chemically Amplified Resist Formation for S
ingle Layer Deep-UV Lithography "SPIE Vo
l.1466 (1991)). This chemically amplified resist mainly contains a resin, an acid generator and a dissolution controller. Then, H ⁺ is generated from the acid generator upon exposure, the baking treatment after the exposure work that H ⁺ is as a catalyst, solubility controller catalysis is promoted in the case of a negative form dissolution accelerating exposed portion Shows a dissolution inhibiting property, and in the case of a positive type, the dissolution inhibiting property of the exposed portion changes into a dissolution promoting property. By utilizing this property, a mask pattern such as a photomask is transferred onto a chemically amplified resist applied on a semiconductor wafer by exposure, and developed after baking treatment to form a predetermined pattern.

By the way, H ⁺ , which serves as a catalyst, immediately starts to diffuse from the exposed portion to the unexposed portion of the chemically amplified resist after the exposure is completed. Therefore, H ⁺ is also distributed in the vicinity of the boundary between the unexposed portion and the exposed portion, and during the baking treatment, the dissolution control agent in that portion undergoes a catalytic reaction to change from dissolution promoting property to dissolution inhibiting property (or dissolution inhibiting property). Change from sex to dissolution-promoting). Therefore, the H ⁺ diffusion region in the unexposed portion expands according to the standing time from the exposure to the baking process, that is, the time during which the H ⁺ can diffuse, and the boundary between the unexposed portion and the exposed portion is blurred, and the exposure immediately after the exposure is performed. A dimensional error occurs with respect to the size of the part. Therefore, conventionally, the baking process is performed within a time period in which the dimensional error during the baking process does not exceed the allowable range.

[0004]

However, the present inventors have clarified that the above-mentioned technique has the following problems. That is, H ⁺ diffuses to a wider range according to the second standing time after the baking treatment to the developing treatment, and since the H ⁺ is sufficiently active as a catalyst even at room temperature, even after the baking treatment. The catalyst reaction of the dissolution control agent occurs using H ⁺ as a catalyst, and the dimensional error becomes larger during the development process, which may deviate from the allowable range of the dimensional error.

The present invention has been made in view of the above circumstances, and uses a chemically amplified resist which utilizes a catalytic reaction,
A main object of the present invention is to provide a semiconductor device manufacturing method and a semiconductor device manufacturing apparatus used for the same, which enable formation of a fine pattern with high dimensional accuracy. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0006]

The typical ones of the inventions disclosed in the present application will be outlined below. That is, in the method for manufacturing a semiconductor device of the present invention, the chemically amplified resist is immediately removed from the HMDS (Hexamethyldis) after the baking process performed after the exposure process.
(ilazane) is provided with a catalytic deactivation treatment step of exposing to a basic atmosphere made of an amine-based substance, and by the catalytic deactivation treatment step, H ⁺ which is the catalytic substance generated in the chemically amplified resist is chemically amplified. It was configured to be removed from the resist or to lose its catalytic function. Further, in the semiconductor device manufacturing apparatus used in the above-described manufacturing method, a catalyst deactivation processing section is provided in the transfer path of the semiconductor wafer from the baking processing step to the development processing step, and the catalyst deactivation processing section has a catalyst deactivation processing section such as HMDS. It was constructed such that steam was introduced to make the inside of the catalyst deactivation section a basic atmosphere.

[0007]

According to the above means, by exposing the chemically amplified resist to a basic atmosphere in the catalytic deactivation processing step after the baking processing, H ⁺ which is active as a catalyst and a basic substance in the basic atmosphere are removed. During this period, a neutralization reaction occurs and H ⁺ is removed from the chemically amplified resist, or its function as a catalyst disappears and becomes inactive as a catalyst.
Therefore, after the catalyst deactivation treatment step, H ^{+ which} is active as a catalyst causing a dimensional error in the chemically amplified resist is generated.
Can no longer exist, and the occurrence of dimensional error from the catalyst deactivation processing step to the development processing step is prevented.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a method of manufacturing a semiconductor device and a semiconductor device manufacturing apparatus used therefor according to the present invention is shown in FIGS. 1 to 7 and described below. Among them, FIG. 1 is a process diagram of a method for manufacturing a semiconductor device, FIG. 2 is a vertical cross-sectional view of a semiconductor wafer in which a chemically amplified resist is deposited on the semiconductor wafer before the exposure process, and FIG. 3 is an exposure process. 4 is a vertical cross-sectional view of the semiconductor wafer after the baking process, FIG. 4 is a vertical cross-sectional view of the semiconductor wafer after the baking process, FIG. 5 is a vertical cross-sectional view of the semiconductor wafer after the catalytic deactivation process, and FIG. FIG. 7 is a schematic cross-sectional view of a semiconductor device manufacturing apparatus.

In the method of manufacturing a semiconductor device, when a desired resist pattern is formed by a lithographic technique, as shown in FIG. 1, after a baking treatment step performed after an exposure step, a catalyst inactivation treatment step is performed, and then a development treatment is performed. The process is performed.

The process will be described below with reference to FIGS. First, as shown in FIG. 2, a semiconductor wafer 1 (workpiece) is coated with a chemically amplified resist 2 (photosensitive material) by a spin coater (spinner) or the like. The chemically amplified resist 2 contains a resin, an acid generator and a dissolution control agent as main components, and H generated from the acid generator upon exposure.
^{The +} serves as the catalyst substance 3 (indicated by a circle in FIGS. 3 to 5) to accelerate the catalytic reaction of the dissolution control agent. By this catalytic reaction, the dissolution promoting property changes to the dissolution inhibiting property in the case of the negative type, and the dissolution inhibiting property changes to the dissolution promoting property in the case of the positive type. In the state of FIG. 2, since it is before exposure, the entire surface of the chemically amplified resist 2 is the unexposed portion 20, and the catalyst substance 3 is not generated in the chemically amplified resist 2 at all. In the following description, it is assumed that the chemically amplified resist 2 is a negative type.

Next, as shown in FIG. 3, by performing an exposure step of irradiating the chemically amplified resist 2 with an ultraviolet ray, an electron beam, a laser beam or the like using a photomask having a desired mask pattern, which is not particularly shown. , The catalytic substance 3 is generated on the exposed portion 21 of the chemically amplified resist 2 (for example, its width dimension is d). The catalytic substance 3 immediately starts to diffuse from the exposed portion 21 toward the unexposed portion 20 around the exposed portion 21. Needless to say, a pre-baking step of improving the adhesion of the chemically amplified resist 2 to the semiconductor wafer 1 is performed before the exposure step, if necessary.

Then, in order to promote the catalytic reaction using the catalyst substance 3 as a catalyst, a baking process is performed at a predetermined temperature and a predetermined processing time in an inert gas atmosphere. From this baking process and the exposure process before that to the baking process,
Further, as shown in FIG. 4, the catalyst substance 3 diffuses by the diffusion dimension Δd depending on the standing time to the development processing step,
A diffusion portion 22 is formed in the vicinity of the boundary between the unexposed portion 20 and the exposed portion 21. Both the diffused portion 22 and the exposed portion 21 are changed to the dissolution inhibiting property by the catalytic reaction. Therefore, the width dimension after the baking process is from d to d '.
It has changed to (d ′ = d + Δd + Δd). Here, it goes without saying that the leaving time is kept within the maximum allowable time and the baking processing condition is set so that the width dimension d ′ does not exceed the allowable error range for the appropriate width dimension. Nor.

After the baking process, in the catalyst deactivation process, the chemically amplified resist 2 is exposed to a basic atmosphere made of an amine-based substance such as HMDS. As a result, the catalyst substance 3 present in the exposed portion 21 and the diffusion portion 22 of the chemically amplified resist 2 and the amine group 4 of HMDS (indicated by a black circle in FIG. 5) cause a neutralization reaction and bond with each other to chemically The catalytic substance 3 is removed from the amplification type resist 2 or its function as a catalyst is lost, and the catalytic substance 3 becomes inactive as a catalyst. Therefore, the width dimension d ′ does not change until the subsequent development processing step. At this time, H is added so that the catalytic substance 3 in the chemically amplified resist 2 is completely neutralized.
Adjust the concentration of MDS appropriately. It should be noted that it is desirable to perform this catalyst deactivation treatment step immediately after the baking treatment step.

Finally, through a development process, a resist pattern having a width dimension d'is formed on the semiconductor wafer 1 as shown in FIG.

Next, a semiconductor device manufacturing apparatus (hereinafter simply referred to as a "manufacturing apparatus") which consistently performs the above-mentioned baking processing step, catalytic inactivation processing step, and development processing step will be described. It will be described based on 7. In this manufacturing apparatus 5, a catalyst deactivation processing section 52 is provided in a transfer path of the semiconductor wafer 1 between a bake unit 50 that performs the bake processing and post-bake processing after development and a developing unit 51 that performs the development processing. It is provided.

Liquid HMDS is fed to the catalyst deactivation processing section 52 via an air supply section 53 and a pipe 54 for guiding the HMDS vapor to the catalyst deactivation processing section 52 as shown by arrows A and B.
A closed container 55 containing 40 is connected for communication. An inert gas is fed into the liquid HMDS 40 from a high pressure gas cylinder 56 filled with an inert gas such as nitrogen gas through a pipe 57 as shown by an arrow C. Then, by bubbling the liquid HMDS 40 with this inert gas, the liquid HMDS 40 is vaporized and becomes vapor of HMDS. In addition, the catalyst deactivation processing unit 52
Is provided with an exhaust unit 58 that guides and discharges HMDS vapor as shown by arrows D and E. The catalyst deactivation processing section 52 is kept airtight at least with respect to the bake unit 50 so that vapor of HMDS does not leak to the bake unit 50. Then, in the conduit 54, a concentration adjusting unit 5 such as a flow rate adjusting valve or a pressure adjusting valve that adjusts the concentration of HMDS vapor in the catalyst deactivation processing unit 52.
9 is provided.

As described above in detail, according to the present embodiment, when the desired resist pattern is formed on the semiconductor wafer 1 by the lithographic technique using the chemically amplified resist 2, the baking process is performed after the exposure step. After the step and before the development step, the catalyst inactivation treatment step of exposing the chemically amplified resist 2 to a basic atmosphere such as HMDS is performed to remove the catalyst substance 3 from the chemically amplified resist 2, or Since the function as a catalyst is lost, it is possible to prevent a dimensional error from the catalyst deactivation processing step to the development processing step. Therefore, a fine pattern can be formed with high dimensional accuracy.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, H
Instead of MDS, TMSDEA (N-Trimethylsilyl
-Diethylamine) and BSA (N, O-Bis (trimethylsi)
lyl) -acetamide) and TMCS (Trimethyl chlorosila)
ne) or the like may be used. If the catalyst substance 3 is other than H ⁺ , a substance other than an amine-based substance may be used as long as the catalyst substance 3 can be neutralized. Further, the manufacturing apparatus 5 is not limited to the one in the above-described embodiment, and the chemically amplified resist 2 is provided between the bake unit 50 and the developing unit 51 in the HMD.
A catalyst deactivation processing section 52 that can be exposed to steam such as S
If it is provided, the configuration does not matter.

Further, when the baking unit 50 and the developing unit 51 are separate devices and the baking process and the developing process cannot be performed consistently, the semiconductor wafer 1 that has undergone the baking process is It may be stored in a wafer case 6 as shown in FIG. 8 and transferred to an apparatus for performing a developing process. The wafer case 6 is sealed by a lid 61 that covers the case body 60. Case body 60
The HM is placed under the storage unit 62 for storing the semiconductor wafer 1.
A reservoir 64 for containing liquid HMDS or the like through a semipermeable membrane 63 that allows vapor such as DS to pass but does not pass liquid HMDS or the like.
It is made of. In addition, the case body 60,
An injection part 65 for pouring liquid HMDS or the like into the storage part 64 is provided. The reference numeral 66 indicates a partition plate.

In the above description, the case where the invention made by the present inventor is mainly applied to the manufacturing technology of the semiconductor device which is the field of application in the background has been described, but the present invention is not limited thereto. For example, it can be used for the manufacture of a printed wiring board on which electronic parts are mounted, and other general processing by lithography using a chemically amplified resist.

[0021]

The effects obtained by the representative one of the inventions disclosed in the present application will be briefly described as follows. That is, when a desired resist pattern is formed on a semiconductor wafer by using a chemically amplified resist that utilizes a catalytic reaction, the catalyst inactivation treatment step performed after the baking treatment step changes the catalyst inactivation treatment step to the development treatment step. Since occurrence of dimensional error up to this point is prevented, a fine pattern can be formed with high dimensional accuracy.

[Brief description of drawings]

FIG. 1 is a process drawing of a method for manufacturing a semiconductor device according to an embodiment.

FIG. 2 is a vertical cross-sectional view of a semiconductor wafer in a state where a chemically amplified resist is deposited on the semiconductor wafer before the exposure step.

FIG. 3 is a vertical cross-sectional view of a semiconductor wafer after an exposure process.

FIG. 4 is a vertical cross-sectional view of the semiconductor wafer after the baking process.

FIG. 5 is a vertical cross-sectional view of a semiconductor wafer after a catalyst deactivation processing step.

FIG. 6 is a vertical cross-sectional view of a semiconductor wafer after a development processing step.

FIG. 7 is a schematic view of a semiconductor device manufacturing apparatus.

FIG. 8 is a perspective view in which a part of the wafer case is cut away.

[Explanation of symbols]

 1 Semiconductor Wafer (Workpiece) 2 Chemically Amplified Resist (Photosensitive Material) 3 Catalytic Substance 52 Catalytic Inactivity Treatment Section

Claims (3)

[Claims] 1. A photosensitive material deposited on a work piece is exposed to generate a catalytic substance in the photosensitive material, and a catalytic reaction using the catalytic substance as a catalyst is promoted by a baking treatment. After changing the property of the predetermined part of the photosensitive material, the unnecessary part of the photosensitive material is removed by the developing process to quickly form the predetermined pattern of the photosensitive material on the work piece after the baking process. A method of manufacturing a semiconductor device, comprising a catalyst deactivation treatment step capable of removing the catalyst substance from the photosensitive material or eliminating its function as a catalyst. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the catalyst inactivation treatment step is performed by exposing the photosensitive material to a basic atmosphere. 3. The catalyst inactivation treatment section in a basic atmosphere is provided in a part or all of a conveyance path of the work piece from the baking treatment step to the development treatment step. Apparatus for manufacturing a semiconductor device used in the method for manufacturing a semiconductor device according to claim 1.