JPH0684352A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To eliminate the need for an address decoder and to decrease the number of blowing times of fuse elements without increasing the number of driving elements. CONSTITUTION:Four pieces OR logics of AND logics are formed of current paths formed of transistors N18, N19/N18, N21/N20, N21/N20, N19 between nodes 11 and VSS nodes for controlling the activation of respective regular and spare word line selectors sW, sspW. The sW is activated if any one current path is established. The fuse element F18 or F19 or F20 or F21 is disposed between N18, N19 or N18, N21 or N20, N21 or N20, N19 forming each current path. The corresponding AND logic current path is turned off so that the sspW is activated at the time of the address assignment thereof if any of the corresponding F18 to F20 is blown.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit forming a redundant circuit of DRAM.

[0002]

2. Description of the Related Art Generally, in a DRAM, a spare word line is prepared, and when a regular word line fails,
It is considered that the spare word line can be substituted to maintain the function of the memory itself.

FIG. 7 shows a circuit configuration of a DRAM in which the spare word line is prepared.

In this figure, WL is a word line, spW
L is a spare word line, BL is a bit line, DR is a selector driver group that functions as a row address decoder, DC is a selector driver group that functions as a column address decoder, SW is a word line selector, SspW is a spare word line selector, and SB is It is a bit line selector. The drivers DR and DC decode the address signals A0 to A9,
The specified word line and bit line are driven by each selector.

When a failure occurs in any of the word lines WL, the word line in which the failure has occurred is replaced by the spare word line s.
The mode is switched to using one of the pWLs. For this switching, the driver of the word selector is provided with a redundant circuit.

FIG. 4 shows a circuit configuration of a selector driver having the redundant circuit.

In the figure, sW is a word line selector corresponding to one regular word line, sspW is a word line selector corresponding to one spare word line, and the word line selector sW is a node 11 having an "L" level. (Low level)
The spare word line selector sspW is activated when the node 11 is at "H" (high level).

P10 is a P-channel type MOS (hereinafter, referred to as a load element for precharging the node 11 to "H").
It is called PMOS. ) A transistor whose source is connected to the power supply potential Vcc and whose drain is connected to the node 11. A precharge signal 10 which becomes "L" during the precharge period is input to the gate of the transistor P10.

N10 to N13 are N-channel MOS (hereinafter, referred to as NMOS) transistors serving as driving elements for address response. The source of the transistor N10 is connected to the ground potential VSS, the drain thereof is connected to the node 11 through the fuse element F10, and the positive phase address signal A0 is inputted to the gate thereof. The source of the transistor N11 is connected to the ground potential VSS, and the drain thereof is the fuse element F11.
To the node 11, and the opposite phase address signal bar A0 is input to the same gate. The source of the transistor N12 is connected to the ground potential VSS, its drain is connected to the node 11 via the fuse element F12, and the positive phase address signal A1 is input to its gate. The source of the transistor N13 is connected to the ground potential, the drain is connected to the node 11 via the fuse element F13, and the anti-phase address signal bar A1 is input to the gate. The negative phase address signal bars A0 and A1 are such that the logic as the inversion level of the corresponding positive phase address signals A0 and A1 is established only during the memory operation (reading, writing (including refreshing and erasing)). . Therefore, the address signals A0 and A1 are set to "L" at the time of non-operation (that is, at the standby time), but at that time, the address signals A0 and A1 are not set to "H" and also "L". It is said that.

Next, the operation will be described. The cycle is
The node 11 is precharged and the address signal is waited for. The timing is as shown in FIG.

Therefore, in the standby state, "L" is input as the precharge signal 10 to the gate of the transistor P10, and at the same time, A0 = A1 = bar A0 = bar A1 = "L" to the gates of the transistors N10 to N13. "Is entered. As a result, the transistor P10 is turned on and the transistors N10 to N13 are turned off, so that the node 11 is precharged to "H". In this state, addressing is awaited.

Next, during the memory operation, "H" is input to the gate of the transistor P10, the supply of the power supply potential to the node 11 is cut off, and the address signals A0 and A are supplied.
The floating "H" is maintained at the node 11 until 0, A1 and A1 operate. Here, for example, when the address signals A0 and A1 become "H", the transistors N10 and N1
11 is turned on, the node 11 is discharged to "L", and the word line selector sw is activated. As a result, a predetermined word line is driven.

By the way, word line address signals A0,
When the word line selector sW is switched to use the spare word line selector sspW when a defect occurs at the address where A1 becomes "H", the fuse elements F10 and F12 are cut off. Then, even if the address signals A0 and A1 are "H", the current path to the ground potential Vss through the transistors N10 and N12 is cut off, and the gates of the transistors N11 and N13 are "L". Since the transistors N11 and N13 are also turned off because they are input, the node 11 holds "H", the word line selector sW is not activated, and the spare word line selector sspW is activated. It will be. As a result, the spare word line is used in place of the regular word line when an address is designated in which both the address signals A0 and A1 are "H". Therefore, as long as there is a spare word line even if a problem is found in the regular word line in tests etc.,
Can be used as memory.

However, when the word line selector is switched by this redundant circuit, 1 / fuse of the total number of fuse elements is used.
2, that is, in this case, two pieces must be cut, which is a problem in terms of production efficiency.

Therefore, conventionally, a circuit for driving a transistor for address signal response with a signal obtained by decoding an address signal has been devised.

FIG. 5 shows the structure of a semiconductor integrated circuit as an example.

The circuit shown in this figure includes a precharge transistor P10 similar to that shown in FIG.
The drive node 11 for W and sspW is precharged to "H".

N14 to N17 are N channel type MOS (NMOS) transistors for address response, and F.
14 to F17 are fuse elements, and these elements N14 to N17
17, F14 to F17 are elements N10 to N13 and F10 to F shown in FIG.
It is connected between node 11 and ground potential VSS in the same manner as 13.

L0 to L3 are logic gates which serve as address decoders, and perform AND operation respectively. The logic gate L0 has address inversion signals A0 and A1.
, The address inversion signal bar A0 and the address signal A1 are input to the logic gate L1, the address signal A0 and the address inversion signal bar A1 are input to the logic gate L2, and the address signals A0 and A1 are input to the logic gate L3. Has been entered. This gives (A0,
A1), (A0, bar A1), (bar A0, A1),
If any one of the combinations (bar A0, bar A1) is designated, the outputs B0 to B of the logic gates L0 to L3 are designated.
Any one of 3 becomes "H" and transistor N14 ~
Any one of N17 is turned on. As a result, the node 11 becomes "L" and the word line selector sw is activated.

In the case of this circuit, since one of the transistors N14 to N17 is activated for one address designation, disconnection is required when a defect occurs at any address. The fuse element may be any one of F14 to F17. For example, address signals A0 and A1
When there is a defect in the address where "H" is "H", only the transistor N17 is activated. Therefore, if only one fuse element F17 corresponding thereto is cut, the address signal A0, The regular word line selector sW is activated at the time of specifying the address where A1 or A0, A1 or A0, A1 becomes "H", but both address signals A0, A1 become "H". When the address is designated, the spare word line selector sspW is activated instead of the regular word line selector sW. Therefore, in the case of this circuit, it is possible to cut the number of the fuse elements by 1/4.

However, in the case of this circuit, the number of transistors used as drive elements increases as the logic gates L0 to L3 are added, and the pattern area of the redundant circuit in the chip increases. There is. By the way, one-stage logic gate has two inputs NAND.
2 PMOS transistors and 2 NMOS transistors, and 1 each of the PMOS and NMOS transistors of the inverter are required. Therefore, in the case of the circuit shown in FIG.
That is, a total of 24 transistors will be added with 12 MOSs.

From the viewpoint of the number of drive elements, the circuit shown in FIG. 4 is rather superior, and when the above-mentioned two types of conventional redundant circuits are adopted, either the pattern area area or the production efficiency must be sacrificed. Is not to be obtained.

[0023]

As described above, in the conventional redundant circuit, when the number of drive elements is to be suppressed, the number of fuse elements to be cut increases and the production efficiency deteriorates. If it is attempted to reduce the number of fuse elements to be cut, the number of drive elements is increased and the area area of the redundant circuit pattern in the chip is increased.
When adopting a redundant circuit of some kind, there is a problem that either the pattern area area or the production efficiency must be sacrificed.

The present invention has been made in view of the above problems of the prior art, and an object of the present invention is to reduce the number of cutting of fuse elements for one address without increasing the number of driving elements. It is to provide a semiconductor integrated circuit capable of performing

[0025]

In a semiconductor integrated circuit of the present invention, a load element connected between a power supply potential node and a first node for selectively activating a regular word line selector and a spare word line selector. And a first drive element connected between the first node and the second node,
A second node connected between the third node and the ground potential node
Drive element, a third drive element connected between the first node and the fourth node, and a fourth drive element connected between the fifth node and the ground potential node. A first fuse element connected between the second node and the third node, and a second fuse element connected between the second node and the fifth node A third fuse element connected between the fourth node and the fifth node, and a fourth fuse element connected between the fourth node and the third node It has and.

Further, the semiconductor integrated circuit of the present invention is the first
The first drive control means for giving the first drive element a first control signal for controlling the on / off of the drive element and the second control signal for controlling the on / off of the second drive element. A second drive control means for giving the second drive element and a third control signal for performing on / off control of the third drive element reciprocally with respect to the first drive element are given to the third drive element. Fourth drive control means and fourth drive control means for giving a fourth control signal for controlling ON / OFF of the fourth drive element reciprocally to the second drive element. And a configuration including

[0027]

According to the present invention, a current path formed by the first and second drive elements is provided between the first node controlling the activation of the regular and spare word line selectors and the ground potential node. Four paths: a current path formed by the first and fourth drive elements, a current path formed by the third and second drive elements, and a current path formed by the third and fourth drive elements O of four AND logic by the current path of
Since the R logic operation circuit is formed, the regular word line selector can be activated if any of the four current paths is established. Therefore, the redundant circuit has a logic as a decoder for obtaining four kinds of address designations by four driving elements.

Further, a fuse element is arranged between the drive elements forming each current path, and if each fuse element is cut, the corresponding AND logic current path is cut,
When addressing the address, the spare word line selector can be activated.

Therefore, the address signal decoder is not required, and the number of cutting of the fuse element for one address can be reduced without increasing the number of driving elements.

[0030]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows the configuration of a semiconductor integrated circuit according to the first embodiment of the present invention.

The circuit shown in this figure includes a precharge transistor P10 as in the above-mentioned conventional circuit, and the selector s
Node 11 which is the first node for W and sspW drives
Is precharged to "H".

Now, the redundant circuit is composed of four Ns serving as driving elements.
MOS transistors N18 to N21 and four fuse elements F
It has 18 to F21.

The drain of the transistor N18 is the node 1
1, the source is connected to the second node 12,
The address signal A0 is input to the gate. The drain of the transistor N19 has the third node 1
3, the source is connected to the node of the ground potential VSS, and the address signal A1 is input to the gate. The drain of the transistor N20 is the node 11
, The source is connected to the fourth node 14, and the address signal bar A0 is input to the gate. The drain of the transistor N21 is connected to the fifth node 15,
The source is connected to the node of the ground potential VSS, and the address signal bar A1 is input to the gate.

The fuse element F18 is a node 12 and a node 1.
3, the transistors N18 and N19 are turned on to form a current path of node 11 → transistor N18 → node 12 → fuse element F18 → node 13 → transistor N19 → ground potential. The fuse element F19 is connected between the node 12 and the node 15, and when the transistors N18 and N21 are turned on,
A current path of node 11 → transistor N18 → node 12 → fuse element F19 → node 15 → transistor N21 → ground potential is formed. The fuse element F20 is connected between the node 14 and the node 15, and when the transistors N20 and N21 are turned on, the node 11 →
A current path of transistor N20 → node 14 → fuse element F20 → node 15 → transistor N21 → ground potential is formed. The fuse element F21 is connected between the node 14 and the node 13, and includes the transistors N20 and N19.
Is turned on, a current path of node 11 → transistor N20 → node 14 → fuse element F21 → node 13 → transistor N19 → ground potential is formed. Corresponding fuse elements F18 to F21 are cut when the respective current paths are cut, but the cutting is performed by a laser.

Next, the operation will be described.

The operation cycle is to precharge the node 11 and wait for the address signal, which is the same as the conventional one.

First, in the standby state, the transistor P
At the same time as "L" is input to the gate of 10 as the precharge signal 10, A0 = A1 = bar A0 = bar A1 = "L" is input to the gates of the transistors N18 to N21. As a result, the transistor P10 is turned on and the transistors N18 to N21 are turned off, so that the node 11 is precharged to "H". In this state, addressing is awaited.

Next, during the memory operation, "H" is input to the gate of the transistor P10, the supply of the power supply potential Vcc to the node 11 is cut off, and the address signal A0, the bars A0, A1, and the bar A1 are changed. Floating “H” is maintained at the node 11 until it operates. Here, for example, when the address signals A0 and A1 become "H", the transistor N1
8, N19 are turned on, the node 11 is discharged to "L", and the word line selector sw is activated. As a result, a predetermined word line is driven.

By the way, the word line address signals A0,
When the word line selector sW is switched to the use of the spare word line selector sspW when a defect occurs at the address where A1 becomes "H", the fuse element F18 is cut. Then, even if the address signals A0 and A1 are "H", the transistors N20 and N21 are off and the current path from the node 11 to the ground potential Vss is cut off, so that the node 11 is held at "H". The Rukoto. Therefore, the regular word line selector sW is not activated, and the spare word line selector sspW is activated. As a result, the address signals A0, A1 or A0, A
1 or the regular word line selector sW is used when the address for which the bar A0, A1 is "H" is specified, but the spare word line is used when the address for the address signal A0, A1 is "H" is specified. sspW is a regular word line sW
It can be used as a memory as long as there is a spare word line even if a problem is found in the regular word line by a test or the like.

As described above, according to this embodiment, the regular,
A current path formed by the transistors N18 and N19 and a current path formed by the transistors N18 and N21 are provided between the node 11 for controlling the activation of the spare word line selectors sW and sspW and the node of the ground potential VSS. , And four current paths formed by the transistors N20 and N21 and four current paths formed by the transistors N20 and N19 form four AND logic OR logic operation circuits. If either of the current paths is established, the regular word line selector sW can be activated. Therefore, it is possible to have a logic as a decoder that obtains four kinds of address designations with four driving elements in the redundant circuit.

Further, the transistors N18, N19 or N18, N21 or N20, N21 or N forming each current path are formed.
A fuse element F18 or F19 or F20 or F21 is arranged between 20 and N19, and the corresponding fuse element F18 to
When F20 is cut, the AND logic current path is cut, and the spare word line selector sspW can be activated when addressing the address.

Therefore, the address signal decoder is not required, the number of transistors serving as drive elements is not increased, and the number of fuse element cuts is once for each address, which is 1/4 of the total number of fuse elements. Will be enough.

FIG. 2 shows the structure of a semiconductor integrated circuit according to the second embodiment of the present invention.

The one shown in this figure has a configuration in the case of three addresses. Therefore, in addition to the configuration shown in FIG. 1, the NMOS transistors N22 and N23 and the fuse element F
22 and F23.

The drain of the transistor N22 is the node 1
6, the source is connected to the node of the ground potential VSS, and the address signal A2 is input to the gate. The transistor N23 has a drain connected to the node 17, a source connected to the node of the ground potential VSS, and a gate to which the address signal bar A2 is input.

The fuse element F22 has nodes 11 and 1
When the transistor N22 is turned on, a current path of node 11 → fuse element F22 → node 16 → transistor N22 → ground potential VSS node is formed. The fuse element F23 is connected between the node 11 and the node 17, and when the transistor N23 is turned on, a current path of node 11 → fuse element F23 → node 17 → transistor N23 → ground potential VSS node is formed. There is.

The operation cycle of this circuit is to precharge the node 11 and wait for the address signal, which is the same as the conventional one.

In the memory operation, for example, when the address signals A0, A1 and A2 are "H", the transistors N18, N19 and N22 are turned on, the node 11 is discharged to "L" and the word line selector sW is activated. Be converted. As a result, a predetermined word line is driven.

By the way, the word line address signals A0,
When a defect occurs at an address where A1 and A2 become "H", the word line selector sW to the spare word line selector ssp
When switching to the use of W, the fuse elements F19 and F22 are cut. Then, the address signals A0 and A1
Even if the voltage goes to "H", the transistors N20 and N21 are turned off, so that the potential from the node 11 via the fuse F19 to the ground potential V
Since the current path to ss is cut off, the node 11 holds "H", and the current path from the node 11 to the ground potential Vss via the fuse F22 is cut off. Therefore, the regular word line selector sW is not activated, and the spare word line selector sspW is activated.

The redundant circuit of this embodiment corresponds to a combination of the circuit configuration shown in FIG. 1 and the circuit configuration shown in FIG.

When the configuration corresponding to three addresses is adopted based on the concept shown in FIG. 4, one address requires cutting of three fuses by 1/2 of six addresses. In contrast,
In the case of the present embodiment, it is sufficient to cut two fuses, and the number of times of cutting the fuse element for one address is reduced.

FIG. 3 shows the structure of a semiconductor integrated circuit according to the third embodiment of the present invention.

The circuit shown in this figure has a configuration for four addresses, and two circuit configurations shown in FIG. 1 are provided in parallel. In FIG. 3, transistors N18-N2
1, fuse elements F18 to F21, and nodes 12 to 15
, The symbols of the elements corresponding to each position are attached with ‘.

The address signal A2 is input to the gate of the transistor N18 ', the address signal A3 is input to the gate of the transistor N19', the address signal bar A2 is input to the gate of the transistor N20 ', and the address signal A2 of the transistor N21' is input. An address signal bar A3 is input to the gate.

Also in the circuit of this embodiment, the operation cycle is that the node 11 is precharged and the address signal is waited, which is the same as the conventional one.

Then, for example, the address signals A0 and A1
, A2, A3 have become "H". Then, the transistors N18, N19, N18 ', N19' are turned on, the node 11 is discharged, and the regular word line sW is discharged.
Is activated.

By the way, the address signals A0, A1, A2
, A3 is "H", the fuse element F18, F18 'is blown when a defect occurs.
As a result, even if the address signals A0 and A1 become "H", the transistors N20 and N21 are turned off, so that the fuse F
The current path from the node 11 to the ground potential Vss via 18 is cut off, and the node 11 holds "H".
Even if the address signals A2 and A3 are "H", the transistors N20 'and N21' are off, so the fuse F18
The current path from the node 11 to the ground potential Vss via ??? is cut off, and the node 11 holds "H".
Therefore, the regular word line selector sW is not activated, and the spare word line selector sspW is activated.

In the case of constructing the concept shown in FIG. 4 with respect to four addresses, one address requires cutting of four fuses by 1/2 of eight. On the other hand, in the case of the present embodiment, only two fuses need to be cut, and the number of cutting of fuse elements for one address can be reduced.

[0060]

As described above, according to the present invention, the first and second driving elements are provided between the first node controlling the activation of the regular and spare word line selectors and the ground potential node. A current path formed by the first and fourth drive elements, a current path formed by the third and second drive elements, and a current path formed by the third and fourth drive elements Since four OR logic operation circuits of AND logic are formed by the four current paths with the current path, the regular word line selector can be activated if any of the four current paths is established. , In the redundant circuit, it has a logic as a decoder that obtains four kinds of address designations with four driving elements.
A fuse element is arranged between the drive elements forming each current path. If each fuse element is cut, the corresponding AND logic current path is cut, and a spare word line selector is used for addressing the address. Since it can be activated, the address signal decoder is not required, and the number of times of cutting the fuse element for one address can be reduced without increasing the number of driving elements.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a semiconductor integrated circuit according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing the configuration of a semiconductor integrated circuit according to a second embodiment of the invention.

FIG. 3 is a block diagram showing the configuration of a semiconductor integrated circuit according to a third embodiment of the invention.

FIG. 4 is a block diagram showing a configuration of a semiconductor integrated circuit as an example of a conventional technique.

FIG. 5 is a block diagram showing the configuration of a semiconductor integrated circuit as another example of the conventional technique.

FIG. 6 is a timing chart showing the operation of the circuits shown in FIGS.

FIG. 7 is a block diagram showing a schematic configuration of a conventional DRAM with a spare word line.

[Explanation of symbols]

sW regular word line selector sspW spare word line selector A0 to A3, bar A0 to bar A3 address signal 10 precharge signal 11 first node 12, 12 'second node 13, 13' third node 14, 14 ' Fourth node 15, 15 'Fifth node P10 P-channel MOS transistor N18, N18' as load element N-channel M as first drive element
OS transistor N19, N19 'N-channel type M as second drive element
OS transistor N20, N20 'N-channel type M as a third driving element
OS transistor N21, N21 'N-channel type M as a fourth driving element
OS transistor F18 First fuse element F19 Second fuse element F20 Third fuse element F21 Fourth fuse element

Claims (2)

[Claims] 1. A load element connected between a power supply potential node and a first node; a first drive element connected between the first node and a second node; Second connected between the node of the
Drive element, a third drive element connected between the first node and the fourth node, and a fourth drive element connected between the fifth node and the ground potential node. A first fuse element connected between the second node and the third node, and a second fuse element connected between the second node and the fifth node A third fuse element connected between the fourth node and the fifth node, and a fourth fuse element connected between the fourth node and the third node A semiconductor integrated circuit comprising: 2. A first drive device for controlling ON / OFF of a first drive element.
Drive control means for applying the control signal of 1 to the first drive element, and second drive control for applying a second control signal for on / off control of the second drive element to the second drive element. Means, a third drive control means for applying to the third drive element a third control signal for performing on / off control of the third drive element reciprocally with respect to the first drive element, and a fourth 4. The semiconductor device according to claim 1, further comprising a fourth drive control means for applying to the fourth drive element a fourth control signal for performing on / off control of the drive element reciprocally with the second drive element. Integrated circuit.