JPH0684288A - Recording device - Google Patents

Abstract

PURPOSE:To generate a notch part and a pilot signal for holding a trancking state by a small-scale circuit in a magnetic recording device. CONSTITUTION:This device is provided with a filter 1 constituted of a binary/ multilevel conversion circuit 2 for filtering an input data group {ek} and outputting multilevel digital data {dk} provided with plural intermediate levels and a D/A converter 3 for converting the output of the binary/multilevel conversion circuit 2 to analog recording data d(t) and two frequency f1 and f2 components of the signals of the binary group to be recorded are changed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a recording device used in equipment for processing digital signals such as a digital VTR.

[0002]

2. Description of the Related Art In a magnetic recording device such as a VTR, a head is displaced from a track during reproduction, the head output is reduced, and errors increase, so that a normal screen cannot be reproduced. Therefore, it is necessary for the head to accurately follow the target track, that is, to stably maintain the tracking state of the head. Especially for home VTR
In order to perform recording for a long time, the track is narrowed, and it is required to more accurately maintain the head tracking state.

As a means for detecting the tracking deviation of the head, the pilot signal of each track is used to compare the crosstalk values of the pilot signals from the front and rear tracks to determine whether the head tracking is forward or backward. There is a means to detect whether there is a deviation.

Therefore, the recording signal is modulated at the time of recording so as to have the frequency characteristics of the three types of patterns of F0, F1, and F2 shown in FIG. In the F0 pattern, the frequency f1
And f2 have a small frequency component, that is, a notch portion. The F1 pattern has a frequency f1 and a portion having many frequency components, that is, a pilot signal, and a notch portion at a frequency f2. Frequency f1 in F2 pattern
Has a notch and has a pilot signal at frequency f2.

As shown in FIG. 11, the recording signal is modulated for each track so that the pattern becomes F0, F1, F0, F2 and recorded. During reproduction of the F0 pattern, due to the crosstalk of the pilot signals from the F1 and F2 patterns of the adjacent tracks, there are peaks at the frequency components f1 and f2. When the head deviates from the center of the F0 pattern and shifts to the F1 pattern side, the crosstalk of the pilot signal from the F1 pattern becomes larger than the crosstalk of the pilot signal from the F2 pattern, and as a result, the frequency component f1 of the reproduction signal becomes large. Therefore, the frequency component f2 becomes smaller. In this way, by comparing the frequency components of f1 and f2 of the reproduced signal in the case of the F0 pattern, the tracking deviation of the head can be detected and correct tracking can be realized.

Conventionally, such a frequency characteristic pattern of F0, F1 and F2 is performed by controlling the connection between 0 and 1 in the binary sequence to be recorded. This method will be described below. First, the input data is divided into n bits, a special bit of 0 is added to the beginning, the data is input to the precoder shown in FIG. 8 and precoded. Similarly, a special bit of 1 is added to the beginning of the input data sequence, input to the precoder, and precoded. The characteristic of the precoder is expressed by (Equation 1), which is used to perform the known partial response detection at the time of decoding, and the precoded data string when the special bit is 0 and the precode when the special bit is 1. By acting so that the odd-numbered bits of the data string are inverted and inserting a precoder, the change in characteristics such as frequency characteristics due to the addition of special bits is increased.

[0007]

[Equation 1]

Here, {ak} is a precoder input data series, and {bk} is a precoder output series. The frequency component of the notch part of the output of the precoder is extracted by the bandpass filter, and the frequency component of the notch part of the precoder output when the special bit is 0 is compared with the frequency component of the notch part of the precoder output when the special bit is 1. The notch part is generated in the output data sequence by using the precoder output with the smaller component as the output of the recording device.

In order to generate a pilot signal in the output data sequence, the DSV of each precoder output is used.
A pilot signal is generated in the output data sequence by selecting a precoder output that is more in agreement with the DSV of the pilot signal with (Digital Sum Variation) as a reference, as the output of the pilot generation unit. The DSV is 1 when the data is 1, and -1 when the data is 0, which is a value accumulated up to a certain time and represents a change in the average value (DC value) of the binary series of signals to be recorded. Therefore, by matching the increase / decrease period of the DSV with the period of the pilot signal, the pilot can be generated by the recording sequence itself.

FIG. 12 shows a block diagram of a conventional recording apparatus. In the input data, the bit 0 insertion circuit 35 inserts a special bit of 0 at the beginning of every fixed bit. The output is input to the precoder 37 and precoded. Similarly, the bit 1 insertion circuit 36 inserts a special bit, which is 1 at the beginning of every fixed bit, into the precoder 38 for precoding. The precoded data strings are input to the bandpass filters 40 and 43, respectively, and the frequency components of the notch part are output. The precoded data strings are input to the DSV calculation circuit 42, and the difference from the DSV of the reference pilot signal is output. The DSV of the reference pilot signal is the reference pilot signal DSV generation circuit 4
It is generated by 1. The difference between the frequency component of the notch portion which is the output of the band pass filters 40 and 43 and the DSV which is the output of the DSV calculation circuit 42 is input to the output selection circuit 44. In the output selection circuit 44, the sum of the square of the frequency component of the notch when the special bit is 0 and the square of the difference between the DSV of the reference pilot signal and the frequency component of the notch when the special bit is 1. The square and the sum of the squares of the differences between the DSVs of the reference pilot signal and the square are compared and the smaller one, that is, the one closer to the desired frequency distribution, is output as precoded data.

[0011]

However, it is known that the means for extracting the frequency component of the data string by the conventional bandpass filter as described above must perform a large number of multiplications and additions. Further, in order to operate such a circuit at high speed, the circuit scale is unavoidably large, which is a serious problem in practical use.

An object of the present invention is to solve the above-mentioned conventional problems and to provide a recording apparatus for generating a notch portion and a pilot signal with a small circuit scale.

[0013]

In order to achieve the above object, the present invention has two frequencies f of a binary series signal to be recorded.
The configuration is provided with a filtering unit that changes the one component and the f2 component.

[0014]

According to the present invention, in the above configuration, the components of the two frequencies f1 and f2 of the input binary series data are changed and output as multi-valued data.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a first embodiment of the present invention. The filter 1 shown in FIG. 1 is a recording waveform d (t) for filtering the input data series {ek} and recording it on the tape.
To have the frequency characteristics shown in FIG. Binary /
The multi-value conversion circuit 2 inputs the input data sequence {ek} as shown in FIG. 3A, and has the multi-value digital as shown in FIG. 3B having a plurality of intermediate levels having the frequency characteristic of FIG. The data {dk} is output. The D / A converter 3 can output a recording waveform having the frequency characteristic of FIG. 2 by converting multivalued digital data into an analog recording waveform.

Next, the case where the binary / multi-value conversion circuit is configured by a digital filter will be described. FIG. 4 shows this block diagram. The recording data string is a binary / multivalue conversion circuit 2
And is delayed by the delay circuit 10. The outputs of the delay circuit 10 are respectively multiplied by the multiplier 11,
The output of the multiplier 11 is added by the output adder 12,
The data is D / A converted by the D / A converter 3 and becomes an output data series. The binary / multi-value conversion circuit 2 is realized by superimposing the impulse response of FIG. 5 obtained by inverse Fourier transform of the frequency spectrum of FIG. 2 for each bit clock. From this, the constant of the multiplier can be obtained from the impulse response of FIG.

The output of the binary / multi-value conversion circuit 2 is uniquely determined by the state of the delay circuit 10 as shown in (Equation 2).

[0018]

[Equation 2]

Therefore, instead of the multiplier 11 and the output adder 12, even if the operation output is calculated in advance and the state of the delay circuit 10 is used as an input and only the operation result is output, a binary / multivalue conversion circuit is provided. It holds. A block diagram when a ROM is used as an example of this circuit is shown in FIG. ROM
The recording data string input to the binary / multilevel circuit 2 configured by 16 is input to the delay circuit 10. This delay circuit 10
Is input as the address of the ROM 16. The data to be output is calculated in advance and stored in the ROM 16. The data output from the ROM 16 is D / A converted by the D / A converter 2 and output. The binary / multi-value conversion circuit 2 configured by using this ROM is equivalent to the binary / multi-value conversion circuit configured by using a digital filter, and can be realized by a high-speed and small-scale circuit.

In the first embodiment, the filter generates the notch and the pilot signal. In the second embodiment, bits of 0 and 1 called special bits are added to the beginning of every fixed bit, and precoding is applied to the data string to which the respective special bits are added. The DSV of the data string to which each special bit is added is calculated, and each DSV is calculated.
Is compared with the DSV of the reference pilot signal to select the precoded data sequence closer to the DSV of the reference pilot signal to generate the pilot signal,
The notch filter and the pilot signal are generated by inputting the output of the pilot signal generator to the notch filter.

A block diagram of the method according to this configuration is shown in FIG. The input recording data string is used for the pilot generation unit 2
9 is input. The bit 0 insertion circuit 20 (bit 0 insertion means) inserts a bit 0 at the beginning of each fixed bit in the recording data string input to the pilot generator 29. Similarly, in the recording data sequence input to the pilot generation unit 29, the bit 1 insertion circuit 21 (bit 1 insertion means) inserts a bit 1 at the beginning of every constant bit, and the data sequence in which each bit is inserted is Precoded by the precoders 22 and 23. Precoder 2
The configurations of Nos. 2 and 23 are shown in FIG. Each precoder 2
The outputs of 2 and 23 are the DSV0 calculation circuit 24 (DS
The DSV is calculated by the V0 calculating means) and the DSV1 calculating circuit 26 (DSV1 calculating means).

On the other hand, the reference pilot signal DSV generating circuit 25 (reference pilot signal DSV generating means) generates the DSV of the reference pilot signal. The output of the DSV0 calculation circuit 24 and the DSV1 calculation circuit 26 and the output of the reference pilot signal DSV generation circuit 25 are the output signal selection circuit 27.
It is input to the (output selection means) and is input to the DSV calculation circuits 24 and 2.
The output signal selection circuit 27 selects and outputs the precoded data string having the smaller absolute value of the difference between the respective outputs of 6 and the DSV of the reference pilot signal. In this way, a pilot signal is generated in the recording data string. Then, the notch part is generated by inputting the output of the pilot generation part 29 to the notch filter 28 having the frequency characteristic as shown in FIG. As described above, since the pilot signal can be generated only by controlling the DSV, the notch filter can be simplified in structure by separating the generation of the pilot signal from the filter and generating only the notch portion in the filter.

The notch filter can also be constructed by the filter of the first embodiment.

[0024]

As described above, according to the recording apparatus of the present invention, two frequencies f1 component and f of the binary series signal to be recorded are recorded.
By providing a filtering means for changing the two components, it is possible to suppress an increase in circuit scale with a simple circuit, generate notches and pilot signals, and use a home digital recorder that requires a narrow track for long-term recording. VTR
It has a great effect when used for such purposes.

[Brief description of drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention.

FIG. 2 is a frequency characteristic diagram of the notch part and the pilot signal.

FIG. 3 (a) is an input waveform diagram of the same binary / multi-value conversion circuit. (B) is an output waveform diagram of the same binary / multi-value conversion circuit.

FIG. 4 is a block diagram of a recording device configured using the digital filter.

FIG. 5 is an impulse response characteristic diagram of the filter.

FIG. 6 is a block diagram of a recording device configured using the ROM.

FIG. 7 is a block diagram of a recording apparatus having a configuration in which a pilot generation unit and a notch generation unit of the second embodiment are separated.

FIG. 8 is a block diagram of a precoder common to the present invention and a conventional example.

FIG. 9 is a frequency characteristic diagram of the notch filter of the present invention.

FIG. 10 is a frequency characteristic diagram of a recording waveform common to the present invention and the conventional example.

FIG. 11 is a track pattern diagram of the same recording waveform.

FIG. 12 is a block diagram of a conventional recording device.

[Explanation of symbols]

 1 Filter 2 2-value / multi-value conversion circuit 3 D / A converter 10 Delay circuit 11 Multiplier 12 Adder 20 Bit 0 insertion circuit 21 Bit 1 insertion circuit 22, 23 Precoder 24 DSV0 calculation circuit 25 Reference pilot signal DSV generation circuit 26 DSV1 calculation circuit 27 output signal selection circuit 28 notch filter 29 pilot generation unit

Claims (2)

[Claims] 1. A recording apparatus comprising a filtering means for changing two frequencies f1 and f2 of a binary series signal to be recorded. 2. The filtering means includes a bit 0 inserting means for inserting bit 0 into a binary series signal to be recorded, a bit 1 inserting means for inserting bit 1 into the binary series signal, and a bit 0 inserting means. D to calculate the output DSV
SV0 calculating means and DS of the output of the bit 1 inserting means
The DSV1 calculating means for calculating V, the reference pilot signal DSV generating means for generating the DSV of the reference pilot signal, the output of the DSV0 calculating means, the output of the DSV1 calculating means and the output of the pilot DSV generating means are compared, and the bit 2. The recording according to claim 1, further comprising: output selecting means for selecting and outputting the output of the 0 inserting means and the output of the bit 1 inserting means, and a notch filter for forming a notch portion in the output of the output selecting means. apparatus.