JPH0682774B2 - Semiconductor package - Google Patents
Semiconductor packageInfo
- Publication number
- JPH0682774B2 JPH0682774B2 JP31224487A JP31224487A JPH0682774B2 JP H0682774 B2 JPH0682774 B2 JP H0682774B2 JP 31224487 A JP31224487 A JP 31224487A JP 31224487 A JP31224487 A JP 31224487A JP H0682774 B2 JPH0682774 B2 JP H0682774B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- mounting portion
- leads
- lead
- metal wire
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体素子を搭載するリードフレームを改善し
たパッケージに関する。TECHNICAL FIELD The present invention relates to a package having an improved lead frame on which a semiconductor element is mounted.
従来、半導体パッケージを構成する場合には、導電性材
料からなるリードフレームに半導体素子を搭載し、かつ
その複数本のリードに電気接続を行った上で、これらを
樹脂等で封止する構造がとられている。例えば、第６図
及び第７図はその一例であり、リードフレーム21は略中
央に配設した半導体素子搭載部22とこの周囲に配設した
複数本のリード23を有し、この半導体素子搭載部22上に
半導体素子10をマウント用ロー材12によって搭載し、か
つ半導体素子10上の電極と前記リード23とをボンディン
グ用金属線11によって電気接続している。Conventionally, in the case of forming a semiconductor package, a structure has been adopted in which a semiconductor element is mounted on a lead frame made of a conductive material, and the leads are electrically connected, and then these are sealed with a resin or the like. It is taken. For example, FIG. 6 and FIG. 7 are examples thereof, and the lead frame 21 has a semiconductor element mounting portion 22 arranged substantially in the center and a plurality of leads 23 arranged around the semiconductor element mounting portion 22. The semiconductor element 10 is mounted on the portion 22 by the mounting brazing material 12, and the electrode on the semiconductor element 10 and the lead 23 are electrically connected by the bonding metal wire 11.
上述した従来の半導体パッケージは、半導体素子搭載部
22を種々の半導体素子に対応し得るように所要以上の寸
法に形成しているため、第６図に示すように面積の小さ
い半導体素子10を半導体素子搭載部22に搭載した場合に
は、リード23との電気接続を行うボンディング用金属線
11の線長が必要以上に長くなる。このため、この金属線
11によるリードインダクタンスが大きくなって高周波特
性が悪化し、或いは金属線11の撓みにより短絡事故が生
じて信頼性が低下されるという問題がある。The conventional semiconductor package described above has a semiconductor element mounting portion.
Since 22 is formed to have a size larger than required so as to be compatible with various semiconductor elements, when the semiconductor element 10 having a small area is mounted on the semiconductor element mounting portion 22 as shown in FIG. Bonding metal wire for electrical connection with 23
The line length of 11 becomes longer than necessary. For this reason, this metal wire
There is a problem that the lead inductance due to 11 increases and the high frequency characteristic deteriorates, or the bending of the metal wire 11 causes a short circuit accident and the reliability decreases.
本発明は高周波特性を改善し、かつ信頼性を向上するこ
とができる半導体パッケージを提供することを目的とし
ている。It is an object of the present invention to provide a semiconductor package which can improve high frequency characteristics and reliability.
本発明の半導体パッケージは、リードフレームの半導体
素子搭載部及びこの周囲に配設した複数本のリードに夫
々空洞部を設け、これら空洞部内には前記半導体素子搭
載部及びリードを夫々電気的接触を保持した状態で引き
出し或いは収納可能に導電性の平板を挿入し、この平板
を素子の搭載或いは金属線の接続、更には搭載部とリー
ドとの直接的な接続を行うように構成している。In the semiconductor package of the present invention, a cavity is provided in each of the semiconductor element mounting portion of the lead frame and a plurality of leads arranged around the semiconductor element mounting portion, and the semiconductor element mounting portion and the leads are electrically contacted in the cavity. A conductive flat plate is inserted so that it can be pulled out or stored in the state of being held, and this flat plate is configured to mount an element or connect a metal wire, and further to directly connect the mount portion and the lead.
次に、本発明を図面を参照して説明する。 Next, the present invention will be described with reference to the drawings.
（第１実施例） 第１図は本発明の第１実施例の平面図、第２図はそのAA
線に沿う断面図である。リードフレーム１は略中央に配
設した半導体素子搭載部２と、その周囲に配設した複数
本のリード３とで構成される。ここで、前記半導体素子
搭載部２は可及的に小さい面積に形成し、かつ一部のリ
ード３はこの搭載部２から若干離した位置に先端部を配
設している。(First Embodiment) FIG. 1 is a plan view of the first embodiment of the present invention, and FIG. 2 is its AA.
It is sectional drawing which follows the line. The lead frame 1 is composed of a semiconductor element mounting portion 2 arranged substantially in the center and a plurality of leads 3 arranged around the semiconductor element mounting portion 2. Here, the semiconductor element mounting portion 2 is formed in an area as small as possible, and a part of the leads 3 is provided with a tip portion at a position slightly separated from the mounting portion 2.
そして、前記半導体素子搭載部２の両側部と一部のリー
ド３の先端部には夫々板厚方向の中間に空洞部2a,3aを
形成し、この空洞部2a,3a内に前記半導体素子搭載部２
及びリード３と同一材質の平板4,5を各々挿入してい
る。この平板4,5は夫々半導体素子搭載部2,リード３と
電気的に接触しており、かつこの接触状態を保持したま
まで空洞部内から引き出し、或いは空洞内に収納させる
ことができる。Then, cavities 2a and 3a are formed at both sides of the semiconductor element mounting portion 2 and the tips of some of the leads 3 in the middle in the plate thickness direction, and the semiconductor element mounting portion is placed in the cavities 2a and 3a. Part 2
Also, flat plates 4 and 5 made of the same material as the lead 3 are inserted. The flat plates 4 and 5 are in electrical contact with the semiconductor element mounting portion 2 and the leads 3, respectively, and can be pulled out from the hollow portion or housed in the hollow portion while maintaining this contact state.
この構成のリードフレームによれば、例えば搭載する半
導体素子10の面積が小さい場合には、第２図のように半
導体素子搭載部２の空洞部2a内の平板４を空洞部内に収
納させた状態で半導体素子10をマウント用ロー材12でマ
ウントする。また、リード３の空洞部3a内の平板５は空
洞部から引き出して半導体素子搭載部２に近接させ、こ
の平板５と半導体素子10上の電極とをボンディング用金
属線11で電気接続する。これにより、ボンディング用金
属線11長を短くでき、リードインダクタンスの低減化を
図って高周波特性を改善し、かつ金属線の短絡を防止し
て信頼性を向上できる。According to the lead frame having this configuration, for example, when the area of the semiconductor element 10 to be mounted is small, the flat plate 4 in the cavity 2a of the semiconductor element mounting portion 2 is housed in the cavity as shown in FIG. The semiconductor element 10 is mounted with the mounting brazing material 12. Further, the flat plate 5 in the hollow portion 3a of the lead 3 is pulled out from the hollow portion and brought close to the semiconductor element mounting portion 2, and the flat plate 5 and the electrode on the semiconductor element 10 are electrically connected by the bonding metal wire 11. As a result, the length of the bonding metal wire 11 can be shortened, the lead inductance can be reduced, the high frequency characteristics can be improved, and the short circuit of the metal wire can be prevented to improve the reliability.
一方、搭載する半導体素子10の面積が大きい場合には、
第３図に第２図と同様の断面構造を示すように、平板４
を半導体素子搭載部２の空洞部2aから引き出し、この平
板４を利用して半導体素子10の搭載を行う。このとき、
リード３の平板５は空洞部内に収納させ、金属線11はリ
ード３に接続させる。この状態でも、金属線11の長さを
短くでき、特性の改善及び信頼性を向上できる。On the other hand, when the area of the mounted semiconductor element 10 is large,
As shown in FIG. 3 which is a sectional structure similar to that shown in FIG.
Is pulled out from the cavity 2a of the semiconductor element mounting portion 2 and the semiconductor element 10 is mounted using this flat plate 4. At this time,
The flat plate 5 of the lead 3 is housed in the cavity, and the metal wire 11 is connected to the lead 3. Even in this state, the length of the metal wire 11 can be shortened, and the characteristics and reliability can be improved.
（第２実施例） 第４図は本発明の第２実施例の平面図、第５図はそのBB
線に沿う断面図であり、第１図乃至第３図と同一部分に
は同一符号を付してある。(Second Embodiment) FIG. 4 is a plan view of a second embodiment of the present invention, and FIG. 5 is its BB.
It is sectional drawing which follows the line, and attaches | subjects the same code | symbol to the same part as FIG. 1 thru | or FIG.
この実施例では、半導体素子搭載部２及びリード３の先
端部に夫々空洞部2a,3aを形成するとともに、この半導
体素子搭載部２の空洞部2aと、選択されたリード３の空
洞部3a間に渡ってこれらと同一材質の平板６を挿入し、
搭載部２とリード３とを直接的に電気接続している。In this embodiment, the cavities 2a and 3a are formed at the tip portions of the semiconductor element mounting portion 2 and the leads 3, respectively, and the cavities 2a of the semiconductor element mounting portion 2 and the cavities 3a of the selected leads 3 are formed. Insert the flat plate 6 made of the same material as these,
The mounting portion 2 and the leads 3 are directly electrically connected.
なお、他のリード３においては、第１実施例と同様に夫
々独立した平板５が各空洞部3aに挿入されている。In addition, in the other leads 3, independent flat plates 5 are inserted into the respective hollow portions 3a as in the first embodiment.
この構成によれば、半導体素子搭載部２上に半導体素子
10をマウント用ロー材12でマウントし、前記半導体素子
10上の電極と前記各リード３の平板５とをボンディング
用金属線11で接続することにより、金属線11を短くで
き、高周波特性の向上及び信頼性の向上が達成できるこ
とは第１実施例と同じである。According to this configuration, the semiconductor element is mounted on the semiconductor element mounting portion 2.
10 is mounted with the mounting brazing material 12, and the semiconductor element
By connecting the electrodes on 10 and the flat plate 5 of each lead 3 with the bonding metal wire 11, the metal wire 11 can be shortened, and high frequency characteristics and reliability can be improved as compared with the first embodiment. Is the same.
更に、この実施例では半導体素子10の特定の電極を平板
６にボンディング用金属線11で接続しているため、平板
６を接地端子として用いれば、半導体素子10の接地抵抗
を低減できるとともに、平板６を介して半導体素子搭載
部２と選択されたリード３とを接触させるので、半導体
素子10における放熱特性を向上でき、半導体パッケージ
自身の熱抵抗を低減することもできる。Furthermore, in this embodiment, since the specific electrode of the semiconductor element 10 is connected to the flat plate 6 by the bonding metal wire 11, if the flat plate 6 is used as a ground terminal, the ground resistance of the semiconductor element 10 can be reduced and Since the semiconductor element mounting portion 2 and the selected lead 3 are brought into contact with each other via 6, the heat dissipation characteristics of the semiconductor element 10 can be improved and the thermal resistance of the semiconductor package itself can be reduced.
以上説明したように本発明は、リードフレームの半導体
素子搭載部及び複数本のリードに夫々空洞部を設け、こ
れら空洞部内に電気的接触を保持した状態で引き出し或
いは収納可能に導電性の平板を挿入しているので、この
平板で素子の搭載或いは金属線の接続を行うことによ
り、ボンディング用金属線長を短くし、リードインダク
タンスを低減化して高周波特性の改善を図るとともに、
金属線の短絡を防止して信頼性を向上できる効果があ
る。また、平板により搭載部とリードとを直接的に接続
することにより、半導体パッケージ自身の熱抵抗の低減
を図ることができる効果もある。INDUSTRIAL APPLICABILITY As described above, according to the present invention, the semiconductor element mounting portion of the lead frame and the plurality of leads are provided with cavities respectively, and a conductive flat plate that can be pulled out or stored while maintaining electrical contact in these cavities is provided. Since it is inserted, by mounting the element or connecting the metal wire with this flat plate, the length of the metal wire for bonding is shortened, the lead inductance is reduced, and the high frequency characteristic is improved,
This has the effect of preventing short-circuiting of the metal wires and improving reliability. Further, there is an effect that the thermal resistance of the semiconductor package itself can be reduced by directly connecting the mounting portion and the lead with the flat plate.
第１図は本発明の半導体パッケージに係る素子を搭載し
た状態のリードフレームの平面図、第２図は第１図のAA
線に沿う断面図、第３図は大きい面積の素子を搭載した
状態の第２図と同様の断面図、第４図は本発明の第２実
施例の素子搭載状態のリードフレームの平面図、第５図
は第３図のBB線の断面図、第６図は従来の半導体パッケ
ージの素子を搭載した状態のリードフレームの平面図、
第７図は第６図のCC線に沿う断面図である。 １……リードフレーム、２……半導体素子搭載部、2a…
…空洞部、３……リード、3a……空洞部、4,5,6……平
板、10……半導体素子、11……ボンディング用金属線、
12……マウント用ロー材、21……リードフレーム、22…
…半導体素子搭載部、23……リード。FIG. 1 is a plan view of a lead frame in which an element according to the semiconductor package of the present invention is mounted, and FIG. 2 is AA of FIG.
FIG. 3 is a cross-sectional view taken along the line, FIG. 3 is a cross-sectional view similar to FIG. 2 with a large-area element mounted, and FIG. 4 is a plan view of the lead frame with the element mounted according to the second embodiment of the present invention. FIG. 5 is a sectional view taken along the line BB in FIG. 3, and FIG. 6 is a plan view of a lead frame in which conventional semiconductor package elements are mounted,
FIG. 7 is a sectional view taken along the line CC of FIG. 1 ... Lead frame, 2 ... Semiconductor element mounting part, 2a ...
… Cavity, 3 …… Lead, 3a …… Cavity, 4,5,6 …… Plate, 10 …… Semiconductor element, 11 …… Bonding metal wire,
12 …… Mounting brazing material, 21 …… Lead frame, 22…
… Semiconductor element mounting part, 23 …… Lead.
Claims (1)
体素子搭載部及びこの周囲に配設した複数本のリードに
夫々空洞部を設け、これら空洞部内には前記半導体素子
搭載部及びリードを夫々電気的接触を保持した状態で引
き出し或いは収納可能に導電性の平板を挿入したことを
特徴とする半導体パッケージ。1. A semiconductor device mounting portion of a lead frame made of a conductive material and a plurality of leads arranged around the semiconductor device mounting portion are provided with cavities respectively, and the semiconductor device mounting portion and the leads are electrically provided in the cavities. A semiconductor package in which a conductive flat plate is inserted so that it can be pulled out or stored while maintaining physical contact.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31224487A JPH0682774B2 (en) | 1987-12-11 | 1987-12-11 | Semiconductor package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31224487A JPH0682774B2 (en) | 1987-12-11 | 1987-12-11 | Semiconductor package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01154543A JPH01154543A (en) | 1989-06-16 |
| JPH0682774B2 true JPH0682774B2 (en) | 1994-10-19 |
Family
ID=18026901
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP31224487A Expired - Lifetime JPH0682774B2 (en) | 1987-12-11 | 1987-12-11 | Semiconductor package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0682774B2 (en) |
-
1987
- 1987-12-11 JP JP31224487A patent/JPH0682774B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01154543A (en) | 1989-06-16 |
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