JPH0681034B2 - Logic LSI - Google Patents

Description

Description: TECHNICAL FIELD The present invention is particularly effective when applied to a signal forming circuit in an LSI (Large Scale Integrated Circuit) such as a gate array formed by a master slice method. The present invention relates to a technique effective for use in, for example, a clock forming circuit in a logic LSI having a non-threshold logic circuit as a basic circuit.

BACKGROUND ART Conventionally, for example, a logical LS formed by a master slice method.
ECL (emitter coupled logic) circuits and non-threshold logic circuits (hereinafter referred to as NTL circuits) as shown in FIG. 1 are used as basic circuits constituting I (hereinafter referred to as master slice LSI). Is proposed.

In FIG. 1, Q ₁ is an input transistor, and the collector of this input transistor Q ₁ is connected to the power supply voltage V _CC via the resistor R _1.
(Ground level), and the emitter of the input transistor Q ₁ is connected to the power supply voltage V such as −2V via the resistor R _2.
Connected to _EE i. Then, the input voltage Vin is supplied to the base of the input transistor Q ₁ . Q
Reference numeral ₂ is an output transistor which operates by receiving the potential of a connection node n ₁ between the collector of the input transistor Q ₁ and the resistor R ₁ as a base. The output transistor Q ₂ and the resistor R ₃ connected to the emitter side of the output transistor Q ₂ form an emitter follower.

The NTL circuit has an input voltage Vin of, for example, −1.4V to −0.
When changed toward 8V, the collector current passed through the transistor Q ₁ increases and the potential of the node n ₁ is lowered by the voltage drop of the resistor R ₁ . Therefore, the output transistor Q ₂ is operated so that its collector current is reduced, and the output voltage Vout is changed from −0.8V to −1.4V. At this time, the output voltage Vout is quickly changed in response to the change of the input voltage Vin. That is, the NTL circuit is designed not to have a threshold voltage, and thereby the operating speed is made faster than that of the ECL circuit.

Although only one input transistor Q ₁ is shown in the drawing, in the master slice LSI, the resistors R ₁ and R ₁ are generally used.
_A plurality of input transistors are provided in parallel with the transistor Q ₁ between the _two and configured as a multi-input NOR gate. In addition, a multi-output gate is formed by preparing a plurality of emitter follower transistors and resistors.

However, as is well known, the ECL circuit (or CML circuit) outputs an NOR signal (NO) in addition to the OR (OR) output as an output signal.
R) output is obtained, whereas the NTL circuit shown in FIG. 1 can take out only NOR output. Therefore, in a master slice LSI whose basic circuit is an NTL circuit, complementary signals such as clock CK,
When ▼ is required, as shown in FIG. 2, two NTL circuits G ₁ and G ₂ are used, and the clock ▲ ▼ output from _one NTL circuit G ₁ is used for the other NTL circuit G _1. By inverting with G ₂ , complementary signals ▲ ▼ and CK had to be generated.

However, when the NTL circuits G ₁ and G ₂ are connected in two stages to form complementary signals ▲ ▼ and CK as described above, the gate delay in the NTL circuit G ₂ in the subsequent stage causes the signal CK to fall and rise. Delayed from the signal ▲ ▼ by the gate delay time,
The skew between the two signals becomes large. As a result, the cycle of the signal cannot be reduced so much that the operation speed of the logic circuit operated by this signal (clock) cannot be increased, which impedes the speedup of the logic LSI configured by the master slice. It was.

[Object of the Invention] An object of the present invention is to provide a complementary signal in a master slice LSI having an NTL circuit as a basic circuit.
It is intended to provide a logic LSI capable of operating at high speed by reducing signal skew.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[Outline of Invention] The outline of a typical invention disclosed in the present application will be described below.

That is, a master slice LSI whose basic circuit is the NTL circuit
In the above, a single ECL circuit is formed by using the elements for forming a plurality of NTL circuits provided adjacent to each other.
Skew between two complementary signals by inserting a reference signal into the CL circuit and extracting complementary signals in opposite phase relationship from the OR output side emitter follower and the NOR output side emitter follower, respectively. Less,
Thus, for example, when a clock for operating the internal logic circuit is formed, the clock cycle is shortened by a small amount of skew so that the LSI can operate at high speed.

Example In this example, an input transistor as shown in FIG. 1 is used.
Three input transistors connected in parallel with Q ₁ 3
An NTL circuit that can configure an input NOR gate circuit is used as a basic circuit of an internal logic circuit, and thereby a master slice LSI is configured. That is, on a semiconductor chip such as single crystal silicon, the first
Elements to be transistors Q ₁ and Q ₂ and resistors R _{1 to} R ₃ that form the NTL circuit as shown in the figure are formed in one rectangular unit cell region. And this unit cell area CC
However, as shown in FIG. 3, four blocks are symmetrically arranged to form a block B, and by arranging the blocks B in a matrix, an internal logic circuit section is formed. There is.

Since the block B is composed of four NTL basic circuit cells, the internal elements of these blocks are used to connect appropriate elements during wiring formation by the master slice. An ECL circuit as shown in FIG. 4 can be easily constructed.

In this embodiment, an ECL circuit as shown in FIG. 4 is constructed by using the four NTL basic circuits in this way, and the reference clock CK ₀ is input to the input transistors Q _{11 to} Q ₁₃ of the ECL circuit, Clock CK from the emitter follower EF ₁ on the OR side
In addition to taking out the clock, the clock ▲ ▼ is taken out from the emitter follower EF ₂ on the NOR side and supplied to a circuit such as a flip-flop configured in the internal logic circuit section. However, in the ECL circuit, since the connection configurations of the elements on the OR side and the NOR side are symmetrical, the gate delay time is also the same.

Therefore, if two complementary signals (clocks) CK, ▲, which are anti-correlated with each other are formed by using the ECL circuit as described above, the NTL gate circuits G ₁ and G ₂ can be formed as shown in FIG. Compared with the case where two stages are connected to form the clock CK and ▲ ▼, the signal skew is reduced, and the clock cycle can be shortened accordingly.

Moreover, E that forms the clock CK, ▲ ▼ as described above
The CL circuit can be configured in an appropriate number at any place in the internal logic circuit section of the master slice LSI.

Further, in the above case, the clock forming circuit is commonly provided for a plurality of flip-flops and gate circuits. Therefore, the magnitude of the current flowing through the emitter followers EF ₁ and EF ₂ will be different. Therefore, depending on the magnitude of the load current, combine the appropriate number of elements and resistance elements that will be the output transistors in each basic circuit cell CC, and use the emitter followers EF ₁ and EF ₂ shown in FIG. Output transistor Q
₂₁ and Q ₂₂ and resistors R ₃₁ and R ₃₂ are formed so that the current density becomes constant.

In the above case, in each NTL basic circuit cell CC, the size of the emitter follower output transistor Q ₂ and the resistor R ₃ can be changed in advance depending on the number of fan-outs, that is, the size of the load current. It is conceivable to provide a plurality of elements for forming a resistor.
Therefore, using a plurality of transistors and resistors prepared in advance in each basic circuit cell as described above, the EC
If the sizes of the transistors Q ₂₁ and Q ₂₂ and the resistors R ₃₁ and R ₃₂ that form the clock forming circuit including the L circuit are changed, a design with good controllability such as current density can be performed.

It should be noted that the diode D ₁ provided in the resistance division circuit for applying the base potential to the transistors Q ₃ and Q ₄ shown in FIG. ₄ is a bipolar transistor (for example, Q ₁ ) Is used to short-circuit the base-collector and use the PN junction between the base-emitter, it is necessary to specially provide a diode element in advance in each basic circuit cell. It goes without saying that there is no such thing.

By the way, when the NTL basic circuit cell is used to form the ECL circuit as shown in FIG. 4 as described above, the pull-in of the power supply voltage V _EE becomes a problem. That is, in the NTL circuit as shown in FIG. 1, a relatively low power supply voltage V _EE i such as −2 V
Therefore, when the internal logic circuit is composed of only the NTL circuit, it suffices to provide a power supply line for supplying the power supply voltage V _CC and a power supply line for supplying the power supply voltage V _EE i. On the other hand, in the clock forming circuit (FIG. 4) of the above-mentioned embodiment, it is necessary to supply the voltage V _EE such as −3V which is lower than V _EE i. Moreover, as described above, in order to be able to configure the clock forming circuit at any location in the internal logic circuit section, the V _EE line that supplies the power supply voltage V _EE in advance must be provided in the internal logic circuit section as well as the V _CC line. It is necessary to arrange them at appropriate intervals so that they are not short-circuited with other power supply lines or the like.

FIG. 5 shows an embodiment of such a power line layout method.

In this embodiment, the local increase / decrease in the current due to the logic operation in the internal logic circuit section is mutually compensated by the entire internal logic circuit section. It is also devised to suppress fluctuations in the. That is, in the internal logic circuit part of the logic LSI, a large current is locally flowed along with the logic operation of the circuit, and the V _CC line or V
Noise may occur on the _EE i line. Then,
Even if there is a local increase / decrease in current in the internal logic circuit section, the average current as a whole is almost constant in many cases.

Therefore, in this embodiment, as shown in FIG. 5, by arranging the V _CC line L _C and the V _EE i line Li in a grid pattern in the internal logic circuit unit ILC, the local current is increased or decreased. It is designed to be able to complement each other as a whole.

In the internal logic circuit unit ILC, as described above, the blocks B as shown in FIG. 3 in which four NTL basic circuit cells CC are arranged adjacent to each other are arranged in a matrix. . VGR _{1 to} VGRn and VGL _{1 to} VGLn are the voltage V NT required for the NTL circuit based on the externally supplied power supply voltage V _EE.
It is a power supply circuit that generates _EE i. This power supply circuit VGR _1- VGR
n and VGL _{1 to} VGLn are located on both sides of the internal logic circuit unit ICL, and each block row B ₁₁ , B ₁₂ , ... B ₁ m; B ₂₁ , B ₂₂ ... B ₂ m;
Bn ₁ , Bn ₂ , ... Bnm are provided corresponding to each.

Further, power supply lines Lc _{1 to} Lcn for supplying the power supply voltage V _CC and power supply lines Li _{1 to} Lin for supplying the power supply voltage V _EE i are arranged in the lateral direction corresponding to each of the block columns. The line connecting the line lc ₁ ~lck and power lines Li ₁ ~Lin for connecting the respective power lines Lc ₁ ~Lcn li ₁ ~lik
Are alternately arranged in the vertical direction, and are short-circuited to the power supply lines Lc, Li in the horizontal direction at intersections with the corresponding lines. As a result, a power supply line network arranged in a grid pattern is formed in the internal logic circuit unit ILC. In this case, to prevent a short circuit between the power supply lines Lc _{1 to} Lcn and li _{1 to} lik and a short circuit between the power supply lines Li _{1 to} Lin and lc _{1 to} lck, although not particularly limited, aluminum three-layer wiring technology is applied. Is
The power supply lines Lc _{1 to} Lcn and Li _{1 to} Lin are formed by the third aluminum layer, and the lines lc _{1 to} lck and li _{1 to} lik are formed by the second aluminum layer, and through holes are formed at each intersection. Is connected via.

Then, a part of the above power lines Lc _{1 to} Lcn (L in the drawing
c ₂₎ in the form of replacing the power supply voltage V _EE power line L _EE supplies is formed laterally drawn from a suitable power supply circuit by a third layer of aluminum. By forming a plurality of power supply lines L _{EE at} appropriate intervals for each block row, a clock forming circuit as shown in FIG. 4 is formed at a desired position in the internal logic circuit section ILC. It is made possible.

However, in this case, since the power supply line L _EE supplies the power supply voltage V _EE such as −3 V, it is separated from the power supply voltage V _EE i such as −2 V and the power supply voltage V _CC such as 0 V. It is necessary to use the above power supply line lc ₁ -lck made of the second layer of aluminum
And li ₁ ~ lik are not connected. Also,
Power supply line L that supplies the power supply voltage V _EE formed in the lateral direction
The power supply voltage is drawn from _EE to the elements that make up the clock generation circuit by each power line Lc _{1 to} Lcn or Li _{1 to} lin.
Similar to pulling the power supply voltage into the L circuit, it is performed by using the aluminum of the second layer and the aluminum of the first layer.

On the other hand, the signal lines connecting the elements in each NTL circuit and the NTL circuits are mainly made of aluminum in the first layer and aluminum in the second layer. In addition, the horizontal power lines Lc, L
Since i and L _EE and the vertical power supply lines lc and li are respectively formed by the third and second layers of aluminum, they can be arranged above the block B including the NTL basic circuit cells. . On the other hand, since the signal line made of aluminum in the first layer may directly contact the element region, it cannot be freely arranged on the NTL basic circuit cell. Therefore, in order to secure a region for arranging the signal line connecting between the cells, in the above embodiment, each block row B ₁₁ ...
A wiring region having an appropriate width is provided between ₁ m: B ₂₁ ... B ₂ m; ~ Bn ₁ ... Bnm.

[Effect] In a master slice LSI whose basic circuit is an NTL circuit,
A single ECL circuit is constructed by using the elements in a plurality of NTL basic circuit cells provided adjacent to each other, and a reference signal is input to this ECL circuit to output an emitter follower on the OR output side and an emitter follower on the NOR output side. Therefore, since complementary signals having mutually opposite phase relations are taken out, the skew of the two complementary signals is reduced, and when a clock for operating the internal logic circuit is formed, There is an effect that it becomes possible to operate the LSI at high speed by shortening the clock cycle as much as the skew is small.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments and various modifications can be made without departing from the scope of the invention. Nor. For example, the configuration of the ECL circuit that forms the clock is not limited to that shown in FIG. 4, and various modifications can be considered.

The voltage applied to the Q ₃ base and Q ₄ base in Fig. ₄ is not generated by resistors or diodes in each ECL circuit, but by LS.
Constitute one or more of the power supply circuit to the peripheral I, Q ₃ bases of the ECL circuit is provided power supply wiring to the internal logic circuit unit ILC, it is conceivable to supply the Q ₄ base.

Various power supply voltages may be directly applied from the outside without using the power supply circuit.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an example of an NTL circuit which is a basic circuit of a logic unit of a master slice LSI, FIG. 2 is a block diagram showing an example of a configuration of a clock forming circuit using the NTL circuit, and FIG. An explanatory diagram showing an example of a basic configuration of a logic unit of a master slice LSI to which the present invention is applied, FIG. 4 is a circuit diagram showing a configuration example of a clock forming circuit using an ECL circuit, and FIG. 5 is an internal logic. It is a plane explanatory view showing an example of a layout method of a power supply line of a circuit part. Q _1, Q ₁₁ ~Q ₁₃ ...... input _{transistor, Q 2, Q 21, Q} 22 ...... emitter follower output transistors, EF _1, EF ₂ ...... emitter follower, CC ...... NTL basic circuit cells, B ...... block , VGR _{1 to} VGRn, VGL _{1 to} VGLn ... Power supply circuit, Lc _{1 to} Lcn ...
… Power line (V _CC line), Li ₁ ~ Lin …… Power line (V _EE i line), L _EE … Power line (V _EE line).

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI Technical indication location H03K 19/00 A 8941-5J 19/173 9383-5J

Claims (1)

[Claims] 1. An NTL basic cell in which elements necessary for constructing a non-threshold logic circuit are formed, and the above-mentioned NTL basic cell depending on a power supply voltage from an external power supply terminal.
A logic LSI that has a plurality of power supply voltage circuits that form the power supply voltage for the NTL basic cell and that realizes the desired logic function by connecting using the master slice method, and outputs the same function in the power supply circuit that corresponds to the horizontal direction. The terminals are connected by the third-layer aluminum wiring extending in the horizontal direction, and the third-layer aluminum wiring is connected to the second-layer aluminum layer in the vertical direction through the through holes. The mesh power supply wiring is configured, and the power supply and the signal supply to the internal logic portion configured by the NTL circuit using the above NTL basic cell are performed by the first and second aluminum wiring layers. , The reverse of each other used in the internal logic section by the emitter coupled logic circuit configured by using multiple adjacent NTL basic cells. With complementary signal relationship is being generated, the power supply line for such emitter-coupled logic is, the third for NTL circuit, first,
A logic LSI characterized in that it is composed of a third-layer aluminum wiring layer separated from a power supply line composed of a second-layer aluminum wiring layer.