JPH0680687B2 - High-speed semiconductor device manufacturing method - Google Patents
High-speed semiconductor device manufacturing methodInfo
- Publication number
- JPH0680687B2 JPH0680687B2 JP21505186A JP21505186A JPH0680687B2 JP H0680687 B2 JPH0680687 B2 JP H0680687B2 JP 21505186 A JP21505186 A JP 21505186A JP 21505186 A JP21505186 A JP 21505186A JP H0680687 B2 JPH0680687 B2 JP H0680687B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor layer
- layer
- wall
- forming
- shaped
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 47
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 238000000034 method Methods 0.000 claims description 27
- 239000012159 carrier gas Substances 0.000 claims description 18
- 238000005530 etching Methods 0.000 claims description 12
- 239000000758 substrate Substances 0.000 claims description 7
- 125000005842 heteroatom Chemical group 0.000 claims description 6
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 239000007789 gas Substances 0.000 description 5
- 239000006251 one-dimensional electron gas Substances 0.000 description 5
- 239000012535 impurity Substances 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- 230000005533 two-dimensional electron gas Effects 0.000 description 4
- 238000001451 molecular beam epitaxy Methods 0.000 description 3
- 239000000969 carrier Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005672 electromagnetic field Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000001771 vacuum deposition Methods 0.000 description 1
Classifications
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/775—Field effect transistors with one dimensional charge carrier gas channel, e.g. quantum wire FET
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Nanotechnology (AREA)
- Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Mathematical Physics (AREA)
- Theoretical Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Crystallography & Structural Chemistry (AREA)
- Ceramic Engineering (AREA)
- Junction Field-Effect Transistors (AREA)
Description
【発明の詳細な説明】 〔概要〕 本発明は、高速半導体装置の製造方法に於いて、基板上
に高抵抗の能動層を形成し、その高抵抗の能動層を適当
な深さまでエッチングしてストライプ状のメサ部分を形
成し、その上に前記能動層との間にヘテロ接合を形成す
るキャリヤ供給層を全面に形成し、そのキャリヤ供給層
を異方性エッチングして前記ストライプ状のメサ部分の
側面に壁状に延在する形状となし、その壁状キャリヤ供
給層の底面と前記能動層とがなすヘテロ接合が露出され
るように前記メサ部分及び前記能動層をエッチングし、
前記キャリヤ供給層の両端に電極を形成し、それら電極
の間の壁状能動層に生成される準一次元キャリヤ・ガス
層を制御する電極を形成することに依り、二次元電子ガ
ス層をチャネルとする高電子移動度トランジスタよりも
遥かに高速の半導体装置を容易に製造できるようにした
ものである。DETAILED DESCRIPTION OF THE INVENTION [Outline] The present invention relates to a method for manufacturing a high-speed semiconductor device, in which a high-resistance active layer is formed on a substrate and the high-resistance active layer is etched to an appropriate depth. A stripe-shaped mesa portion is formed, a carrier supply layer for forming a heterojunction with the active layer is formed on the entire surface, and the carrier supply layer is anisotropically etched to form the stripe-shaped mesa portion. A side wall of the mesa portion and the active layer are etched so that a heterojunction formed by the bottom surface of the wall-shaped carrier supply layer and the active layer is exposed.
The two-dimensional electron gas layer is channeled by forming electrodes at both ends of the carrier supply layer and forming electrodes controlling the quasi-one-dimensional carrier gas layer generated in the wall-shaped active layer between the electrodes. This makes it possible to easily manufacture a semiconductor device having a much higher speed than the high electron mobility transistor.
本発明は、準一次元キャリヤ・ガス層をチャネルとする
高速半導体装置の製造方法に関する。The present invention relates to a method of manufacturing a high speed semiconductor device having a quasi-one-dimensional carrier gas layer as a channel.
従来、高抵抗の能動層と電子親和力が該能動層に比較し
て小さく且つ不純物がドーピングされた電子供給層とで
ヘテロ接合を形成し、そのヘテロ界面の近傍に於ける前
記能動層側に生成される二次元電子ガス層をチャネルと
して利用する高速半導体装置、即ち、高電子移動度トラ
ンジスタ（high electron mobility transistor:HEMT）
が知られている。Conventionally, a heterojunction is formed between an active layer having a high resistance and an electron supply layer which has a smaller electron affinity than the active layer and is doped with impurities, and is formed on the active layer side near the hetero interface. Speed semiconductor device using the generated two-dimensional electron gas layer as a channel, that is, high electron mobility transistor (HEMT)
It has been known.
そのHEMTに於いては、前記したように、電子が二次元電
子ガス層中を移動するものであり、そこでは不純物散乱
などの影響を受けることが少ないので、電子は高速で移
動することができ、その移動度は約10万〔cm2/V・ｓ〕
程度にも達する。In the HEMT, as described above, the electrons move in the two-dimensional electron gas layer, and there is little influence of impurity scattering etc., so the electrons can move at high speed. , Its mobility is about 100,000 [cm 2 / V ・ s]
It reaches the level.
前記したようにHEMTは極めて高速であるが、現在、次の
世代を担うトランジスタの開発が進行しつつあり、その
トランジスタに対しては更に高速化が要求されている。As described above, the HEMT is extremely fast, but currently, the development of a transistor for the next generation is under development, and the transistor is required to have a higher speed.
そのような超高速トランジスタの一種として一次元キャ
リヤ・ガス層をチャネルとするものが試作されている
が、これは云うまでもなく、キャリヤ・ガス層が線状を
なすものであり、HEMTに於ける二次元電子ガス層と比較
すると更に不純物散乱が少なくなる。As a kind of such an ultra-high speed transistor, a device using a one-dimensional carrier gas layer as a channel has been prototyped. Needless to say, this is because the carrier gas layer has a linear shape. In comparison with the two-dimensional electron gas layer, the impurity scattering is further reduced.
試作された一次元キャリヤ・ガス層を有する高速半導体
装置の構造としては、Ｖ字溝の稜線の部分にキャリヤ・
ガス層が生成されるようにしたものが知られているが、
ヘテロ界面との関係上、そのような構造の高速半導体装
置を製造することは甚だ困難である。As a structure of a prototype high-speed semiconductor device having a one-dimensional carrier gas layer, a carrier layer is formed at the ridge of the V-shaped groove.
It is known that a gas layer is generated,
It is extremely difficult to manufacture a high-speed semiconductor device having such a structure because of the relationship with the hetero interface.
本発明は、一次元キャリヤ・ガス層の線幅を然程狭くす
ることはできないが、準一次元と呼べる程度のキャリヤ
・ガス層を有する高速半導体装置を極めて容易に製造で
きる方法を提供する。The present invention provides a method capable of extremely easily manufacturing a high-speed semiconductor device having a carrier gas layer that can be called quasi-one-dimensional, although the line width of the one-dimensional carrier gas layer cannot be made so narrow.
本発明に依る高速半導体装置の製造方法に於いては、基
板（例えば半絶縁性GaAs基板１）上に高抵抗の第１の半
導体層（例えばｉ型GaAs能動層２）を形成する工程と、
次いで、前記第１の半導体層を適当な深さまでエッチン
グしてストライプ状のメサ部分（例えばメサ部分2A）を
形成する工程と、次いで、前記第１の半導体層との間で
ヘテロ接合を形成し且つ前記第１の半導体層に比較して
電子親和力が小である第２の半導体層（例えばｎ型AlGa
As電子供給層４）を全面に形成する工程と、次いで、前
記第２の半導体層を異方性エッチングして前記ストライ
プ状のメサ部分に於ける側面に被着された壁状に延在す
る部分のみを残して他を除去する工程と、次いで、前記
壁状に延在する第２の半導体層に於ける底面と前記第１
の半導体層とがなすヘテロ界面が露出される適当な深さ
まで前記ストライプ状のメサ部分及び第１の半導体層を
エッチングする工程と、次いで、前記壁状に延在する第
２の半導体層の両端に対向して電極（例えばソース電極
６及びドレイン電極７）を形成する工程と、次いで、前
記対向して形成された電極間に前記壁状に延在する第２
の半導体層及び第１の半導体層のヘテロ界面近傍の前記
第１の半導体層側に生成されるキャリヤ・ガス層（例え
ば準一次元電子ガス層５）を制御する為の電極（例えば
ゲート電極８）を形成する工程とを含んでなる構成にな
っている。In the method of manufacturing a high-speed semiconductor device according to the present invention, a step of forming a high-resistance first semiconductor layer (eg, i-type GaAs active layer 2) on a substrate (eg, semi-insulating GaAs substrate 1),
Next, a step of etching the first semiconductor layer to an appropriate depth to form a stripe-shaped mesa portion (for example, the mesa portion 2A), and then forming a heterojunction with the first semiconductor layer. In addition, the second semiconductor layer having a smaller electron affinity than that of the first semiconductor layer (for example, n-type AlGa
As electron supply layer 4) is formed on the entire surface, and then the second semiconductor layer is anisotropically etched to extend in a wall shape attached to a side surface of the stripe-shaped mesa portion. Removing only the part and removing the others, and then the bottom surface of the second semiconductor layer extending in the wall shape and the first semiconductor layer.
Etching the stripe-shaped mesa portion and the first semiconductor layer to an appropriate depth so that the hetero-interface formed with the semiconductor layer is exposed, and then both ends of the wall-shaped second semiconductor layer are etched. A step of forming electrodes (for example, a source electrode 6 and a drain electrode 7) facing each other, and then a second wall-shaped extending between the electrodes formed facing each other.
Electrode for controlling the carrier gas layer (for example, the quasi-one-dimensional electron gas layer 5) generated on the side of the first semiconductor layer in the vicinity of the hetero interface between the semiconductor layer and the first semiconductor layer (for example, the gate electrode 8). ) Is formed.
前記手段を採ることに依って得られた高速半導体装置で
は、キャリヤ・ガス層が完全な一次元とは言い難いがそ
れに近いパターンで生成されるので、その準一次元キャ
リヤ・ガス層を走行するキャリヤが受ける散乱は極めて
すくなくなり、キャリヤ移動度は二次元キャリヤ・ガス
層の10倍程度、即ち、100万〔cm2/V・ｓ〕程度にも達
し、しかも、その高速半導体装置は、現在、安定した技
法になっている、所謂、サイド・ウォール法と呼ばれて
いる異方性エッチング法を利用した技術を適用すること
で簡単に製造することが可能であり、その量産も容易で
ある。In the high-speed semiconductor device obtained by adopting the above-mentioned means, the carrier gas layer is generated in a pattern close to that of the one-dimensional carrier gas layer, but the carrier gas layer travels in the quasi-one-dimensional carrier gas layer. The scattering received by the carriers is extremely small, and the carrier mobility reaches about 10 times that of the two-dimensional carrier gas layer, that is, about 1,000,000 [cm 2 / Vs], and the high-speed semiconductor device is currently It is possible to easily manufacture by applying a technique utilizing a so-called side wall method, which is a stable technique, and is easy to mass-produce. .
第１図乃至第５図は本発明一実施例を解説する為の工程
要所に於ける半導体装置の要部切断側面図、第６図は同
じく要部切断斜面図、第７図は同じく要部切断平面図を
それぞれ表し、以下、これ等の図を参照しつつ説明す
る。FIGS. 1 to 5 are side views of essential parts of a semiconductor device in a process essential part for explaining an embodiment of the present invention, FIG. 6 is a perspective view of essential parts of the same, and FIG. Respective partial cutaway plan views are shown and described below with reference to these drawings.
第１図参照 （１）分子線エピタキシャル成長（molecular beam epi
taxy:MBE）法を適用することに依り、半絶縁性GaAs基板
１上に厚さが例えば6000〔Å〕であるｉ型GaAs能動層２
を成長させる。See Fig. 1 (1) Molecular beam epitaxy
By applying the taxy: MBE method, an i-type GaAs active layer 2 having a thickness of, for example, 6000 [Å] is formed on the semi-insulating GaAs substrate 1.
Grow.
第２図参照 （２）通常のフォト・リソグラフィ技術に於けるレジス
ト・プロセスを適用することに依り、エッチング・マス
クとなるストライプ状のフォト・レジスト膜３を形成す
る。See FIG. 2 (2) By applying a resist process in a normal photolithography technique, a stripe-shaped photoresist film 3 to be an etching mask is formed.
この場合のフォト・レジスト膜３に於けるストライプ幅
は1.0〔μｍ〕〜0.5〔μｍ〕の範囲で選択することがで
きる。In this case, the stripe width of the photoresist film 3 can be selected in the range of 1.0 [μm] to 0.5 [μm].
（３）エッチング・ガスをCF4とする反応性イオン・エ
ッチング（reactive ion etching:RIE）法を適用するこ
とに依り、フォト・レジスト膜３をマスクとして能動層
２のエッチングを行う。(3) The active layer 2 is etched by using the photoresist film 3 as a mask by applying a reactive ion etching (RIE) method using CF 4 as an etching gas.
これに依り、フォト・レジスト膜３と同じストライプ状
のパターンを有し、また、その高さが2000〔Å〕である
メサ部分2Aが形成される。As a result, the mesa portion 2A having the same stripe pattern as the photoresist film 3 and having a height of 2000 [Å] is formed.
第３図参照 （４）エッチング・マスクとして用いたフォト・レジス
ト膜３を除去してから、MBE法を適用することに依り、
ｎ型AlXGa1-XAs電子供給層４を形成する。See FIG. 3 (4) By removing the photoresist film 3 used as the etching mask and then applying the MBE method,
The n-type Al X Ga 1-X As electron supply layer 4 is formed.
ここで、電子供給層４に関する主要データを例示すると
次の通りである。Here, the main data regarding the electron supply layer 4 will be exemplified as follows.
ｘ値:0.3 厚さ:300〔Å〕 不純物濃度:1×1018〔cm-3〕 尚、電子供給層４の厚さは100〔Å〕乃至300〔Å〕の範
囲で任意に選択される。x value: 0.3 Thickness: 300 [Å] Impurity concentration: 1 × 10 18 [cm -3 ] The thickness of the electron supply layer 4 is arbitrarily selected within the range of 100 [Å] to 300 [Å] .
第４図参照 （５）エッチング・ガスをCF4とするRIE法を適用するこ
とに依り、マスクを用いることなく、電子供給層４のエ
ッチングを行う。See FIG. 4 (5) By applying the RIE method using CF 4 as an etching gas, the electron supply layer 4 is etched without using a mask.
ここで適用される技術は、所謂、サイド・ウォール法と
呼ばれる技術であり、異方性ドライ・エッチングにて幅
狭い壁状の膜を形成する技術である。The technique applied here is a so-called side wall technique, which is a technique for forming a narrow wall-shaped film by anisotropic dry etching.
これに依り、電子供給層４はメサ部分2Aの側面に被着し
ているもののみが壁状に残って他は除去される。As a result, only the electron supply layer 4 adhered to the side surface of the mesa portion 2A remains in the form of a wall, and the others are removed.
第５図及び第６図参照 （６）エッチング・ガスをCCl2F2とするRIE法を適用す
ることに依り、マスクを用いることなく、能動層２及び
メサ部分2Aのエッチングを行う。尚、この場合、電子供
給層４はエッチングされない。See FIGS. 5 and 6. (6) The active layer 2 and the mesa portion 2A are etched without using a mask by applying the RIE method using CCl 2 F 2 as an etching gas. In this case, the electron supply layer 4 is not etched.
この場合のエッチングは、電子供給層４と能動層２との
界面を約1000〔Å〕程度越えるまで行うものとする。In this case, the etching is performed until the interface between the electron supply layer 4 and the active layer 2 is exceeded by about 1000 [Å].
このように形成された壁状の電子供給層４並びに能動層
２の接合面は云うまでもなくヘテロ界面になり、従っ
て、その近傍の壁状の能動層２側に準一次元電子ガス層
５が生成されるものである。Needless to say, the junction surfaces of the wall-shaped electron supply layer 4 and the active layer 2 formed in this manner form a hetero interface, and therefore, the quasi-one-dimensional electron gas layer 5 is located near the wall-shaped active layer 2 side. Is generated.
ここで、一次元電子ガス層に「準」と断っている理由
は、前記したところから判るように、電子ガス層が300
〔Å〕を越えることはないにしても、半導体技術に於い
ては充分に認識できる程度の「幅」を有しているからで
ある。Here, the reason why the one-dimensional electron gas layer is referred to as “quasi” is that the electron gas layer is 300
This is because, even if it does not exceed [Å], it has a sufficiently wide "width" in semiconductor technology.
第６図参照 （７）通常の技法、例えば真空蒸着法及びリフト・オフ
法などを適用することに依り、AuGe/Au膜からなるソー
ス電極６及びドレイン電極７、Alからなるゲート電極８
を形成する。See FIG. 6 (7) A source electrode 6 and a drain electrode 7 made of an AuGe / Au film and a gate electrode 8 made of Al are formed by applying a usual technique such as a vacuum deposition method and a lift-off method.
To form.
前記実施例に依って得られた高速半導体装置では、準一
次元電子ガス層５が２本であるが、これは更に本数を増
すことは容易であり、そのようにすると、超高速性を維
持しながら大きな電流を取り出すことができる。In the high-speed semiconductor device obtained according to the above-mentioned embodiment, the number of quasi-one-dimensional electron gas layers 5 is two, but it is easy to further increase the number, and by doing so, the ultra-high speed can be maintained. However, a large current can be taken out.
本発明に依る高速半導体装置の製造方法に於いては、基
板上に高抵抗の能動層を形成し、その高抵抗の能動層を
適当な深さまでエッチングしてストライプ状のメサ部分
を形成し、その上に前記能動層との間にヘテロ接合を形
成するキャリヤ供給層を全面に形成し、そのキャリヤ供
給層を異方性エッチングして前記ストライプ状のメサ部
分の側面に壁状に延在する形状となし、その壁状キャリ
ヤ供給層の底面と前能動層とがなすヘテロ接合が露出さ
れるように前記メサ部分及び前記能動層をエッチング
し、前記壁状のキャリヤ供給層の長手方向両端に電極を
形成し、それら電極間の壁状の能動層に於けるヘテロ界
面近傍に生成される準一次元キャリヤ・ガス層を制御す
る電極を形成することに依り、 この方法を実施して得られた高速半導体装置では、キャ
リヤ・ガス層が完全な一次元とは言い難いがそれに近い
パターンで生成されるので、その準一次元キャリヤ・ガ
ス層を走行するキャリヤが受ける散乱は極めてすくなく
なり、キャリヤ移動度は二次元キャリヤ・ガス層の10倍
程度、即ち、100万〔cm2/V・ｓ〕程度にも達し、しか
も、その高速半導体装置は、現在、安定した技法になっ
ている。所謂、サイド・ウォール法と呼ばれている異方
性エッチング法を利用する技術を適用することで簡単に
製造することが可能であり、その量産も容易でる。In the method for manufacturing a high-speed semiconductor device according to the present invention, a high resistance active layer is formed on a substrate, and the high resistance active layer is etched to an appropriate depth to form a stripe-shaped mesa portion, A carrier supply layer that forms a heterojunction with the active layer is formed on the entire surface, and the carrier supply layer is anisotropically etched to extend in a wall shape on the side surface of the stripe-shaped mesa portion. The mesa portion and the active layer are etched so that the heterojunction formed by the bottom surface of the wall-shaped carrier supply layer and the front active layer is exposed, and both ends of the wall-shaped carrier supply layer in the longitudinal direction are etched. It is obtained by carrying out this method by forming electrodes and controlling the quasi-one-dimensional carrier gas layer generated near the hetero interface in the wall-shaped active layer between the electrodes. High speed semiconductor device However, since the carrier gas layer cannot be said to be completely one-dimensional, but is generated in a pattern close to that, the scattering received by the carriers traveling in the quasi-one-dimensional carrier gas layer is extremely low and the carrier mobility is two. It reaches about 10 times that of the dimensional carrier gas layer, that is, reaches about 1,000,000 [cm 2 / V · s], and the high-speed semiconductor device is a stable technique at present. It can be easily manufactured by applying a technique utilizing an anisotropic etching method called a so-called side wall method, and its mass production is also easy.
第１図乃至第５図は本発明一実施例を説明する為の工程
要所に於ける半導体装置の要部切断側面図、第６図は同
じく要部切断斜面図、第７図は同じく要部切断平面図を
それぞれ表している。 図に於いて、１は半絶縁性GaAs基板、２はｉ型GaAs能動
層、2Aはメサ部分、３はフォト・レジスト膜、４はｎ型
AlGaAs電子供給層、５は準一次元電子ガス層、６はソー
ス電磁、７はドレイン電極、８はゲート電極をそれぞれ
示している。FIGS. 1 to 5 are side views of essential parts of a semiconductor device in a process essential part for explaining one embodiment of the present invention, FIG. 6 is a perspective view of essential parts, and FIG. The partial cutaway plan views are respectively shown. In the figure, 1 is a semi-insulating GaAs substrate, 2 is an i-type GaAs active layer, 2A is a mesa portion, 3 is a photoresist film, and 4 is n-type.
AlGaAs electron supply layer, 5 is a quasi-one-dimensional electron gas layer, 6 is a source electromagnetic field, 7 is a drain electrode, and 8 is a gate electrode.
Claims (1)
る工程と、 次いで、前記第１の半導体層を適当な深さまでエッチン
グしてストライプ状のメサ部分を形成する工程と、 次いで、前記第１の半導体層との間でヘテロ接合を形成
し且つ前記第１の半導体層に比較して電子親和力が小で
ある第２の半導体層を全面に形成する工程と、 次いで、前記第２の半導体層を異方性エッチングして前
記ストライプ状のメサ部分に於ける側面に被着された壁
状に延在する部分のみを残して他を除去する工程と、 次いで、前記壁状に延在する第２の半導体層に於ける底
面と前記第１の半導体層とがなすヘテロ界面が露出され
る適当な深さまで前記ストライプ状のメサ部分及び第１
の半導体層をエッチングする工程と、 次いで、前記壁状に延在する第２の半導体層の両端に対
向して電極を形成する工程と、 次いで、前記対向して形成された電極間に前記壁状に延
在する第２の半導体層及び第１の半導体層のヘテロ界面
近傍の前記第１の半導体層側に生成されるキャリヤ・ガ
ス層を制御する為の電極を形成する工程と を含んでなることを特徴とする高速半導体装置の製造方
法。1. A step of forming a high-resistance first semiconductor layer on a substrate, a step of etching the first semiconductor layer to an appropriate depth to form a stripe-shaped mesa portion, Forming a heterojunction with the first semiconductor layer and forming a second semiconductor layer having an electron affinity smaller than that of the first semiconductor layer on the entire surface; Anisotropically etching the second semiconductor layer to remove only the wall-shaped portion of the stripe-shaped mesa portion which is attached to the side surface of the semiconductor layer, and to remove the other portions, and then to form the wall-shaped portion. The stripe-shaped mesa portion and the first portion are formed to an appropriate depth to expose a hetero-interface between the bottom surface of the extending second semiconductor layer and the first semiconductor layer.
The step of etching the semiconductor layer, the step of forming electrodes facing both ends of the second semiconductor layer extending in the shape of the wall, and the step of forming the wall between the electrodes formed facing each other. Forming an electrode for controlling a carrier gas layer generated on the side of the first semiconductor layer in the vicinity of the hetero interface between the second semiconductor layer and the first semiconductor layer extending in a line shape. And a method for manufacturing a high-speed semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21505186A JPH0680687B2 (en) | 1986-09-13 | 1986-09-13 | High-speed semiconductor device manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21505186A JPH0680687B2 (en) | 1986-09-13 | 1986-09-13 | High-speed semiconductor device manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6372165A JPS6372165A (en) | 1988-04-01 |
| JPH0680687B2 true JPH0680687B2 (en) | 1994-10-12 |
Family
ID=16665946
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21505186A Expired - Lifetime JPH0680687B2 (en) | 1986-09-13 | 1986-09-13 | High-speed semiconductor device manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0680687B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2545956B2 (en) * | 1988-11-15 | 1996-10-23 | 日本電気株式会社 | Field effect transistor |
-
1986
- 1986-09-13 JP JP21505186A patent/JPH0680687B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6372165A (en) | 1988-04-01 |
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