JPH0680195U - Solar cell clock - Google Patents

Abstract

(57) [Summary] [Object] The present invention provides a solar cell timepiece capable of charging a large-capacity capacitor even under low illumination. [Configuration] In a solar cell timepiece having a large-capacity capacitor and a small-capacity capacitor, a time-division signal generation circuit is provided and a large-capacity capacitor is generated by a division signal when re-irradiation of light after the large-capacity capacitor is completely discharged. The small-capacity capacitors are charged alternately. [Effect] It is possible to charge a large-capacity capacitor even under low illuminance.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to improvement of charging characteristics of an electronic timepiece driven by a solar cell and a large-capacity capacitor as a storage battery.

[0002]

[Prior art]

 Conventionally, by combining a solar cell and an electric double layer type large-capacity capacitor, a long-life electronic timepiece that does not require battery replacement has been commercialized. However, since the large-capacity capacitor has a large capacity, once it is completely discharged by leaving the electronic timepiece in a dark place, the operation of the clock circuit will start even if it is put out in the next bright place and exposed to light. There is a problem that it takes too long to start the operation of the watch because it takes a long time to charge it to the voltage. However, a proposal for solving this problem is made in Japanese Patent Publication No. 80355/1992, which will be described below with reference to the drawings.

FIG. 4 is a block diagram of a conventional solar cell timepiece, 1 is a solar cell, 2 is a diode for preventing backflow to the solar cell, 3 is an electric double layer type large capacity capacitor, and 4 is a timepiece. Reference numeral 5 is a constant voltage circuit, 6 is a discharging diode, 7 is a voltage detecting circuit, 8 is a charging circuit, 9 is a reverse current preventing diode, 10 is a charging transistor, and 11 is a small capacitor. is there. When the generated voltage of the solar cell 1 exceeds the forward voltage of the diode 2 and becomes the minimum operating voltage or higher, the clock circuit 4 starts to function. Here, the charging transistor 10 does not turn on until the voltage detection circuit 7 detects a voltage level at which the clock circuit 4 can sufficiently operate and generates a detection signal. When the voltage detection circuit 7 detects that the voltage generated by the solar cell 1 is at a sufficiently high voltage level, the charging transistor 10 is turned on, and the surplus current generated by the solar cell 1 causes the large capacity capacitor 3 to flow. Is charged. When the terminal voltage of the large-capacity capacitor 3 rises due to sufficient charging, the constant voltage circuit 5 controls the rated voltage. When the illuminance decreases, the clock circuit 4 is driven by the electricity stored in the large-capacity capacitor 3 via the diode 6.

While the voltage detection circuit 7 is detecting the state where the illuminance is low as in the above configuration, the charging circuit 8 is turned off, and the clock circuit 4 is driven only by the small capacity capacitor 11. When the voltage detection circuit 7 detects a voltage rise above the time when the voltage detection circuit 7 maintains the clock function, the charging transistor 10 is turned on and the surplus current of the solar cell 1 is distributed to the charging of the large-capacity capacitor 3. The clock circuit 4 can be quick-started without waiting for the charging time of the large capacity capacitor 7.

[0005]

[Problems to be solved by the device]

 According to the configuration shown in FIG. 4, it is basically possible to perform a quick start without waiting for the charging time of the large-capacity capacitor 3 even when the large-capacity capacitor 3 is once discharged and then exposed to light. . However, in the above configuration, there is a problem that the large-capacity capacitor 3 will not be charged forever depending on the irradiation condition when the light is applied from the discharged state. In other words, considering that the place where the solar cell clock restarts light irradiation is a room with low illuminance, the condition of this room is such that the generated voltage of the solar cell maintains the minimum operation start voltage. If only this is obtained, the clock circuit 4 starts its operation with the small capacity capacitor 11, but since the voltage detection circuit 7 cannot generate a detection signal, the charging transistor 10 does not turn on and the large capacity capacitor 3 is supplied. Is not charged.

Therefore, while the solar cell 1 is exposed to light, the small-capacity capacitor 11 operates the clock circuit 4, but if the light is not exposed to light for some time, the large-capacity capacitor 3 supplies voltage. Since the clock circuit 4 does not exist, the operation of the clock circuit 4 is stopped. That is, the structure is such that the large-capacity capacitor 3 does not function as a secondary battery in an office under a slightly dark illumination or in a store. An object of the present invention is to solve the above problems and provide a solar cell clock capable of charging a large-capacity capacitor even under slightly dark illumination.

[0007]

[Means for Solving the Problems]

 The configuration of the present invention for achieving the above object is as follows. A solar battery and a small-capacity capacitor with a relatively small capacity that is charged by the solar cell, a large-capacity capacitor that is charged from the solar cell via the switch means, and energy is supplied from the small-capacity capacitor and the large-capacity capacitor. An electronic timepiece having a clock circuit which operates in a controlled manner is characterized in that a time division signal generation circuit is provided and the switching means is controlled by the time division signal output from the time division signal generation circuit.

Further, the clock circuit has a drive signal generation circuit that outputs a motor drive signal for driving a motor load, and the time division signal generation circuit divides one cycle time of the motor drive signal into two. It is characterized by creating a time division signal.

Further, a voltage detection circuit for detecting that the charging voltage of the large-capacity capacitor is equal to or higher than a predetermined voltage value, and a time division signal for stopping the output of the time division signal by the detection signal of the voltage detection circuit. A stop means is provided, and the switch means is held in a charged state by the time division signal stop means.

[0010]

【Example】

 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram of a solar cell clock according to the present invention, in which 1 is a solar cell, 3 is a large-capacity capacitor, and 40 is a clock circuit, which has a function of driving a motor coil 50. Reference numeral 5 is a constant voltage circuit, 6 is a discharge diode, 7 is a voltage detection circuit, TN is a charging transistor, 11 is a small capacitor, and 2 and 9 are reverse current blocking diodes. In the above configuration, the same numbers as those in FIG. 4 indicate the same elements and perform the same operations.

Next, the operation of FIG. 1 will be described. When the generated voltage of the solar cell 1 exceeds the forward voltage of the diode 2 and becomes equal to or higher than the operation start voltage of the clock circuit 40, the small capacity capacitor 11 is turned on for a short time. The clock circuit 40 starts to operate by being charged with. As a result, the clock circuit 40 outputs a divided signal Pc described later to intermittently turn on / off the charging transistor TN, so that the voltage generated by the solar cell 1 is large-capacity capacitor 3 only while the divided signal Pc is ON. Will be charged to. That is, while the divided signal Pc is OFF, the small-capacity capacitor 11 is rapidly charged to operate the clock circuit 40, and while the divided signal Pc is ON, the large-capacity capacitor 3 is charged via the charging transistor TN. Goes charged.

When the charging voltage of the large-capacity capacitor 3 rises and becomes equal to or higher than the operation start voltage as the above operation is continued, the voltage detection circuit 7 outputs the detection signal Pk and inputs it to the clock circuit 40. As a result, the divided signal Pc from the clock circuit 40 is stopped, and the small capacity capacitor 11 and the large capacity capacitor 3 are connected in parallel by holding the charging transistor TN in the ON state.

FIG. 2 is a block diagram showing details of the clock circuit 40 in FIG. 41 is a crystal oscillator circuit, 42 is a frequency dividing circuit, 43 is a motor drive signal generation circuit, 44 is a motor drive circuit, and 45 is a time division signal generation for inputting a signal from the frequency division circuit 42 and outputting a division signal Pc. When the voltage detection signal Pk supplied to the control terminal C is H, the divided signal Pc is output to the force terminal Q, and when the detection signal Pk is L, the Vdd signal is output to the force terminal Q.

Next, the operation will be described with reference to the waveform diagram of FIG. Charging is started by shining light from the state where the solar cell clock is completely discharged, and when the generated voltage reaches the operation start voltage of the clock circuit 40, the clock circuit 40 starts operating and the crystal oscillation shown in FIG. A motor drive signal Pm is output by the circuit 41, the frequency dividing circuit 42, and the motor drive signal generating circuit 43. However, at this point in time, the charging voltage is not yet sufficiently high, so the voltage detection circuit 7 detects a voltage drop and the detection signal Pk is H. In this state, as is well known, an alarm drive signal P ml for intermittently moving for 2 seconds to output a warning of voltage drop is output, and drive signals Po1 and Po2 are supplied to the motor coil 50 via coil terminals O1 and O2, respectively. It

Further, the time division signal generation circuit 45 generates the division signal Pc by the frequency division circuit 42 and supplies the division signal Pc to the output terminal Ot. The division signal Pc is controlled by the detection signal Pk and the detection signal Pk. Is output only when H is H, and the Vdd signal is output when the detection signal Pk is L. Since the charging transistor TN having the divided signal Pc as a gate signal is off when the divided signal Pc is L, the voltage generated by the solar cell 1 charges only the small capacity capacitor 11 through the diode 2, The clock circuit 40 is operated by the charging voltage of the small-capacity capacitor 11, but when the divided signal Pc becomes H, the charging transistor TN is turned on, so that the voltage generated by the solar cell 1 becomes the diode 9 and the charging voltage. The large-capacity capacitor 3 is also charged via the transistor TN. At this time, the small-capacity capacitor 11 is connected in parallel via the diode 2, but the generated voltage is almost charged in the large-capacity capacitor 3.

That is, when the illuminance is low and the detection signal Pk is in the H state, the clock circuit 40 is operated in the quick start state by the voltage charged in the small capacity capacitor 11 while the divided signal Pc is L. While the divided signal Pc is H, the voltage of the large capacity capacitor 3 is gradually increased by charging the large capacity capacitor 3. When the large-capacity capacitor 3 is sufficiently charged to increase the terminal voltage, the voltage detection circuit 7 inverts the detection signal Pk to L. As a result, the motor drive signal generation circuit 43 outputs the normal drive signal Pmh for performing the normal 1 second cycle hand movement by releasing the warning display mode, and the time division signal generation circuit 45 outputs the detection signal Pk to L. As a result, the Vdd signal (H level) is output instead of the divided signal Pc, so that the charging transistor TN is held in the ON state, and the small capacity capacitor 11 and the large capacity capacitor 3 are connected in parallel. When the charging voltage rises due to the further increase in illuminance, the constant voltage circuit 5 operates to hold the constant voltage, and the clock circuit 40 becomes a stable driving condition.

While the division signal Pc is in the OFF state, the small capacity capacitor 11 charged while the division signal Pc is OFF maintains a single hand movement operation of the electronic timepiece. 3 is gradually charged, and when the large-capacity capacitor 3 is sufficiently charged, the small-capacity capacitor 11 and the large-capacity capacitor 3 are connected in parallel to perform a stable operation of the timepiece circuit 40.

[0018]

[Effect of device]

 As described above, according to the present invention, the small-capacity capacitor and the large-capacity capacitor are charged by the time-division signal even when the illuminance is low. Even when the illuminance is low enough to maintain the minimum operation start voltage, it is possible to drive the clock circuit with a large-capacity capacitor as a secondary battery in a stable manner, greatly improving the reliability of the solar cell clock. Have the effect of becoming.

[Brief description of drawings]

FIG. 1 is a block diagram showing a solar cell timepiece according to the present invention.

FIG. 2 is a block diagram showing details of a clock circuit of the present invention.

FIG. 3 is a waveform diagram of the present invention.

FIG. 4 is a block diagram showing a conventional solar cell timepiece.

[Explanation of symbols]

 1 Solar Cell 3 Large Capacitor 4, 40 Clock Circuit 7 Voltage Detection Circuit 11 Small Capacitor 44 Motor Drive Circuit 45 Time Division Signal Generation Circuit TN Charging Transistor

Claims (3)

[Scope of utility model registration request] 1. A solar cell, a small-capacity capacitor having a relatively small capacity charged by the solar cell, a large-capacity capacitor charged from the solar cell via a switch means, and the small-capacity capacitor and the large-capacity capacitor. An electronic timepiece having a timepiece circuit that is supplied with energy to operate, and a time division signal generation circuit is provided, and the switch means is controlled by the time division signal output from the time division signal generation circuit. Battery clock. 2. The timepiece circuit has a drive signal generation circuit for outputting a motor drive signal for driving a motor load, and the time division signal generation circuit has one of the motor drive signals.
A solar cell clock characterized by creating a time division signal that divides a cycle time into two. 3. A voltage detection circuit for detecting that the charging voltage of the large-capacity capacitor is equal to or higher than a predetermined voltage value, and a time division signal for stopping the output of the time division signal by a detection signal of the voltage detection circuit. A solar cell timepiece characterized in that stop means is provided and the switch means is held in a charged state by the time division signal stop means.