JPH0679322B2 - Image editing processor - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an image editing processing apparatus that creates a composite image of a plurality of images represented by encoded image data.

[Prior Art] Conventionally, when synthesizing a plurality of images represented by encoded image data, each image data is decoded,
The composite image was created according to the layout information prepared in advance. Then, it was confirmed by actually printing out whether or not the desired composite image was obtained.

[Problems to be Solved by the Invention] On the other hand, if desired layout information is extracted while confirming a plurality of images on a display and a composite image can be created according to the layout information, the composite image can be generated using the printed out image. It is not necessary to check, and the editing process can be performed efficiently.

However, when the composite image is displayed on the display, if image data having the same resolution as the original image is used, the load for combining and displaying becomes large, and the editing process takes time. On the other hand, it suffices that parameters for editing such as layout information can be extracted on the display, and the same image quality as the original image is required and is not always required.

The present invention has been made in view of the above circumstances, and is capable of efficiently extracting edit processing parameters when synthesizing a plurality of images represented by encoded image data and displaying the synthesized image at high speed. It is an object of the present invention to provide an image editing processing device capable of performing the above.

[Means and Actions for Solving the Problem] In order to achieve the above object, the image editing processing device of the present invention stores code data obtained by coding image data of the first resolution for a plurality of images. Storage means, decoding means for decoding the coded data stored in the storage means, and image data of the first resolution decoded by the decoding means, the second resolution lower than the first resolution. Converting means for converting into image data of resolution, and performing edit processing on the image data of the second resolution corresponding to the plurality of images converted by the converting means,
A first edit processing means for obtaining image data of the second resolution corresponding to the composite image of the plurality of images; and based on the image data of the second resolution obtained by the first edit processing means, Display means for displaying a composite image of the plurality of images, and a composite image displayed by the display means for the image data of the first resolution corresponding to the plurality of images decoded by the decoding means Second edit processing means for performing edit processing according to the edit parameter used by the first edit processing means to obtain the image data of the first resolution corresponding to the composite image of the plurality of images. It is characterized by having.

[Example] <Overview> Generally, the functions of the image editing apparatus are as follows. The above two editing functions are required. The former is generally called a pipeline processor in hardware, and in this apparatus, an image editing function is executed for a certain item requiring high speed. The latter processing by the CPU is executed for items that interact with humans (it may take some time).

That is, the former pipeline processor is, for example, affine transformation (enlargement / reduction / movement / rotation) that determines the image layout, spatial filter processing (image enhancement / smoothing, etc.), and color conversion by look up table (LUT). Sequential processing of images such as processing is mainly performed.

The latter processing by the CPU generally performs complicated processing and processing that cannot be implemented by hardware. Here, it refers to processing such as cutting out an image into an arbitrary shape, copying the cut out image to another place, and correcting a part of the image. These processes are generally creative processes created by the operator and can be tolerated even if it takes some time. However, this function needs to be highly functional.

In order to carry out the above two editing processing functions with the maximum performance, it is necessary to consider from the system architecture of the editing apparatus.

That is, in order to perform both processes with sufficiently high functions at high speed, it is necessary to consider the system system to be configured, how to hold image data to be handled (format), signal flow, analysis of functions, etc. .

As a result of various examinations, the following was concluded as a system architecture as a (color) image editing apparatus.

(1) In order to edit an image, the image data has compressed data.

(2) As a compression method, vector quantization having an m × m block as one code is preferable.

In (1), in order to perform the high-resolution / high-gradation image editing processing, the image data capacity becomes extremely huge. For example, when A4,1 page is color read at 16 pel / mm, R, G,
B3 colors have a data capacity of about 48 Mbytes. In order to perform the above-described image editing interactively and with high functionality, it is an important technique to compress the color image data so that it can be edited easily. It was concluded that the vector quantization method (2) is optimal for this.

The present invention has determined the system architecture based on the above conclusions, and was able to realize a high image quality, high function, and high speed image editing processing apparatus.

Hereinafter, the present invention will be described in detail based on examples when it is applied to color processing.

FIG. 1 is a block diagram of an image editing apparatus showing an embodiment of the present invention. The image data read by the reader 1 (for example, R, G, B 8-bit digital data) is converted by the converter 11 into a luminance (Y) signal and a color difference signal (I, Q) used in the NTSC signal. To be converted. Such conversions can be performed using R,
G and B data Is given by the matrix calculation. Here, the coefficient of the conversion matrix is appropriately modified according to the color separation characteristics, γ characteristics, etc. of the reader. The Y, I and Q signals are compressed by a compressor 2 described later and stored in a disk memory 3 for image data file. Image data in the disk is Image
It is read out on an IC memory called memory 5 and processed / edited. In order to perform high-speed processing, the basic processing is edited and developed on the image memory 5 by a so-called raster operation in the process of transfer from the disk to the image memory by the hardware pipeline processor 4.

On the other hand, the image data on the image memory 5 is subjected to various kinds of processing by the CPU 8 to be processed / corrected. The editing process is CR
It is displayed on the color CRT 10 by the T controller 9, and the editing status can be monitored. The edited result is returned from the image memory 5 to the original image data through the decoder 6,
This image data is converted by the converter 12 into color signals (Yellow, Magenta, Cyan, Black) compatible with the printer and Color P
Output to rinter 7.

Next, a method of compressing image data will be described. If the spatial frequency of the Y signal that is the luminance data is well preserved by dividing it into three color signals of luminance and color difference such as Y, I, and Q, the spatial frequency of the I and Q signals that are the color difference signals will be It is known that there is little visual quality deterioration due to some limitation (cutting of high frequency components).

So, for example, I and Q signals are m × m blocks (m is an integer)
A data compression method is conceivable in which the color information is represented by an average value of, and the data amount of the color image is reduced. As the block size of the I and Q signals, a block size of 2 × 2, 4 × 4, 6 × 6 or the like is selected depending on the required image quality and the allowable memory capacity. For example, if the block size is 4x4, the memory capacity of A4,1page is 48MByte and the Y signal is 16MByte as described above.
+ I, Q signal 2MByte = 18MByte in total, resulting in a compression ratio of about 2.7.

On the other hand, for the Y signal, unlike the compression of the I and Q signals, a compression method that leaves sufficient resolution data is required.

The first method is a block coding method.

This method calculates the average value and standard deviation σ of the pixel data x in the m × m block. Next, the grayscale information for each pixel is represented by several bits. For example, it can be realized by requantizing the calculated value of (x −) / σ. This compressed data format is as shown in FIG. 2 (a). The average value and the standard deviation are followed by the density information of each pixel, and the order of this density information corresponds one-to-one to the pixel position in the block. Let Therefore, it is possible to rotate the pixels within the block by changing the order of the grayscale information.

The second method is a vector quantization method of m × m pixels.

In this method, the pixel data in the m × m block is averaged,
The data compression is measured by expressing the standard deviation σ and a code representing the rotation of the image and a code representing the pattern of the image. This compressed data format is as shown in FIG. 2 (b). Here, the code representing rotation is, for example, 90 °, 180 ° for an image pattern in an m × m block.
This is a code representing this angle in the vector quantization method using the same pattern code as that rotated by 270 °. In this embodiment, four patterns of 0 °, 90 °, 180 ° and 270 ° are represented by 2 bits.

In this method, by manipulating the rotation code, it is possible to rotate the pixels in the block.

Next, the affine transformation will be described.

Affine conversion involves enlarging, reducing, moving, and rotating images.

The address of the input image on the input memory is (x _S , y _S ).
, The main scanning direction reduction ratio is α, the sub-scanning direction reduction ratio is β, the rotation angle is φ, the rotation center coordinate is (x _C , y _C ), the movement amount in the main scanning direction is Xm, and the sub-scanning direction is when the Ym the amount of movement, the address of the output memory (x _D, y _D) when relational expression such as the following is established.

Given x _S , y _S , we find x _D , y _D according to. This can be realized, for example, by the configuration shown in FIG. Hereinafter, description will be given with reference to FIG. To obtain x _S according to the formula, the initial value offset (DC component) is set as the initial value in the register 31. The sub-scanning synchronization increment value and the main-scanning synchronization increment value are set in the registers 32 and 27, respectively. This series of values is executed by the CPU according to the reduction ratio and rotation angle. FIG. 4 is a timing chart showing the relationship among the page sync signal, the sub-scan sync signal, and the main-scan sync signal of the circuit of FIG. When the page sync signal falls, the sub-scan sync signal is started to be generated and the number of scan lines existing in the page is generated. The main scanning synchronization signal is generated by the falling of the sub scanning synchronization signal, and is generated by the number of data existing in the scanning line. These signals are generated by a synchronizing signal generating circuit (not shown).
The 33 selectors output the values held by the 31 initial value registers while the page sync signal is at the low level. The adder 34 performs addition at the falling edge of the sub-scanning synchronization signal. 34
Is latched at 35 by the sub-scanning rack synchronization.
Also, 36 is 35 while the sub-scanning synchronization signal is at the Low level.
Output the output of. The adder of 38 performs addition of the output of 36 and the main scanning synchronization increment value of 37 at the falling edge of the main scanning synchronization signal, and the output thereof is latched at 39 at the rising edge of the main scanning synchronization signal. The latch 35 holds the address on the output side corresponding to the data at the beginning of the scanning line and latches it.
39 gives the address of the corresponding output side of each data in the scan line. It is possible to obtain y _{D in the} same manner according to the formula.

The address thus obtained is an irrational number because cosφ, sinφ, etc. are generally irrational numbers. On a real machine, it is a decimal with a sufficient number of bits. An integer address near this decimal address is determined as an output address. (X _D , y _D )
In the main scanning direction with α as the center (| sinφ | + | cosφ |)
And an integer address existing in a region having a width of β (| sinφ | + | cosφ |) in the sub-scanning direction are respectively inversely converted. If this integer address is (X _D , X _D ), (X
_D, and the address of the input data side corresponding to the _{Y D) (X S, Y} S)
When The relational expression is established.

The above equation is successively obtained by the circuit shown in FIG. Figure 6 shows
6 is a timing chart of the signals in FIG. It is assumed that the initial value offset (DC component), the main-scan synchronization increment value, and the sub-scan synchronization increment value are set in the registers 57, 51, and 52 by the CPU in advance. Further, when there is a change in X _D , Y _D , each of them is controlled by a circuit (not shown) (for example, composed of a register holding the value of the previous clock and a comparator for comparing the value of the current clock). The gate signal that turns ON / OFF the gates of 53 and 54 becomes Low. At this time, the gate outputs the value of 51 and 52 independently, otherwise it is Low.
Output level, ie 50. The 55 adder executes addition at the falling edge of the main scanning synchronization signal, and the output is latched at 56 at the rising edge of the main scanning synchronization signal. Further, while the sub-scanning synchronization signal is at the low level, 59 outputs the value held in the register 57. Otherwise, it outputs the value of 58 adder. The 50 latch holds the 59 output at the rising edge of the main scanning synchronization. The adder 58 adds the value held by 50 and the value held by 56 at the falling edge of the main scanning synchronization.

The thus obtained X _S , Y _S are generally irrational numbers like x _D , y _D , and are represented by decimal numbers in actual machines. The value obtained by rounding off this value is used as the input side address of the data to be output. 7 and 8 show the correspondence between addresses on the source side and the destination side. The square grid shows the address grid on the dayside side, and the center of the square is an integer address. The parallelogram grid shows the source side address grid, and the center of the parallelogram is an integer address. The rectangle given by l, m in FIG. 7 is the area centering on x _D , y _D , and A, B are the input destination addresses to be output. 8th
As shown in the figure, a is determined as the output of A. Here, the circuit shown in FIG. 5 exists for the maximum number of output grids included in the area of 1 × m, and operates in parallel. Also,
As shown in FIG. 9, the input side has four scanning line buffers, and while the data is being input to one buffer, the above processing is performed with the already input data to the other three buffers. As the data, the encoded data described above is input as scanning data, and the attended input is determined in the order of the data. Thus, the input / output addresses are associated,
Affine conversion is realized.

As described above, the affine-converted algorithm in this embodiment inputs the raster data on the source side (in this case, there are reading from the file, reading from the reader, and reading from the image memory), and the destination memory. (In the present case, image memory) is stored by random access. Therefore, since the affine conversion hardware is pipelined, sequential input data is sequentially output and executed in the process of data transfer from the file to the image memory, which enables extremely high-speed conversion. . Here, the image data means the above-mentioned compressed data, and the address point means the coordinates in the address space of the compressed data.

When the address after the Affine conversion of the encoded data is determined, the arrangement and exchange of the image data in the block is executed next.

The embodiment will be described below with a 2 × 2 block.

FIG. 10 (a) shows the data in 4 blocks (A, B, C, D) which are original images. For this block, 90 °, 180
The rotation of each block of 270 ° and 270 ° is generated by the rotation process described above, and the address is recorded in the destination memory, and when this is reproduced, the same figure (b), (c),
It becomes like (d). As is clear from the figure, the original image is not faithfully reproduced. Therefore, a method of rotating the pixels inside the block according to the rotation angle is adopted. The same figure (e),
Pixels in the block are 90 °, 180 °, 270 in (f) and (g).
This is an example in which the image is rotated by °, and the fidelity to the original image can be increased. This rotation operation uses the code in FIG. 2 (b),
The 2-bit rotation code can be rewritten and the pattern code can be implemented without tampering.

For rotation at an arbitrary angle, the rotation angle in the block is divided into 90 ° units. Figure 7 shows the rotation angle of 315 ° to 45 °, 45
An example is shown in which the rotation in the block is divided into 0 °, 90 °, 180 ° and 270 ° by dividing into four regions of ° to 135 °, 135 ° to 225 °, 225 ° to 315 °.

FIG. 12 shows an embodiment in which the block-encoded data format shown in FIG. 2 (a) is replaced by the rotation angle in the block and re-formatted. (A) 0 ° (b) 90 ° (c) 180 ° (d) 270 ° , Σ is not changed by rotation, and the order of the grayscale data that follows is changed. (A) When the 0 ° data format is ABCD, (b) 90 ° is BDAC, (c) 180 ° is DCBA, and (d) 270 ° is
It becomes CADB.

FIG. 13 shows an embodiment of the data format conversion circuit in the block. As for the input signals, .sigma. Is held in the buffer 80, and the remaining four grayscale data are held in the buffers 81, 82, 83, 84 separately. A selector signal corresponding to the rotation angle is sent to the selects 85, 86, 87, 89 from a controller (not shown). For example, the rotation angles 0 °, 90 °, 180 °, 270 ° in the block are 0, 1,
If it corresponds to 2 and 3, it becomes a 2-bit select signal. The outputs of buffers 81, 82, 83, 84 are A, B, C, D, selectors 85, 86, 8
Connect to input terminals X, Y, Z, and W of 7,88 so that they correspond to each other. If there is only one select signal and the input terminal Y is output from the output terminals of the respective selectors, B, D, A and C will be output from the buffers 85, 86, 87 and 88, respectively. This output value at buffer 90
When reconnected with σ, the data format as shown in FIG. 12 is completed and output as the output signal of the buffer 90.

The above is the embodiment of the block rotation and the intra-block rotation of the encoded data. That is, in the present invention, the AFFI with rotation
When NE conversion is performed, it is performed by a combination of performing rotation operation using m × m compressed data as −data and performing rotation operation within m × m compressed data. This is accompanied by some deterioration in image quality, so in order to prevent it to a minimum, a small matrix (m _O
Block encoding or vector quantization is performed with × m _O ).

For color-difference signals (I, Q), a relatively large matrix (m1 × m
1: m1> m _O ) and has block coding, vector quantization, or direct average data.

It is necessary to pay attention to the above two points.

Next, the CRT controller 9 will be described.

FIG. 14 is a diagram showing the function of the CRT controller 9, 5 is a compressed image memory, 9 is a CRT controller, and 10
Is a color CRT, 8 is a CPU, and 356 is a parameter register set by the CPU. In the present invention, the memory address X, Y
However, this address can be converted into a one-dimensional address for use. Figure 14
The function of the CRT controller is to create a rectangular area of arbitrary size (xw, yw) having an arbitrary start address (x ₀ , y ₀ ) in the memory 5 and a CRT with a degree of resolution of T _D dot and horizontal X _D dot. It is to display and output to. Any value x ₀ , y ₀ , xw, yw can be restricted not only to the range but also to a multiple of 2 or 4. FIG. 15 shows an example of this CRT controller.
02, 103, 104 are parameter registers, 105, 106 are adders, 1
07 and 108 are selectors, and 109 and 110 are address latches or registers. 112 is a CRT synchronizing circuit, 121 is a horizontal synchronizing signal, 122 is a vertical synchronizing signal, and 123 is a pixel clock. 11
1 is a data latch, 128 is a color signal read from the memory, 124 is a color signal to the CRT, 125 is a horizontal address (X), and 126 is a vertical address (Y). CRT synchronization circuit
A vertical synchronizing signal 122 is generated by 112, and a horizontal synchronizing signal 121 and a pixel clock 123 are further generated. 122 is ON for the address taken in by the Y address latch 110 by 121.
During, the opening price y ₀ 102 is selected depending on 108, so
It becomes y ₀ . Further, the address taken into the X address latch 109 by 123 is the open value x ₀ depending on 107 while 121 is ON.
Since 101 is selected, it becomes x ₀ . In other cases, the X address latch 109 is increased by 1 clock (= 1 dot) by xw / X _D , the memory address is updated, and scanning in the x direction is performed. When the horizontal synchronizing signal 121 is turned ON and the pixel clock is turned ON, the X address latch 109 is x
Reset to ₀ . Further, the Y address latch 110 is increased by yw / Y _{D for} each horizontal synchronization, the memory address is updated, and scanning in the y direction is performed.

FIG. 12 is a diagram showing the function of a CRT controller capable of performing rectangle synthesis on a CRT. The rectangular images 130 and 131 displayed on the CRT 10 are images held as areas 132 and 133 on the memory 5. Now, the image 130 is overlaid on the image 131, and the part of the image 131 on which the image 130 is placed is not displayed. This can be an extension of the configuration shown in FIG. FIG. 17 shows a configuration example. In FIG. 17, reference numerals 134, 135, 136 and 137 are in-region address generation modules, all of which have the same internal structure. Reference numeral 134 is a horizontal address generation module for the area having the highest priority, 135 is also a vertical address generation module, 136 is a horizontal address generation module for the area having the second priority, and 137 is also a vertical address generation module. Reference numeral 148 is a horizontal display address counter, 149 is a vertical display address counter, each of which is a horizontal display address.
Outputs 150 and vertical display address 151. Next, the address generation module will be described. 134 Inside 138
Is a register that holds the display start display address,
139 is a register for holding the display end display address, 152 and 140 are comparators, and a signal 150 is given by the logic circuit of 141.
Is included in the areas of the registers 138 and 139. If included in the area, this address generation module has the right to output the memory address.
However, it is when both X and Y are established, and the address output by these modules 134 and 135 becomes possible when both the signals 153 and 154 become true, and the logic circuit 1
The output enable signal 155 is generated by 59, and the output buffer 147
Are enabled and the contents of the address register 146 are output to the memory horizontal address bus 125. Similarly, the address is output from the module 135 to the memory vertical address bus 126. If the signal in one of the modules 134, 135, ie 153 or 154, goes false, the output of the logic circuit 159 will also go false and the outputs of the modules 134, 135 will be disabled. At this time, module 13 with the second priority
If the in-region signals of 6,137, that is, 156,157 are true, the output of the logic circuit 160 becomes true, and the address output of the modules 136,137 is output to the memory address buses 125,126. When the output of the logic circuit 160 is invalid, the module having the third priority is tested, and thereafter, the address output right is shifted to the one having the lower priority. Of course, when a module having a higher priority than itself acquires the address output right, the higher module will output the address. On the other hand, the output address will be described. Register 143 in module 134
Is a register holding the read start memory address, 14
2 is a register that holds the address increment value, and 145 is 15
A selector configured to input the output of the register 143 to the address register 146 while 3 is false, and 144 is an adder for adding the contents of the increment register 142 to the register 146. When signal 153 goes true, register 146 will register 14
Only the contents of 2 increase with each clock. As mentioned above, the first
With the configuration shown in FIG. 7, rectangular composition can be performed on the CRT screen shown in FIG.

FIG. 18 is a diagram showing the function of the CRT controller, which makes it possible to synthesize and output an arbitrary free-form image on the CRT. In FIG. 18, reference numeral 306 denotes a mask shape record. In the example of FIG. 18, a mask area 162 corresponds to the image area 133 and a mask area 161 corresponds to the image area 132.
Is defined, and a heart-shaped mask is written in the mask area 161. At this time, as shown in the CRT of FIG. 18, the image area 132 is cut out in a heart shape and is superimposed and displayed on the image area 133. The CRT controller 9 that performs such processing is realized by pre-reading the mask shape memory 306 prior to reading the image memory 5.
For example, in this embodiment, the line preceding by 1 in the vertical address direction is read and the mask is controlled. CRT10 in Figure 18
Area of raster image data to be displayed at vertical address y
In the case of 133, the raster is y ₀ from the beginning and the region 132 is y ₁ from the beginning. Mask area 1 on master shape memory 306
The line 62 reads the line y ₀ +1 and the region 161 reads the line y ₁ +1 and makes it possible to read the line y ₀ +1 and provide it to the vertical address y + 1 of the next CRT 10. FIG. 19 shows an example of a CRT controller. FIG. 19 corresponds to the pair of horizontal and vertical modules shown in FIG. In Fig. 19, 161, 162, 16
Reference numeral 7,168 is a register for holding a display address, and similarly to the previous embodiment, the rectangular area on the display designated by this register is controlled by this module. Numeral 173 is a two-line mask data buffer capable of holding a mask for two rasks, which is a feature of this embodiment. The mask data preread by one vertical address is addressed by the counter 174 and input to the logic circuit 176. The logic circuit 176 outputs true when the addresses X _D and Y _D on the display generated by a counter (not shown) are included in the rectangular area to be handled by this module and the mask data is ON. This signal is input to the logic circuit 177, and when the signal PRIOR from the module having a higher priority than this module is true,
The data address buffers 179 and 178 are driven so as to output the memory addresses X _DAT and Y _DAT . The mask data MSKDT remains in the mask data buffer 173 even while the data to be displayed is being transferred.
Continues to read. The mask data to be used is read from the mask shape memory 306, but it is necessary to read it prior to the display data address, so that it is output from the mask address registers 165 and 171 which hold the address one timing ahead of the data address registers 166 and 172. At this time, when the number of modules is plural, mask reading may be performed simultaneously from different modules, but the ENMSK signal is time-divided to give permission to use the mask address bus to prevent collision.
As described above, according to this embodiment, it is possible to superimpose and display an image of an arbitrary shape on a display at high speed and with high precision. Since the CRT controller image data itself according to the present embodiment can be superimposed without rewriting, it is characterized in that it can be processed without holding time.

Next, the function and operation of image editing will be described.

Table 1 shows various image editing functions of this device.

FIG. 20 is a schematic flow of editing operation. Now assume that multiple images are edited and combined. The image input process 200 means an operation and a process of first reading the plurality of images and storing them in a memory for image files. At this time, the above-mentioned compressed data is used to reduce the file capacity. Then, at 204, it is selected whether to perform the component processing or the layout processing. What is the component processing 201?
Perform processing such as conversion In this case, item A in Table 1 is roughly applicable. Layout process 20
2 is a process of deciding the layout of a plurality of image data as finished parts, and performs affine transformation for performing processes such as image rotation, scaling, and movement, and composition processing. Corresponds to item B in Table 1.

Here, the component processing needs to directly convert the image data, but the layout processing only needs to store the layout parameter information (for example, the scaling factor, the position after the rotation angle movement, etc.). Therefore, the layout process may be performed by thinning out the image data, displaying the image data on the display, and extracting the parameters.

At the stage where this processing is completed, the actual image data 203 is next performed. This is to compose and edit the completed part data on the image memory under the layout parameters.
After this processing is completed, the data in the image memory is transferred to the printer and the printer output 206 is performed.

FIG. 21 shows the image input process 200 in detail. First, the document is read by the reader 207, the data is compressed by the above-mentioned compressor (208), and then the file is registered on, for example, a hard disk. . This operation is repeated as long as there are originals, and it ends when there are no more originals to read
0).

FIG. 22 shows the contents of the component processing. First, a processing item selection 211 is performed to determine what to do. First, the color correction 212 transfers the image data from the file (File) to the image memory (since the image memory doubles as the video memory of the display, it is immediately output to the display.), And the color correction is performed while watching the display. To do. This operation does not change the image data in the image memory and
This is done by changing the Look up Table (LUT) to output to (T) (216). The one that stores the LUT when an image that you think is good with this (220).

In the contour correction 213, a space filter arithmetic unit is placed on the cable which is also output to the CRT, and the actual image data is not touched. Then, information on the spatial filter (for example, a well-known Laplacian kernel or coefficient) and the like are recorded (221). The cutout mask 214 is then placed on the Ibit pl in parallel with the image memory.
Rewrite the mask memory of ane. This determines the area of the image and does not touch the actual image data (218).
The other processing is processing called actual data correction 215. This is to directly rewrite the real image data written in the image memory from the CPU and rewrite it. The image data is written, erased, or copied to the real image data. When the above processing is completed, the actual data and the mask data are registered as a hard disk 222 as a file.

FIG. 23 shows the layout process.

First, write the image data from the file to the image memory (223). At this time, the thinned-out data is sufficient as described above, and a plurality of pieces of image data are taken into the image memory. The image data of a plurality of such images are combined and scaled (225) by the CRT controller and output on the display. At this time, the image rotation can be rewritten to another area on the image memory by the raster operation (ROP) by the affine converter 4 (224). On the other hand, the scaling can be performed only by the integer scaling with the CRT controller. Arbitrary scaling is performed by the device 4. Next, data creation 226 of the mask memory for limiting the output image area is performed. The above operation is performed for each image to extract layout parameters (22
7).

FIG. 24 forms final image data based on the above component data and layout parameters. This process can be completely unmanned. First, the image component data overlaid below is processed first. Layout parameter and master data of the first image is AFFINE for pipeline
It is set to a register for conversion, a LUT and a mask memory (this is a 1-bit memory placed in parallel with the image memory). The data from the file is then transferred to the image memory via these pipeline processors. As a result, it is processed by Raster Operation (ROP).

This processing is repeated for the number of component data (ηmax) and overwritten on the image memory (230,
231).

Next, the output to the printer will be described.

The image data of the edited result is created in the image memory and transferred to the printer side. The output state from the image memory differs depending on the printer output method, for example, frame sequential, line sequential, or dot sequential. Such conversion is performed by the converter 12 shown in FIG. Prior to that, the compressed data is decoded into normal pixel data by the decoder 6.

Normally, one printer 7 is connected. However, connecting multiple printers enables higher-speed output, which is particularly important in the publishing and printing fields that require a large amount of output. The image data is stored in this image memory in a format that compresses the density data and restores it to the density data again.Therefore, the hue shift that occurs when connecting to multiple printers (this may depend on the individual printer Different) can be converted / corrected by a Look Up Table (LUT) that moves from one density data to another density data.

(This is usually difficult if the system stores the image memory after it has been binarized.) The adjusting mechanism for the individual printer by the LUT is included in the converter 12.

The color printer 7 outputs an image based on the corrected image data by a normal method such as a dither method.

[Effects of the Invention] As described above, according to the present invention, when a plurality of images represented by coded image data are combined, edit processing parameters can be efficiently extracted, and high-speed display of combined pixels can be performed. It is possible to provide a possible image editing processing device.

[Brief description of drawings]

FIG. 1 is an overall block diagram of the color edit processing apparatus of this embodiment, FIG. 2 is a diagram showing the data format of encoded data, and FIG.
Fig. 4 is a block diagram of the address generator of the affine converter. Fig. 4 is a timing chart of the address generator.
FIG. 5 is a block diagram of the address generation unit, FIG. 6 is a timing chart of the address generation unit, FIGS. 7 and 8 are diagrams showing address correspondence between the original image and the processed image, and FIG. 9 is an affine conversion. Block diagram of the line buffer for use, Fig. 10 is a conceptual diagram of block rotation and rotation inside the block, Fig. 11 is a diagram showing rotation inside the block, Fig. 12 is a diagram showing processing that the code receives by rotation, Fig. 13 Is the block diagram of rotation, 14th
Figures 16, 16 and 18 are conceptual diagrams of the CRT controller, 15
Figures 17, 17 and 19 are block diagrams of the CRT controller,
20, FIG. 21, FIG. 22, FIG. 23, and FIG. 24 are flow charts showing the editing processing procedure.

Claims (1)

[Claims] 1. A storage unit for storing a plurality of images of code data obtained by encoding image data of a first resolution, and a decoding unit for decoding the code data stored in the storage unit. Conversion means for converting the image data of the first resolution decoded by the decoding means into image data of a second resolution lower than the first resolution, and a plurality of images converted by the conversion means Edit processing is performed on the image data of the second resolution corresponding to
A first edit processing means for obtaining image data of the second resolution corresponding to the composite image of the plurality of images; and based on the image data of the second resolution obtained by the first edit processing means, Display means for displaying a composite image of the plurality of images, and a composite image displayed by the display means for the image data of the first resolution corresponding to the plurality of images decoded by the decoding means Second edit processing means for performing edit processing according to the edit parameter used by the first edit processing means to obtain the image data of the first resolution corresponding to the composite image of the plurality of images. An image edit processing device comprising: