JPH0677952A - Secret talk transmitter - Google Patents

Secret talk transmitter

Info

Publication number
JPH0677952A
JPH0677952A JP4229631A JP22963192A JPH0677952A JP H0677952 A JPH0677952 A JP H0677952A JP 4229631 A JP4229631 A JP 4229631A JP 22963192 A JP22963192 A JP 22963192A JP H0677952 A JPH0677952 A JP H0677952A
Authority
JP
Japan
Prior art keywords
data
encryption
encryption code
circuit
storage element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4229631A
Other languages
Japanese (ja)
Inventor
Kazuhiko Tamesue
和彦 爲末
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP4229631A priority Critical patent/JPH0677952A/en
Publication of JPH0677952A publication Critical patent/JPH0677952A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To provide a secret talk transmitter which generates a ciphering code from the contents of plural stored slots in the case of cable or radio data communication for transmitting data decomposed into the unit of a slot. CONSTITUTION:On the transmission side, n-th bit data of stored digital data decomposed for the unit of a slot are stored in a shift register 4 by an n-th bit select circuit 3, and the ciphering code is generated by a ciphering code generating circuit 6. Further, the ciphering code generated there and the digital data extracted from a memory cell 1 are logically calculated and turned to secret talk. Afterwards, the ciphering code is extracted from the n-th bit of the received and stored digital data on the reception side, and decoding logical arithmetic is performed in the inverse order.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明はスロット単位に分割され
たデジタルデータを対象として、有線または無線通信に
おいて伝送を行う場合の、送信者または受信者以外の第
三者による通信内容の容易な知得を防止することを目的
とした秘話伝送装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention makes it possible to easily know the contents of communication by a third party other than the sender or the receiver when transmitting by wire or wireless communication for digital data divided into slots. The present invention relates to a confidential transmission device intended to prevent gains.

【0002】[0002]

【従来の技術】従来の秘話伝送装置では暗号化符号に相
当する部分を加入者側で設定し排他論理和をとることで
暗号化されたデータを復号化していた(たとえば特開昭
63ー237633号公報参照)。
2. Description of the Related Art In a conventional confidential communication transmission device, a portion corresponding to an encryption code is set on the subscriber side and an exclusive OR is taken to decrypt the encrypted data (for example, Japanese Patent Laid-Open No. 63-237633). (See the official gazette).

【0003】[0003]

【発明が解決しようとする課題】しかしながら、上記の
ような従来の方式では何等かの原因で暗号化符号が明か
になれば一意的に復号化が可能になるため、秘話方式と
しては安全性に欠ける面があった。そこで本発明は前記
の問題点を改良し、かつ既存の半導体素子で実現が可能
なハードウェア構成をもつ低コストな秘話伝送装置を提
供することを目的とする。
However, in the conventional system as described above, if the encrypted code becomes clear for some reason, the decryption can be uniquely performed. There was a chipped surface. Therefore, an object of the present invention is to provide a low-cost confidential communication transmission device that improves the above problems and has a hardware configuration that can be realized by an existing semiconductor device.

【0004】[0004]

【課題を解決するための手段】この目的を達成するため
本発明の秘話伝送装置は、送信側では蓄積データのスロ
ットの第nビットのデータ列から暗号化符号を抽出する
ことで暗号化論理演算するための暗号化符号を蓄積デー
タ自身より生成する暗号化符号抽出手段を有し、受信側
では受信した蓄積データの第nビットのデータ列によ
り、復号化論理演算するための暗号化符号を生成する暗
号化符号復元手段を有する構成となっている。
In order to achieve this object, the confidential transmission apparatus of the present invention uses a cryptographic logical operation by extracting a cryptographic code from an n-th bit data string of a slot of accumulated data on the transmitting side. The receiving side has an encryption code extracting means for generating an encryption code for performing the decoding from the stored data itself, and the receiving side generates an encryption code for a decryption logical operation based on the n-th bit data string of the received stored data. It has a configuration including an encryption code restoring means for performing.

【0005】[0005]

【作用】本発明は上記構成において、スロット単位に分
割されたデータの第nビットは次のデータの第nビット
とは相関が低いことを利用して暗号化論理演算の暗号化
生成符号として用いることで復号の際には暗号化符号生
成に用いたデータがすべてそろった時点で復号のための
暗号化符号が得られるように作用する。
According to the present invention, in the above construction, the fact that the nth bit of the data divided into slot units has a low correlation with the nth bit of the next data is used as the encryption generation code for the encryption logical operation. Therefore, at the time of decryption, the encryption code for decryption is obtained when all the data used for generating the encryption code are available.

【0006】[0006]

【実施例】以下、本発明の秘話伝送装置の一実施例につ
いて図面を用いて説明する。図1の構成要素を説明する
と、送信側において、1はデータを蓄積するための記憶
素子、2は記憶素子にデータを書き込み、または読みだ
しを制御するアドレス発生回路、3はスロット単位に分
割されたデータから第nビットをセレクトしてシフトレ
ジスタ4へその値の書き込みを制御するクロックを発生
する第nビットセレクト回路、6はシフトレジスタ4で
得られた第nビットデータ列をもとにタイミング発生回
路5のタイミングにより論理演算を実行し暗号化符号を
生成する暗号化符号生成回路、7は記憶素子1より読み
だされたデータを暗号化符号生成回路6で生成した暗号
化符号をもとにタイミング発生回路5のタイミングによ
り暗号化論理演算する暗号化回路、8は暗号化されたデ
ータを伝送媒体にて伝送するため伝送媒体に適した変調
を行う変調回路、9は電気信号を電波に変換して送信を
行う送信回路である。上記の第nビットセレクト回路3
とシフトレジスタ4と暗号化符号生成回路6をあわせて
暗号化符号抽出手段とする。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the confidential transmission apparatus of the present invention will be described below with reference to the drawings. The components of FIG. 1 will be described. On the transmitting side, 1 is a storage element for accumulating data, 2 is an address generation circuit for controlling writing or reading of data in the storage element, and 3 is divided into slots. The n-th bit select circuit for selecting the n-th bit from the selected data and generating the clock for controlling the writing of the value to the shift register 4, and 6 is a timing based on the n-th bit data string obtained by the shift register 4. An encryption code generation circuit that executes a logical operation at the timing of the generation circuit 5 to generate an encryption code, and 7 is based on the encryption code generated by the encryption code generation circuit 6 for the data read from the storage element 1. An encryption circuit that performs an encryption logical operation according to the timing of the timing generation circuit 5, and 8 is suitable for a transmission medium because the encrypted data is transmitted by the transmission medium. Modulation circuit for modulating the, 9 is a transmission circuit for transmitting by converting electric signals radio waves. The nth bit select circuit 3
The shift register 4 and the encryption code generation circuit 6 together form an encryption code extraction means.

【0007】続いて受信側において、10は電波を受信
し電気信号へ変換し送受信間で発生するエラーの訂正を
行う受信回路、11は変調回路8でかけた変調を復調し
暗号化回路7の出力と等しい暗号化データを再現する復
調回路、12は復調されたデータを蓄積する記憶素子、
13は記憶素子12にデータの書き込みまたは読みだし
を制御するアドレス発生回路およびタイミング発生回
路、14はスロット単位に分割されたデータから第nビ
ットにある暗号化符号成分をセレクトしてシフトレジス
タ15へその値の書き込みを制御するクロックを発生す
る第nビットセレクト回路、17はシフトレジスタ15
で得られた暗号化符号より第nビットデータ列を再現す
る暗号化符号復号化回路、18は記憶素子12より読み
だされた暗号化データをシフトレジスタ15で再現した
暗号化符号をもとにタイミング発生回路16のタイミン
グで復号化論理演算する復号化回路である。上記の第n
ビットセレクト回路14、シフトレジスタ15および暗
号化符号復号回路17を併せて暗号化符号復元手段とす
る。
Next, on the receiving side, 10 is a receiving circuit that receives radio waves and converts them into electric signals to correct errors that occur during transmission and reception, and 11 demodulates the modulation applied by the modulation circuit 8 and outputs from the encryption circuit 7. A demodulation circuit for reproducing encrypted data equal to, a storage element 12 for storing demodulated data,
Reference numeral 13 denotes an address generation circuit and timing generation circuit for controlling writing or reading of data in the storage element 12, and 14 selects an encryption code component at the nth bit from the data divided in slot units and shifts it to the shift register 15. An nth bit select circuit for generating a clock for controlling the writing of the value, 17 is a shift register 15
An encryption code decoding circuit that reproduces the n-th bit data string from the encryption code obtained in step 18 is based on the encryption code that the encrypted data read from the storage element 12 is reproduced by the shift register 15. This is a decoding circuit that performs a decoding logical operation at the timing of the timing generation circuit 16. The nth above
The bit select circuit 14, the shift register 15, and the encryption code decoding circuit 17 together form an encryption code restoring means.

【0008】以上のような構成要素より成り、つぎにそ
の構成要素相互の関連と動作を説明すると、送信側は記
憶素子1およびシフトレジスタ4へスロット単位に分解
したデータを入力する。記憶素子1はアドレス発生回路
2によって制御され、所定のアドレスにデータを蓄積す
る。一方、記憶素子1へ入力するデータのうち第nビッ
トを第nビットセレクト回路3で制御するタイミングに
よりシフトレジスタ4へ順次入力する。やがてシフトレ
ジスタの段数分のデータの入力を完了すると暗号化符号
生成回路6での暗号化符号生成に必要な第nビットデー
タ列が得られ、その論理変換は図5(a)に示す各々の
ビットの反転、図5(b)に示すビット列の並べ変え、
図6(a)に示す記憶素子を用いたもの、図6(b)に
示す使用者が定義した暗号コードとの論理演算によるも
の、またはこれらの組合せにて暗号化符号を生成する。
そのタイミングはタイミング発生回路5で制御され、暗
号化符号の生成を完了すると暗号化回路7にて記憶素子
1から読みだしたデータと論理演算を行い、また第nビ
ットのデータについては暗号化符号自身を用いて、デー
タの暗号化が完了する。
[0008] The constituent elements as described above will be described. Next, the mutual relation and operation of the constituent elements will be described. The transmitting side inputs the data decomposed into the storage element 1 and the shift register 4 in slot units. The storage element 1 is controlled by the address generation circuit 2 and stores data at a predetermined address. On the other hand, the nth bit of the data input to the storage element 1 is sequentially input to the shift register 4 at the timing controlled by the nth bit select circuit 3. Eventually, when the input of data for the number of stages of the shift register is completed, the n-th bit data string necessary for the encryption code generation in the encryption code generation circuit 6 is obtained, and its logical conversion is as shown in FIG. Bit inversion, rearrangement of the bit string shown in FIG.
An encryption code is generated by using the storage element shown in FIG. 6A, by a logical operation with a user-defined encryption code shown in FIG. 6B, or by a combination thereof.
The timing is controlled by the timing generation circuit 5, and when the generation of the encryption code is completed, the encryption circuit 7 performs a logical operation with the data read from the storage element 1, and the data of the nth bit is the encryption code. The data encryption is completed by using itself.

【0009】ここで、暗号化回路の論理演算の方法とし
ては図7に示すように記憶素子1からのデータと暗号化
符号生成回路6で生成した暗号化符号との排他論理和を
とって暗号化データを得る方法がある。暗号化されたデ
ータは変調回路8にて伝送媒体に適した変調をうけ送信
回路9で電波へと変換され送信される。
Here, as the method of the logical operation of the encryption circuit, as shown in FIG. 7, the data from the storage element 1 and the encryption code generated by the encryption code generation circuit 6 are exclusive ORed and encrypted. Method is available. The encrypted data is subjected to modulation suitable for the transmission medium in the modulation circuit 8 and converted into radio waves in the transmission circuit 9 for transmission.

【0010】受信側では、受信回路10で目的の電波を
受信し適当なレベルへの増幅および送受信間で発生する
伝送エラーを訂正して復調回路11へ送られ、ここで変
調器8に入力する時点と等しいデータを再現する。記憶
素子12はアドレス発生回路13で制御され、所定のア
ドレスにデータを蓄積する。一方、記憶素子12へ入力
するデータの第nビットを第nビットセレクト回路14
で制御するタイミングでシフトレジスタ15へ順次入力
する。やがてシフトレジスタの段数分のデータの入力を
完了するとその出力には復号化に必要な第nビットデー
タ列が得られ、その第nビットデータ列と記憶素子12
から読みだしたデータとの排他論理演算を復号化回路1
8で行い、第nビットデータ列自身は暗号化符号復号回
路17で図5(a),(b)、図6(a),(b)に対
応した方法で復号され、記憶素子1に入力されたデータ
を再構成する。そのタイミングはタイミング発生回路1
6で制御される。
On the receiving side, the receiving circuit 10 receives a target radio wave, amplifies it to an appropriate level, corrects a transmission error occurring between transmission and reception, and sends it to the demodulation circuit 11, where it is input to the modulator 8. Reproduce data equal to the time point. The storage element 12 is controlled by the address generation circuit 13 and stores data at a predetermined address. On the other hand, the nth bit of the data input to the storage element 12 is set to the nth bit select circuit 14
Are sequentially input to the shift register 15 at the timing controlled by. Eventually, when the input of data for the number of stages of the shift register is completed, the n-th bit data string required for decoding is obtained at the output, and the n-th bit data string and the storage element 12 are obtained.
Decoding circuit 1 for exclusive logic operation with data read from
8 and the n-th bit data string itself is decrypted by the encryption code decoding circuit 17 by a method corresponding to FIGS. 5 (a), 5 (b), 6 (a) and 6 (b), and is input to the storage element 1. The reconstructed data. The timing is the timing generation circuit 1
Controlled by 6.

【0011】なお上記実施例では無線通信の場合につい
て説明したが、有線通信の場合にも適用できることは当
然である。また送信側での第nビットデータ列抽出手段
として、上記説明では第nビットデータ列の抽出は記憶
素子への格納と平行してシフトレジスタ4へ入力した
が、それに代えて図2のように記憶素子にいったん蓄積
した後、その中から第nビットデータ列を選択抽出して
もよい。また図3,図4のように記憶素子1に入力する
データまたは記憶素子1に蓄積したデータのアドレスを
検出手段としてアドレスデコーダとラッチで構成する第
nビット抽出回路19を用いて第nビットのデータを選
択抽出してもよい。受信側における第nビットデータ列
抽出手段も送信側で挙げた構成またはその組合せを用い
てもよいのは当然である。
In the above embodiment, the case of wireless communication has been described, but it goes without saying that it is also applicable to wired communication. Further, as the n-th bit data string extracting means on the transmitting side, in the above description, the extraction of the n-th bit data string is input to the shift register 4 in parallel with the storage in the storage element, but instead, as shown in FIG. After being once stored in the storage element, the n-th bit data string may be selectively extracted from it. Further, as shown in FIGS. 3 and 4, the n-th bit extraction circuit 19 including an address decoder and a latch is used as a detection means for detecting the address of the data input to the storage element 1 or the address of the data stored in the storage element 1. Data may be selectively extracted. As a matter of course, the n-th bit data string extracting means on the receiving side may also use the configuration mentioned on the transmitting side or a combination thereof.

【0012】図3,図4の場合暗号化符号抽出手段は第
nビット抽出回路19と、暗号化符号生成回路6とより
なり、また暗号化符号復元手段は第nビット抽出回路1
9と、暗号化符号復号回路17とよりなるものとする。
In the case of FIGS. 3 and 4, the encryption code extracting means is composed of the nth bit extracting circuit 19 and the encryption code generating circuit 6, and the encryption code restoring means is the nth bit extracting circuit 1.
9 and the encryption / decryption circuit 17.

【0013】さらに送信側および受信側の第nビットセ
レクト回路3,14または第nビット抽出回路19を外
部の制御信号により制御して第nビット目の”n”を任
意に変化できるようにすれば、その秘話性をさらに高め
ることができる。
Further, the nth bit select circuits 3 and 14 on the transmitting side and the nth bit extracting circuit 19 on the receiving side are controlled by an external control signal so that "n" of the nth bit can be arbitrarily changed. If so, the confidentiality can be further enhanced.

【0014】[0014]

【発明の効果】以上説明したように本発明によれば、複
数のスロット単位のデータを用いて暗号化符号を生成し
暗号化論理演算を行い、かつ暗号化符号生成に用いたす
べてのデータの伝送が正確に完了しないと復号化できな
いことから、確度の高い秘話性を有し、かつ伝送する情
報量を増加させない秘話伝送装置を実現することができ
る。
As described above, according to the present invention, an encryption code is generated by using a plurality of slot unit data, an encryption logical operation is performed, and all data used in the encryption code generation is generated. Since it cannot be decoded unless the transmission is completed correctly, it is possible to realize a confidential transmission device that has highly accurate confidentiality and does not increase the amount of information to be transmitted.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例の秘話伝送装置のブロック図FIG. 1 is a block diagram of a confidential transmission device according to an embodiment of the present invention.

【図2】同じく他の実施例のブロック図FIG. 2 is a block diagram of another embodiment.

【図3】同じく他の実施例のブロック図FIG. 3 is a block diagram of another embodiment.

【図4】同じくさらに他の実施例のブロック図FIG. 4 is a block diagram of yet another embodiment.

【図5】(a)同じくその各々のビットの反転による暗
号化符号生成回路の論理図 (b)同じくそのビット列の並べ替えによる暗号化符号
生成回路の論理図
FIG. 5 (a) is a logic diagram of an encryption code generation circuit by similarly inverting each bit thereof. (B) is a logic diagram of an encryption code generation circuit by similarly rearranging the bit strings.

【図6】(a)同じくその記憶素子を用いる暗号化符号
生成回路の論理図 (b)同じくその使用者が定義した暗号コードとの論理
演算を用いる暗号化符号生成回路の論理図
FIG. 6A is a logic diagram of an encryption code generation circuit that also uses the storage element; FIG. 6B is a logic diagram of an encryption code generation circuit that also uses a logical operation with the encryption code defined by the user.

【図7】同じくその暗号化回路の論理図FIG. 7 is a logic diagram of the encryption circuit of the same.

【符号の説明】[Explanation of symbols]

1 記憶素子 2 アドレス発生回路 3 第nビットセレクト回路 4 シフトレジスタ 5 タイミング発生回路 6 暗号化符号生成回路 7 暗号化回路 8 変調回路 9 送信回路 10 受信回路 11 復調回路 12 記憶素子 13 アドレス発生回路 14 第nビットセレクト回路 15 シフトレジスタ 16 タイミング発生回路 17 暗号化符号復号回路 18 復号化回路 19 第nビット抽出回路 1 Storage Element 2 Address Generation Circuit 3 nth Bit Select Circuit 4 Shift Register 5 Timing Generation Circuit 6 Encryption Code Generation Circuit 7 Encryption Circuit 8 Modulation Circuit 9 Transmission Circuit 10 Reception Circuit 11 Demodulation Circuit 12 Storage Element 13 Address Generation Circuit 14 Nth bit select circuit 15 shift register 16 timing generation circuit 17 encryption code decoding circuit 18 decoding circuit 19 nth bit extraction circuit

Claims (6)

【特許請求の範囲】[Claims] 【請求項1】送信側において記憶素子と、前記記憶素子
の書き込みおよび読みだしを制御するアドレス発生回路
と、入力データから第nビットデータ列を抽出し論理演
算による暗号化符号を生成する暗号化符号抽出手段と、
前記暗号化符号抽出手段で生成した暗号化符号をもとに
前記記憶素子より読み出されたデータの暗号化論理演算
を行う暗号化回路とを有し、受信側において前記暗号化
回路の出力データを蓄積する記憶素子と、前記記憶素子
の書き込みおよび読みだしを制御するアドレス発生回路
と、復調したデータのうち第nビットデータ列を用いて
復号を行う復号化回路と、前記第nビットデータ列すな
わち暗号化符号自身を復号する暗号化符号復元手段回路
とを有し、送信側ではスロット単位に分割蓄積されたデ
ータの第nビットデータ列を前記暗号化符号抽出手段で
暗号化生成符号として抽出して暗号化論理演算を行い、
受信側では受信蓄積したスロットの第nビットのデータ
列から暗号化符号復元手段により暗号化符号を抽出して
復号化論理演算を行うように構成してなる秘話伝送装
置。
1. A storage device at a transmitting side, an address generation circuit for controlling writing and reading of the storage device, and an encryption for extracting an n-th bit data string from input data and generating an encryption code by a logical operation. Code extraction means,
An encryption circuit for performing an encryption logical operation on the data read from the storage element based on the encryption code generated by the encryption code extraction means, and the output data of the encryption circuit on the receiving side. A storage element that stores the data, an address generation circuit that controls writing and reading of the storage element, a decoding circuit that performs decoding using the nth bit data string of the demodulated data, and the nth bit data string. That is, it has an encryption code restoring means circuit for decoding the encryption code itself, and the transmitting side extracts the n-th bit data string of the data divided and accumulated in slot units as the encryption generation code by the encryption code extracting means. And perform an encrypted logical operation,
A secret-speech transmission apparatus configured so that the receiving side extracts an encryption code from the n-th bit data string of the slot received and accumulated by the encryption code restoring means and performs a decryption logical operation.
【請求項2】入力したデータから、またはいったん記憶
素子に蓄積したデータからシフトレジスタを介して第n
ビットデータ列を抽出する請求項1記載の秘話伝送装
置。
2. The n-th data from the input data or the data once stored in the storage element via a shift register.
The confidential transmission device according to claim 1, which extracts a bit data string.
【請求項3】記憶素子に入力するデータのアドレスを検
出手段として第nビットデータ列を抽出する請求項1記
載の秘話伝送装置。
3. The confidential transmission apparatus according to claim 1, wherein the n-th bit data string is extracted by using the address of the data input to the storage element as the detection means.
【請求項4】記憶素子に蓄積したデータのアドレスを検
出手段として第nビットデータ列を抽出する請求項1記
載の秘話伝送装置。
4. The confidential transmission apparatus according to claim 1, wherein the n-th bit data string is extracted by using the address of the data stored in the storage element as the detecting means.
【請求項5】暗号化符号抽出手段の暗号化符号生成回路
または暗号化符号復元手段の暗号化符号復号回路の論理
演算を行う部分に記憶素子を用いる請求項1記載の秘話
伝送装置。
5. The secret channel transmission device according to claim 1, wherein a storage element is used in a portion for performing a logical operation of the encryption code generation circuit of the encryption code extraction means or the encryption code decoding circuit of the encryption code restoration means.
【請求項6】送信側および受信側の第何ビット目のデー
タ列を抽出するかを外部からの制御信号により変化でき
る請求項1記載の秘話伝送装置。
6. The confidential transmission device according to claim 1, wherein the number of the data bit of the transmitting side and the receiving side to be extracted can be changed by a control signal from the outside.
JP4229631A 1992-08-28 1992-08-28 Secret talk transmitter Pending JPH0677952A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4229631A JPH0677952A (en) 1992-08-28 1992-08-28 Secret talk transmitter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4229631A JPH0677952A (en) 1992-08-28 1992-08-28 Secret talk transmitter

Publications (1)

Publication Number Publication Date
JPH0677952A true JPH0677952A (en) 1994-03-18

Family

ID=16895228

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4229631A Pending JPH0677952A (en) 1992-08-28 1992-08-28 Secret talk transmitter

Country Status (1)

Country Link
JP (1) JPH0677952A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7561693B2 (en) 2002-08-07 2009-07-14 Pantech & Curitel Communications, Inc. Method for automatically entering into secure communication mode in wireless communication terminal

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7561693B2 (en) 2002-08-07 2009-07-14 Pantech & Curitel Communications, Inc. Method for automatically entering into secure communication mode in wireless communication terminal

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