RU2138126C1 - Method and device for ciphering/deciphering messages by hashing function - Google Patents

Abstract

FIELD: electric communications; secret communications engineering. SUBSTANCE: method involves pre-shaping of noise-immune cryptogram blocks, their hashing, comparison with information block of a-th symbols, selection of most close one among them, and transmission of messages of noise-immune cryptogram block corresponding to chosen hashed noise-immune cryptogram block to receiving party, as well as hashing of identified noise-immune cryptogram block received. Device implementing this method has in transmitting center additionally introduced selection unit, storage module for noise-immune cryptogram blocks, and commutator; in receiving center it has identification unit, storage module for noise-immune cryptogram blocks, and switch. Errors are detected during transmission of ciphered messages and provision is made for their retransmission in case errors are detected in them upon reception. EFFECT: improved confidence of ciphered messages over noise-bearing channels. 4 cl, 14 dwg

Description

 The proposed technical solutions are united by a single inventive concept and relate to the field of telecommunications, namely, the secret (confidential) communication technique, which provides encrypted transmission of redundant messages, such as digitally converted speech, sound, television, fax, etc. messages.

 The proposed method and device for encrypting / decrypting messages with a hashing function can be used to exclude unauthorized access of third parties to messages transmitted by the sender to the recipient of messages via discrete communication channels, while increasing the reliability of the transmission under the influence of transmission errors. The term "encryption" refers to the conversion of messages using a secret key known to the sender and recipient of messages on the transmission and the reverse transformation on reception, eliminating or significantly complicating unauthorized access to the transmitted messages of third parties who do not know the secret key. The term "cryptogram" means an encrypted message transmitted over a communication channel.

 Known methods for encrypting / decrypting messages are described, for example, in the book: J. Messi, "Introduction to Modern Cryptology." TIIER, 1988, v. 76, No. 5, p. 34. They consist in the formation by the sender of messages of the encryption sequence from the secret key, the elementwise addition of the next element of the message sequence with the next element of the encryption sequence, transmission of the encrypted sequence to the message recipient, and the decryption of the messages by the recipient sequences from the secret key and decryption of the message sequence by elementwise subtraction of the encrypted sequence from the next element with the corresponding element of the encryption sequence. A disadvantage of the known methods of encrypting / decrypting messages is the low reliability of the transmission of encrypted messages over interference channels due to the inability to detect transmission errors. By the type of received encrypted message, it is impossible to determine whether it is distorted by transmission errors, since in the known methods of encrypting / decrypting messages, an encrypted message of any kind can be generated.

 Known devices for encrypting / decrypting messages are described, for example, in the book: W. Diffie, M. Hellman, "Security and Immunity." TIIER, 1979, v. 67, N3, p. 55. The device includes transmitting and receiving nodes. The transmitting node consists of an encryption sequence overlay unit, a secret key memory unit, a conversion unit, and a counter. The encryption sequence at the output of the conversion unit is formed depending on the value of the secret key and the current state of the counter. In the block of imposition of the encryption sequence, element-by-element summation of the message sequence with the encryption sequence is performed. The encrypted message is transmitted over the communication channel. In the receiving node, consisting of a block for subtracting the encryption sequence, a secret key memory block, a conversion block, and a counter, an encryption sequence identical to the encryption sequence generated in the transmitting node is synchronously generated. Decryption of the message is performed in the block subtracting the encryption sequence by elementwise subtraction of the encrypted sequence from the received sequence of the encrypted message. A disadvantage of the known message encryption / decryption devices is the low reliability of the transmission of encrypted messages over interference channels due to the inability to detect transmission errors. By the type of received encrypted message, it is impossible to determine whether it is distorted by transmission errors, since in known message encryption / decryption devices an encrypted message of any kind can be generated.

The hashing function closest in technical essence to the claimed method of message encryption / decryption is the method described in US Pat. No. 5,483,598 to IPC ⁶ H 04 L 9/20 of January 9, 1996. The prototype method of encrypting / decrypting messages with a hashing function consists in preliminary generating a hash function, a secret key and a starting block of binary characters, transmitting a secret key and a starting block of binary characters between the sender and recipient of messages, breaking the message into information blocks of binary characters, and hashing by the sender of messages of the starting block of binary characters by hash function and secret key, encryption of the first information block of binary characters with putting it with a hashed binary character start block, transmitting the binary character cryptogram block to the message recipient, the student hashes the messages of the binary character start block by the hash function and secret key, decrypts the received cryptogram block by subtracting the hashed binary character start block from it and thereby recovering the first information block binary characters. To encrypt the second and subsequent information blocks of binary symbols, the previous cryptogram block is hashed by the hash function and secret key, and then the next information block of binary symbols is encrypted by adding the next hashed block of binary symbols. The next block of cryptograms is transmitted to the message recipient, who similarly hashes the previous received block of cryptogram by hashing function and secret key, and then decrypts the next received block of cryptogram by subtracting the next hashed block of binary characters from it, and then re-hashing the blocks of cryptograms and the subsequent actions until as long as the next information blocks of binary characters.

 The disadvantage of the prototype of the claimed method of encrypting / decrypting messages with a hashing function is the low reliability of the transmission of encrypted messages over interference channels due to the inability to detect transmission errors. By the type of received encrypted message, it is impossible to determine whether it is distorted by transmission errors, since in the known methods of encrypting / decrypting messages, an encrypted message of any kind can be generated by a hashing function.

The hashing function closest in technical essence to the claimed message encryption / decryption device is the device described in US patent N 548 3598 IPC ⁵ H 04 L 9/20 of January 9, 1996. A known prototype device includes transmitting and receiving nodes. At the transmitting node, the input of the information block memory module is the input of the device. The secret key input of the hash block is connected to the output of the secret key memory module. The first information input of the hash block is connected to the output of the switching block, the first information input of the switching block is connected to the output of the memory module of the start block, the second information input of the switching block is connected to the output of the memory module of the previous cryptogram block. The output of the information block memory module is connected to the first adder input modulo 2, the hash block output is connected to the second adder input modulo 2. The adder modulo 2 output is connected to the input of the cryptogram block memory module and in parallel with the memory module input of the previous cryptogram block. The output of the memory module of the cryptogram block is connected to the input of the communication channel. At the receiving node, the input of the memory module of the received cryptogram block is connected to the output of the communication channel. The secret key input of the hashing block is connected to the output of the secret key memory module, the first information input of the hash block is connected to the output of the switching block, the first information input of the switching block is connected to the output of the starting block memory module, the second information input of the switching block is connected to the output of the memory module of the previous received block cryptograms. The output of the memory module of the received cryptogram block is connected to the first adder input modulo 2 and in parallel with the memory module input of the previous received cryptogram block. The modulator output is the output of the device.

 The disadvantage of the prototype of the claimed device for encrypting / decrypting messages with an encrypting function is the low reliability of the transmission of encrypted messages over channels with interference due to the inability to detect transmission errors. It is impossible to determine by the type of received encrypted message whether it is distorted by transmission errors, since in known message encryption / decryption devices a hashed function can generate an encrypted message of any kind.

 The aim of the invention of the claimed technical solutions is to develop a method of encrypting / decrypting messages with a hashing function and a device that implements it, providing increased reliability of encrypted message transmission over interference channels due to detection of transmission errors and retransmission of encrypted messages received with an error.

 This goal is achieved by the fact that in the known method of encrypting / decrypting messages with a hashing function, which consists in preliminarily generating a hash function, a secret key and a starting block of binary characters, transmitting between the sender and receiver of messages a secret key and a starting block of binary characters, breaking the message into information blocks characters, binary sender message hashing of the sender of messages, transmission of binary character blocks to the message recipient, and hashing are accepted x blocks of binary symbols, additionally pre-form N noise-resistant blocks of cryptograms, where N> 2. The formation of N noise-resistant blocks of cryptograms is performed by multiplying each of the N blocks of binary symbols by the generating matrix of the binary noise-immunity code. The noise-resistant blocks of cryptograms are hashed by the hashing function, the secret key and the starting block of binary symbols, each i-th one is compared, where i = 1, 2, ..., N, the hashed noise-resistant block of the cryptogram with the first information block of q-decimal symbols, where q > 2. Among the N hashed noise-resistant blocks of cryptograms, the one closest to the first information block of q-ary symbols is selected. For comparison, each i-th, where i = 1, 2,. . . , N, of the hashed error-correcting block of the cryptogram with the first information block of q-ary symbols from the value of each q-ary sample of the i-th hashed noise-resistant block of the cryptogram, the corresponding q-ary sample of the first information block of q-symbol symbols is subtracted for each i-th the hashed error-correcting cryptogram block the absolute values of the resulting differences are summed, and the closest hashed noise-resistant cryptogram block to the first information block of q-ary characters is selected They shout the corresponding minimum sum of the differences obtained. The noise-resistant cryptogram block corresponding to the selected hashed noise-resistant cryptogram block is transmitted via the forward communication channel to the message recipient, the received noise-resistant cryptogram block with N noise-resistant cryptogram blocks is identified, and if it is not identified, the received noise-resistant cryptogram block is erased and the signal is transmitted back to retransmission to the message recipient of an error-correcting cryptogram block corresponding to the selected hashed th block noise immunity cryptogram. The received identified error-correcting cryptogram block is hashed by a hash function, a secret key and a starting block of binary symbols. Each N noise-resistant block of cryptograms is re-hashed using the hashing function, secret key and noise-resistant block of cryptogram corresponding to the hashed noise-resistant block of cryptogram selected in the previous step, each i-th one is compared, where i = 1,2, .., N, the hashed noise-resistant block of cryptogram is the next information block of q-ary symbols, among the N hashed noise-resistant blocks of cryptograms, the one closest to the next information block of q-ary symbols is selected. To compare each i-th, where i = 1, 2, ..., N, of the hashed error-correcting block of the cryptogram with the next information block of q-ary symbols, the corresponding value is subtracted from the value of each q-th sample of the i-th hashed noise-resistant block of the cryptogram q-ary counting of the next information block of q-ary characters, for each i-th hashed noise-tolerant cryptogram block, the absolute values of the resulting differences are summed, and the closest hashed noise-resistant cryptogram block to the next To the information block of q-ary characters, the corresponding minimum sum of the differences is selected. A noise-resistant cryptogram block corresponding to the selected hashed noise-resistant cryptogram block is transmitted via a direct communication channel to the message recipient. The received noise-resistant cryptogram block is identified with N noise-resistant blocks of cryptograms, and if it is not identified, the received noise-resistant block of the cryptogram is erased and a control signal is transmitted via the reverse communication channel for retransmission to the message recipient of the noise-resistant block of the cryptogram corresponding to the selected hashed noise-resistant cryptogram block. The received identified error-correcting cryptogram block is hashed by the hashing function, the secret key, and the previous received identified error-correcting cryptogram block is hashed. Re-hashing of noise-resistant blocks of cryptograms and subsequent actions are performed until the next information blocks of q-ary characters arrive.

 The aforementioned new set of actions performed by transmitting via the communication channel pre-formed noise-resistant blocks of cryptograms can improve the reliability of transmission by detecting transmission errors and retransmitting encrypted messages received with an error, without introducing additional redundancy in the transmitted encrypted messages.

 This goal is achieved by the fact that in the known device for encrypting / decrypting messages with a hash fiction containing a data unit memory module on the transmitting node, the input of which is the device input, a hash unit whose secret key input is connected to the output of the secret key memory module. The first input of the hash block is connected to the output of the switching block, the first information input of the switching block is connected to the output of the start block memory module, the second information input of the switching block is connected to the output of the memory module of the previous cryptogram block, the memory module of the cryptogram block, the information output of which is connected to the direct channel input communication. At the receiving node, the memory module of the received cryptogram block, the input of which is connected to the output of the direct communication channel, the hash block, the secret key of which is connected to the output of the secret key memory module. The first information input of the hash block is connected to the output of the switching block, the first information input of the switching block is connected to the output of the memory module of the start block, the second information input of the switching block is connected to the output of the memory module of the previous received cryptogram block. At the transmitting node, a selection block is additionally introduced, the first information input of which is connected to the memory module of the information block, the second information input of the selection block is connected to the output of the hashing block, the output of the selection block is connected to the information input of the memory module of noise-resistant cryptogram blocks, the output of which is connected to the information input of the switch , the first information output of the switch is connected to the second information input of the hash block, the second information output of the switch is connected to the information input of the memory module of the cryptogram block and in parallel to the input of the memory module of the previous cryptogram block. The first control input of the cryptogram block memory module is connected to the output of the reverse communication channel. An identification block is additionally introduced at the receiving node, the first information input of which is connected to the output of the memory module of the received cryptogram block, the second information input of the identification block is connected to the output of the memory module of the noise-resistant cryptogram blocks, the first control output of the identification block is connected to the control input of the memory module of the noise-resistant cryptogram blocks, the second control output of the identification unit is connected to the control input of the key, the third control output of the identification unit is connected nen with the input of the reverse communication channel and in parallel with the input of the erasing of the memory module of the received cryptogram block, the information input of the key is connected to the output of the memory module of the received cryptogram block, the information output of the key is connected to the second information input of the hash block and in parallel with the memory module of the previous received cryptogram block, the output of the hash block is the output of the device, the memory module of the information block, the select block, the hash block, the secret key memory module, the communication block memory, start block memory module, cryptogram block memory module, previous cryptogram block memory module, noise-resistant cryptogram block memory module, cryptogram block memory module, switch on the transmitting node, received cryptogram block memory module, identification block, switching block, secret key memory module , the hash block, the switching block, the memory module of the previous received cryptogram block, the memory module of the start block at the receiving node are equipped with control inputs to which Control ignaly generated by the control unit not forming part of the claimed device. The analysis of the prior art by the applicant has made it possible to establish that there are no analogues having sets of features identical to all the features of the claimed method and device for encrypting / decrypting messages with a hashing function. Therefore, each of the claimed inventions meets the condition of patentability "novelty."

 The search results for known solutions in this and related fields of technology in order to identify features that match the distinctive features of the prototypes of each claimed invention have shown that they do not follow explicitly from the prior art. From the prior art determined by the applicant, the popularity of the influence of the essential features of each of the claimed inventions on the achievement of the specified technical result is not revealed. Therefore, each of the claimed inventions meets the condition of patentability "inventive step".

The claimed objects of the invention are illustrated by drawings, in which:
- in FIG. 1 is a block diagram of a message encryption / decryption device with a hashing function;
- in FIG. 2 - oscillograms explaining the essence of the proposed method for encrypting / decrypting messages with a hashing function;
- in FIG. 3 is a block diagram of a hash block 3;
- in FIG. 4 is a block diagram of a switching unit 3.7;
- in FIG. 5 is a structural diagram of an identification unit 12;
- in FIG. 6 is a structural diagram of a switch 3.5.3;
- in FIG. 7 is a structural diagram of a key 3.14;
- in FIG. 8 is a block diagram of a selection block 2;
- in FIG. 9 is a block diagram of a unit for calculating the remainder of division 3.5;
- in FIG. 10 is a structural diagram of a memory module of noise-resistant blocks of cryptograms 10;
- in FIG. 11 is a graph showing the effect of the claimed method;
- in FIG. 12 is a timing chart explaining the essence of the proposed device for encrypting / decrypting messages with a hashing function;
- in FIG. 13 is a timing chart explaining the essence of the operation of the hash unit 3 of the proposed message encryption / decryption device by the hashing function.

 The implementation of the claimed method is as follows. To increase the reliability of the transmission of encrypted messages over communication channels with interference, their error-resistant coding is used with an excess code, which allows detecting transmission errors in received messages. However, this requires the channel to transmit additional redundant information generated from encrypted messages according to the encoding rule with a noise-resistant code, which requires an increase in the throughput of the communication channel. On the other hand, encrypted transmission of discrete channels of redundant messages, such as voice, sound, television fax and the like, which are shown in FIG. 2 (a), requires their preliminary conversion to digital form. Known methods of analog-to-digital conversion do not provide complete removal of the redundancy of the above signals, therefore, digital voice, sound, television, fax and similar messages have significant residual redundancy, which is described, for example, in the book "Compression and information search". - M.: Radio and Communications, 1988, p. 77. A view of digital speech, sound, television, facsimile and similar messages discretized with a sampling frequency of F = 1 / T and quantized by q levels (q> 2) is shown in FIG. 2 (b).

 However, the known methods for encrypting / decrypting messages do not take into account the presence of this redundancy in messages and generate unnecessary cryptograms in the encryption process. By the type of cryptogram received from the communication channel, it is impossible to determine whether it is distorted by a transmission error. Therefore, for the transmission of encrypted redundant messages over communication channels with errors, the use of noise-resistant cryptograms, which ensure that they are not distorted during transmission without introducing additional redundancy, has significant advantages.

 In the claimed method for providing encryption / decryption of messages by a hashing function with detection of transmission errors and retransmission of encrypted messages received with an error, which will increase the reliability of their transmission, the following sequence of actions is implemented.

 The preliminary formation of the hash function, secret key and start block of binary characters is as follows. As a hashing function, a conversion of a hashed block of binary symbols into a hashed block of q-ary symbols is used, which satisfies the following requirements.

 1) Each q-ary character of a hashed block depends on each binary character of a hashed block, each binary character of a secret key and each binary character of a start vector, that is, a change in any binary character of a hash block, a secret key or a start block causes a change in several q-ary characters hashed block.

 2) Knowing the full description of the hash fix, the value of the starting block of binary characters and an arbitrarily large number of values of hashed blocks and their corresponding values of hashed blocks, third parties (the adversary) are not able to calculate the secret key used in the hashing process.

 3) Knowing the full description of the hash function and the value of the starting block of binary characters, third parties are not able to form a hashed block for an arbitrary hashed block without knowing the secret key.

Known methods for pre-forming a hash function are described, for example, in the book of M.D. Smid, D.K. Branstel "Data Encryption Standard: Past and Future." TIIER, 1988, v. 76, No. 5, p. 49. They consist in the formation of a hash function with a secret key using the DES data encryption algorithm in ciphertext feedback mode or in output feedback mode. However, these methods of preliminary generation of the hash function are intended for hashing blocks of binary symbols with a length of only 64 bits, which significantly reduces the scope of their use. In addition, well-known methods for generating a hash function generate hashed blocks of binary characters, rather than q-ary characters, which is required in the claimed invention. Therefore, for hashing blocks of binary characters of arbitrary length with the formation of hashed blocks of q-ary characters, a hashing function of the following form is proposed. Randomly choose a Galois algebraic field GF (p) consisting of p elements. In the selected Galois field, one of the primitive elements a is searched for, capable of generating in an arbitrary order all the values of the elements of this field if it is successively raised to integer positive powers from 1 to p-1, calculating the result modulo p;
a ¹ (mod p) = a, and ² (mod p), and ³ (mod p), and ⁱ (mod p), .., a ^p-1 mod p),
where a ⁱ (mod p) belongs to the field GF (p) for all i = 1, ... p-1.

It is proposed to use one of the primitive elements of the Galois field as a secret key. A preformed hash function is mathematically described as:
e _{i, k} + e ^* _{j-1, k}
y _{i, j, k} = (a (modp)) (mod q), i = 1,2, ..., N, j = 1,2 .....,
where y _{i, j, k} is the k-th q-ary symbol of the hashed noise-resistant block of the cryptogram Y _{i, j} obtained by hashing the i-th noise-resistant block of the cryptogram E _{i of the} encryption of the j-th information block M _{j of} q-ary characters (i = 1 , 2, ..., N, j = 1,2, ..., k = 1,2, .., n);
e _{i, k} is the k-th binary symbol of the pre-selected i-th noise-resistant block of the cryptogram E _i (i = 1,2., .., N);
e ^* _{j-1, k} is the k-th binary symbol of the noise-resistant cryptogram block corresponding to the hashed noise-resistant cryptogram block selected in the previous step:
q is a prime, q << p, q> 2.

To encrypt / decrypt the first information block M _{1 of} q-ary characters, the value of the starting block of binary symbols E _{0 is} used as the value of the noise-resistant block of the cryptogram corresponding to the hashed noise-resistant block of the cryptogram selected in the previous step,
E ^* _j-1 = E ₀ if j = 1
The calculation of the result of exponentiation modulo a prime q provides the same probability that the calculated value y _{i, j, k} will take any value from 0 to q-1 with the same probability 1 / q, which is proved in the book: D. Knut "Art computer programming. " - M .: Mir, 1978, v. 3, p. 604.

The secret key value is selected by randomly selecting one of the primitive elements of the selected Galois field GF (p). The number of primitive elements of the field is estimated by the value of the Euler function from the value of the Euler function and, for p> 10 ^20, is the computationally non-exhaustive number of possible values of the secret key for third parties (the enemy). A method of searching for primitive elements of a Galois field is described, for example, in the book: IM. Vinogradov "Fundamentals of number theory." - M.: Science, Main Edition of the Physics and Mathematics Literature, 1981, p. 89.

 The choice of the value of the starting block of binary symbols is carried out by randomly selecting the block of binary symbols described, for example, in the book: D. Knut, "The Art of Computer Programming." - M .: Mir, 1977, v. 2, p. 22. A view of the binary character start block is shown in FIG. 2 (d).

 The transfer between the sender and the recipient of the messages of the secret key and the starting block of binary characters is carried out before the sender begins to transmit encrypted messages. In this case, the value of the secret key must be unknown to third parties (the adversary). To do this, the secret key and the starting block of binary characters can be transferred by courier in accordance with the necessary precautions. Known methods for transmitting between the sender and the recipient messages of the private key and blocks of binary characters are described, for example, in the book: J. Messi "Introduction to modern cryptology." TIIER, 1988, t. 76, No. 5, p. 24.

 If the message length exceeds the length of the information block of q-ary characters, then the message is divided into sequentially transmitted information blocks of q-ary characters of a fixed length n. Known methods for splitting a message into sequentially transmitted information blocks of q-aryn characters of fixed length are described, for example, in the book: V.I. Vasiliev, A.P. Burkin, V. A. Sviridenko "Communication systems". - M.: Higher School, 1987, - p. 208.

The preliminary formation of N noise-resistant blocks of cryptograms is as follows. An arbitrary binary error-correcting code is described by a generating matrix G of dimension r rows by n columns, where n> r. The value n is the length of the noise-resistant code blocks, r is the number of information bits in the noise-resistant code blocks. The formation of N noise-resistant blocks of cryptograms E _i is performed by multiplying each of N blocks of binary symbols I _{i of} length r bits, where i = 1,2 ...., N. to the generating matrix G of the binary error-correcting code according to the rule:
E = I _i G.

 Known methods for generating noise-resistant blocks are described, for example, in the book by W. Peterson, E. Weldon, "Codes for Correcting Errors." - M .: Mir, 1976, p. 252. The number N of pre-formed noise-resistant blocks of cryptograms is selected depending on the required accuracy of information blocks recovery of q-ary characters by the message recipient, as shown, for example, in the book: J. McHole. S. Rukos, G. Guiche "Vector quantization in speech coding". TIIER, 1985, v. 73, No. 11, p. 23. A view of N pre-formed noise-resistant blocks of cryptograms is shown in FIG. 2 (c).

Hashing of noise-resistant blocks of cryptograms by hashing function, secret key and starting block of binary symbols can be performed, for example, using the proposed hashing function based on raising to a power a primitive element of the Galois field with respect to the moduli of primes p and g:
e _{i, k} + e _{0, k}
y _{i, 1, k} = (a (mod p)) (mod q), i = 1,2, ..., N, k = 1, 2, ... n, q << p,
where y _{i, l, k} is the k-th q-ary symbol of the hashed noise-resistant block of the cryptogram Y _{i, 1} to encrypt the first information block of q-ary symbols M ₁ (i = 1,2 ..., N, k = 1, 2, .., n);
e _{i, k} is the kth binary symbol of the noise-resistant block of the cryptogram E _i (i = 1,2 ..., N);
e _{0, k} is the kth binary character of the starting block of binary characters E ₀ .

 As a result of the hashing of N noise-resistant blocks of cryptograms, N hashed noise-immune blocks of cryptograms are formed, each of which consists of n q-ary characters. A view of N hashed noise-resistant blocks of cryptograms is shown in FIG. 2. (g).

 Each i-th, where i = 1, .., N, the hashed error-correcting block of the cryptogram is compared with the first information block of q-ary characters. Known methods for comparing blocks of q-ary symbols are described, for example, in the book: W. Peterson. E. Weldon, “Codes Correcting Errors, '' - M.: Mir, 1976, p. 52. For comparison, the Lee metric is used, according to which, for comparing each i-th hashed noise-resistant block of the cryptogram with the first information block of q-ary characters, the value of the q-th hash noise-resistant block of cryptogram is subtracted from the value of each q-th the first information block of q-ary symbols and for each i-th hashed noise-resistant block of the cryptogram, the absolute values of the resulting differences are summed.

 Among the N hashed error-correcting blocks of cryptograms, the one closest to the first information block of q-ary symbols is selected, which corresponds to the minimum sum of learned differences. Known methods for choosing the minimum value among several values are described, for example, in the book: D. Knut, "The Art of Computer Programming." - M.: Mir, 1978, vol. 3, p. 219.

 A noise-resistant cryptogram block corresponding to the selected hashed noise-resistant cryptogram block is transmitted via a direct communication channel to the message recipient. Methods of binary blocks on a communication channel are known and described, for example, in a book: A.G. Zyuko, D.D. Klovsky, M.B. Nazarov. L.M. Fink "Theory of signal transmission." - M.: Radio and Communications, 1986, p. 11.

 A received noise-resistant cryptogram block is identified with N noise-resistant cryptogram blocks. Known identification methods are described, for example, in the book: W. Peterson, E. Weldon, "Codes for Correcting Errors." -M .: Mir, 1976, p. 15. To identify a received noise-resistant cryptogram block with N noise-resistant blocks of cryptograms, it is sequentially compared with each of N noise-resistant blocks of cryptograms. If there is not a single noise-resistant cryptogram block matching the received noise-resistant cryptogram block, then the received noise-resistant cryptogram block is considered unidentified.

The received unidentified noise-resistant cryptogram block is erased and a control signal is transmitted via the reverse communication channel for retransmission to the message recipient of the noise-resistant cryptogram block corresponding to the selected hashed noise-resistant cryptogram block. Known methods for erasing received noise-resistant blocks are described, for example, in the book: U, Peterson, E. Weldon "Error Correcting Codes". -M .: Mir, 1976, p. 17. Known methods for transmitting sending signals over the reverse communication channel for retransmission to the receiver of messages of the noise-resistant block are described, for example, in the book: W. Peterson, E. Weddon, “Codes Correcting Errors,” M.: Mir, 1976, p. 17,
The received identified noise block is hashed by the hash function, the secret key and the binary start block in a manner identical to the message sender hashes the noise-resistant blocks of the cryptogram by the hash function, the secret key and the binary start block using the proposed hash function based on raising a primitive Galois field element moduli of primes p and g:
e ' _{1, k} + e _{0, k}
m ^ _{1, k} = (a (modp)) (modq), k = 1, 2, ..., n, g << p,
where m ^ _{1, k} is the k-th q-ary symbol of the first restored information block of M ^ ₁ q-ary symbols;
e _{1, k} 'is the kth binary symbol of the first received identified noise-resistant cryptogram block E ₁ ';
e _{0, k} is the kth binary character of the starting block of binary characters E ₀ .

 As a result, the approximation of the first information block of q-ary symbols is restored on the receiving side.

To encrypt the second and subsequent information blocks of q-ary characters, N noise-resistant cryptogram blocks are hashed by the hashing function, the secret key, and the noise-resistant cryptogram block corresponding to the hashed noise-resistant cryptogram block selected in the previous step using the proposed hash function based on raising the primitive element of the field field Galois moduli of primes p and g:
e _{i, k} + e ^* _{j-1, k}
y _{i, j, k} = (a (mod p)) (mod q), i = 1,2, ..., N, j = 1,2, ..., k = 1,2, ... , n, q << p.

where y _{i, j, k} is the k-th q-ary character of the hashed noise-resistant block of the cryptogram Y _{i, j} for encryption of the j-th information block of q-ary characters (i = 1,2, ..., N, j = 1 , 2, ..., k = 1,2, ..., n);
e _{i, k} is the kth binary symbol of the noise-resistant block of the cryptogram E _i (i = 1,2, ..., N);
e ^* _{j-1, k} is the kth binary symbol of the noise-resistant block of the cryptogram E ^* _j-1 corresponding to the hashed noise-blocking block of the cryptogram Y ^* _j-1 selected in the previous step.

 Each i-th, where i = 1,2, ..., N, the hashed error-correcting block of the cryptogram is compared with the next information block of q-ary characters. Known methods for comparing blocks of q-ary symbols are described, for example, in the book: W. Peterson, E. Weldon "Error Correcting Codes'". - M .: Mir, 1976, p. 52. For comparison, the Lee metric is used, according to which, for comparing each i-th hashed noise-resistant block of a cryptogram with the next information block of q-ary symbols from the value of each q-ary sample of the i-th the hashed error-correcting block of the cryptogram is subtracted the corresponding q-ary count value of the next information block of q-symbol characters, and for each i-th hashed noise-resistant block of the cryptogram, the absolute values of the damaged differences are summed.

 Among the N hashed noise-resistant blocks of cryptograms, the one closest to the next information block of q-ary symbols is selected, which corresponds to the minimum sum of the obtained differences. Known methods for choosing the minimum value among several values are described, for example, in the book: D. Knut, "The Art of Computer Programming." - M.: Mir, 1978, vol. 3, p. 219.

 A noise-resistant cryptogram block corresponding to the selected hashed noise-resistant cryptogram block is transmitted via a direct communication channel to the message recipient. Methods of transmitting a binary block over a communication channel are known and described, for example, in the book of A.G. Zyuko, D.D. Klovsky M.B. Nazarov, L.M. Fink "Theory of signal transmission." - M.: Radio and Communications, 1986, p. 11.

 A received noise-resistant cryptogram block is identified with N noise-resistant cryptogram blocks. Known identification methods are described, for example, in the book: W. Peterson, E. Weldon, "Codes for Correcting Errors." -M .: Mir, 1976, p. 15. To identify a received noise-resistant cryptogram block with N noise-resistant blocks of cryptograms, it is sequentially compared with each of the N noise-resistant blocks of cryptograms. If there is not a single noise-resistant cryptogram block matching the received noise-resistant cryptogram block, then the received noise-resistant cryptogram block is considered unidentified.

 The noise-resistant cryptogram block received by an unidentified one is erased and the control signal is transmitted to the retransmission message receiver of the noise-resistant cryptogram block corresponding to the selected hashed noise-resistant cryptogram block via the reverse communication channel. Known methods for erasing received noise-resistant blocks are described, for example, in the book: W. Peterson. E. Weldon "Error Correcting Codes." -M .: Mir, 1976, p. 17. Known methods for transmitting control signals over the reverse communication channel for retransmission to the receiver of messages of a noise-resistant block are described, for example, in a book; W. Peterson, E. Uzldon "Codes Correcting Errors." -M .: World. 1976, p. 17.

The received identified noise-resistant cryptogram block is hashed by the hash function, the secret key and the previously received identified noise-resistant cryptogram block in a way identical to the message sender hashing the noise-resistant cryptogram blocks according to the hashing function, the secret key and the noise-resistant cryptogram block corresponding to the selected cryptogram block corresponding to the selected cryptogram block used in the previous step proposed hash based function erected I have the power of a primitive element of the Galois field modulo the prime numbers p and g:
e ' _{j, k} + e' _{j-1, k}
m ^ _{j, k} = (a (mod p)) (mod q), k = 1,2 ..., n, q << p.

where m ^ _{j, k} is the k-th q-ary character of the j-ro restored information block M ^ _{j of} q-ary characters;
e ' _{j, k} is the kth binary symbol j-ro of the received identified noise-resistant cryptogram block E'_j;
e ' _{j-1, k} is the kth binary symbol of the previous received identified noise-resistant cryptogram block E' _j-1 .

 As a result of this, the approximation of the next information block of q-ary symbols is restored on the receiving side.

 The actions for transmitting, via a direct communication channel, the message receiver of the noise-resistant cryptogram block corresponding to the selected hashed noise-resistant block of the cryptogram, and the actions for transmitting a control signal via the reverse communication channel for retransmission to the message recipient of the noise-resistant cryptogram block corresponding to the selected hashed noise-resistant block of the cryptogram, are synchronized. Synchronization methods are described, for example, in the book by E. M, Martynov, "Synchronization in discrete message transmission systems." -M .: Communication, 1972, p. 186.

 In an analytical form, these actions can be written as follows.

e'_j,k + e'_j-1,k
m^_j,k = (a(mod p))(mod q), j=1,2,..., k=1,2,..,n, q<<p,
e'_j-1,k = e_0,k, если j=1,
где Y_i,j - i-й хэшированный помехоустойчивый блок криптограммы для шифрования j-го информационного блока М_j q-ичных символов, состоящий из n q-ичных символов y_i,j,k;;
Y^* _j - выбранный хэшированный помехоустойчивый блок криптограммы для шифрования j-го информационного блока М_j q- ичных символов, состоящий из n q-ичных символов y^* _j,k;
E₀ - стартовый блок двоичных символов, состоящий из n двоичных символов e_0,k;
E_i - i-й помехоустойчивый блок криптограммы, состоящий из n двоичных символов e_i,k;
E^* _j - помехоустойчивый блок криптограммы, соответствующий выбранному хэшированному помехоустойчивому блоку криптограммы, состоящий из n двоичных символов e^* _j,k;
E^* _j-1 - помехоустойчивый блок криптограммы, соответствующий выбранному на предыдущем шаге хэшированному помехоустойчивому блоку криптограммы, состоящий из n двоичных символов e^* _j-1,k;
E^ _j - j-й принятый помехоустойчивый блок криптограммы, состоящий из n двоичных символов e^_j,k;
E'_j - j-й принятый идентифицированный помехоустойчивый блок криптограммы, состоящий из n двоичных символов e'_j,k;
E'_j-1 - предыдущий принятый идентифицированный помехоустойчивый блок криптограммы, состоящий из n двоичных e'_j-1,k;
M^_j - j-й восстановленный информационный блок q-ичных символов, состоящий из n q-ичных символов m^_j,k.M _j = (m _{j, 1} , m _{j, 2} , ..., m _{j, k} , ..., m _{j, n} ), k = 1,2, ..., n,
E ₀ = (e _0,1 , e _0,2 , ..., e _{0, k} , ..., e _{0, n} ), k = 1,2, ..., n,
E _i = (e _{i, 1} , e _{i, 2} , ..., e _{i, k} , ..., e _{i, n} ), k = 1,2, ..., n,
Y _{i, j} = (Y _{i, j, 1} , Y _{i, j, 2} , ..., Y _{i, j, k} , ..., Y _{i, j, n} ), k = 1,2 ,. .., n,
E ^* _j = (e ^* _{j, 1} , e ^* _{j, 2} , ..., e ^* _{j, k} , ..., e ^* _{j, n} ), k = 1,2, ..., n,
E ^* _j-1 = (e ^* _j-1,1 , e ^* _j-1,2 , ..., e ^* _{j-1, k} , ..., e ^* _{j-1, n} ), k = 1,2, ..., n,
E ^ _j = (e ^ _{j, 1} , e ^ _{j, 2} , ..., e ^ _{j, k} , ..., e ^ _{j, n} ), k = 1,2, ..., n,
E ' _j = (e' _{j, 1} , e ' _{j, 2} , ..., e' _{j, k} , ..., e ' _{j, n} ), k = 1,2, ..., n,
E ' _j-1 = (e' _j-1,1 , e ' _j-1,2 , ..., e' _{j-1, k} , ..., e ' _{j-1, n} ), k = 1,2, ..., n,
M ^ _j = (m ^ _{j, 1} , m ^ _{j, 2} , ..., m ^ _{j, k} , ..., m ^ _{j, n} ), k = 1,2, ..., n,
e _{i, k} + e ^* _{j-1, k}
Y _{i, j, k} = (a (mod p)) (mod q), i = 1,2, ..., N, j = 1,2, ..., k = 1,2, .. n , q << p,
e ^* _{j-1, k} = e _{0, k} if j = 1,

e ' _{j, k} + e' _{j-1, k}
m ^ _{j, k} = (a (mod p)) (mod q), j = 1,2, ..., k = 1,2, .., n, q << p,
e ' _{j-1, k} = e _{0, k} if j = 1,
where Y _{i, j} is the i-th hashed error-correcting cryptogram block for encryption of the j-th information block M _{j of} q-ary characters, consisting of n q-ary characters of y _{i, j, k;} ;
Y ^* _j is the selected hashed noise-resistant block of the cryptogram for encryption of the j-th information block M _{j of} q-ary characters, consisting of n q-ary characters of y ^* _{j, k} ;
E ₀ - the starting block of binary characters, consisting of n binary characters e _{0, k} ;
E _i is the i-th noise-resistant block of the cryptogram, consisting of n binary symbols e _{i, k} ;
E ^* _j is the noise-resistant cryptogram block corresponding to the selected hashed noise-resistant cryptogram block, consisting of n binary characters e ^* _{j, k} ;
E ^* _j-1 - noise-resistant cryptogram block corresponding to the hashed noise-resistant cryptogram block selected in the previous step, consisting of n binary characters e ^* _{j-1, k} ;
E ^ _j - the j-th received noise-resistant block of the cryptogram, consisting of n binary characters e ^ _{j, k} ;
E ' _j is the jth received identified error-correcting cryptogram block, consisting of n binary symbols e' _{j, k} ;
E ' _j-1 - the previous received identified noise-resistant block of the cryptogram, consisting of n binary e' _{j-1, k} ;
M ^ _j is the j-th restored information block of q-ary characters, consisting of n q-ary characters m ^ _{j, k} .

где m_j,k - k-й q-ичный символ j-го информационного блока M_j q-ичных символов;
m^ _j,k - k-й q-ичный символ j-го восстановленного информационного блока M^_j q-ичных символов;
Q - количество шифрованных информационных блоков q-ичных сигналов.Verification of the theoretical background of the claimed method of encrypting / decrypting messages with a hashing function was verified by computer simulation on a PC. As a result of modeling the encryption / decryption of redundant messages transmitted over the communication channel with interference, the results were obtained, presented in the form of graphs in FIG. 11. In FIG. 11 shows the dependences of the signal-to-noise ratio A _{o of the} decrypted excess signal on the probability of error p in a binary symmetric memoryless channel. Graph 1) is constructed for the case of using the claimed method of encrypting / decrypting messages with a hashing function, and graph 2) for the case of using the prototype method. The signal-to-noise ratio A _{o of the} decrypted excess signal was determined by the formula:

where m _{j, k} is the k-th q-ary character of the j-th information block M _j q-ary characters;
m ^ _{j, k} is the k-th q-ary character of the j-th restored information block of M ^ _j q-ary characters;
Q is the number of encrypted information blocks of q-ary signals.

 A speech signal quantized using an 8-bit pulse-code modulation codec and having 253 different amplitude values (q = 253) was used as an excess signal.

 The conducted experimental studies confirm that the use of the proposed method of encrypting / decrypting messages with a hashing function improves the reliability of the transmission of encrypted redundant messages over interference channels due to the detection of transmission errors and the retransmission of encrypted redundant messages received with an error.

 The message encryption / decryption device by the hashing function shown in FIG. 2, consists of a transmitting and receiving nodes. The transmitting unit includes a memory module for information block 1, a selection block 2, a hash block 3, a secret key memory module 4, a switching block 5, a starting block 6 memory module, a cryptogram block memory module 7, a previous cryptogram block memory module 8, a switch 9, and a module memory of noise-resistant blocks of cryptograms 10. The receiving node includes a memory module of a received block of cryptograms 11, an identification unit 12, a memory module of noise-resistant blocks of cryptograms 13, a key 14, a memory module of a secret key 15, a hashing block 16, a block to ommutation 17, the memory module of the previous received cryptogram block 18 and the memory module of the start block 19. The input of the memory module of the information block 1 is the input of the device. The output of the memory module of the information block 1 is connected to the first information input of the selection block 2, the output of which is connected to the information input of the memory module of the noise-resistant blocks of cryptograms 10. The second information input of the selection block 2 is connected to the output of the hash block 3. The input of the secret key of the hash block 3 is connected to the output secret key memory module, the first hash information input is connected to the output of the switching unit 5, the first information input of which is connected to the output of the memory module of the start block 6 , the second information input of the switching unit 5 is connected to the output of the memory module of the previous cryptogram unit 8. The first output of the switch 9 is connected to the second information input of the hashing unit, the second output of the switch is connected to the input of the memory module of the selected cryptogram unit 7 and in parallel with the input of the memory module of the previous selected block cryptograms 8, the input of the switch 9 is connected to the output of the memory module of noise-resistant blocks of cryptograms 10. The output of the memory module of the noise-resistant block of cryptograms 7 is connected to the input th forward link channel, and the first control input cryptogram 7 is connected to the inverse output connection channel block error-correcting memory module. The output of the direct communication channel is connected to the input of the memory module of the received cryptogram block 11, the first output of which is connected to the first input of the identification block of the received cryptogram block with noise-resistant cryptogram blocks 12, the output of which is connected to the information input of the key 14. The second input of the identification block 12 is connected to the output of the module memory of noise-resistant blocks of cryptograms 13. The first control output of the identification block 12 is connected to the input of the memory module of noise-resistant blocks of cryptograms 13, the second control output connected to the control input of the key 14 and in parallel with the input of the reverse communication channel. The output of the key 14 is connected to the second information input of the hash block 16 and in parallel with the input of the memory block of the previously received cryptogram block 18. The secret key input of the hash block 16 is connected to the output of the secret key memory module 15, the first information input of the hash block 16 is connected to the output of the switching block 17 the first input of which is connected to the output of the memory module of the previous received cryptogram block 18, and the second to the output of the memory module of the start block 19. The output of the hash block is the output of the device.

 Information module 1 memory module, selection block 2, hash block 3, secret key memory module 4, switching block 5, starting block memory module 6, memory module of the selected cryptogram block 7, memory module of the previous selected cryptogram block 8, switch 9, memory module the received cryptogram block 11, the identification block 12, the switching block 14, the secret key memory module 15, the hash block 16, the switching block 17, the memory module of the previous received cryptogram block 18, the memory module of the starting block 19 are provided with inputs ravlyaetsya signals generated by the control unit, not shown in the drawings.

 The memory module of the information block 1 is designed to divide the message into information blocks of q-ary characters with a length of n characters, write the value of the first and then the next information block of q-ary characters, store and read it to the first information input of block 2 for comparison with the value of each i-th, where i = 1,2 ..., N. hashed noise-resistant cryptograms. As a memory module of information block 1, a static random access memory (RAM) can be used, the construction scheme of which is known and is given, for example, in the book: V. A. Batushev, V. N. Veniaminov, etc. "Microcircuits and their application: Reference Guide. " - M.: Radio and Communications, 1983, p. 175, Fig. 5.12. The memory module of information block 1 can be implemented, for example, on a memory chip K 537RU8 (see V.I. Korneychuk, V.P. Tarasenko, "Computing devices on microcircuits: a Reference." - K .: Technika, 1988, p. 85 -87).

 The selection unit 2 shown in FIG. 8, is intended to compare the values of each i-th, where i = 1,2, .., N, of the hashed error-correcting block of the cryptogram with the value of the first, and then the next information block of q-ary symbols and to select among the N hashed noise-resistant blocks of the cryptogram close to the first and then the next information block of q-ary characters. The selection block 2 consists of a subtractor 2.1, an adder 2.2, a controlled switch 2.3, a comparator 2.4, a storage register of the minimum amount 2.5) and a multiplexer 2.6.

 The first input of the subtractor 2.1 is the second information input of the selection block 2. The second input (input B) of the subtractor 2.1 is the first information input of the selection block 2. The output of the subtractor 2.1 is connected to the first input (input A) of the adder 2.2. The output of the adder 2.2 is connected in parallel with the information input of the managed switch 2.3 and its own second input (input B). To the control input of the managed switch 2,3, control signals are output from the output of the control unit, not shown in the drawings. The control input of the controlled switch 2.3 is the first control input of the selection unit 2. The information output of the controlled switch 2.3 in parallel is connected to the second input (input B) of the comparator 2.4 and the first information input (input X) of the multiplexer 2.6. At the second information input (input Y) of the multiplexer 2.6 information signals of a unit value "1" are constantly supplied. The control input (input S) of the multiplexer 2.6 sends control signals from the output of the control unit, not shown in the drawings. The control input of multiplexer 2.6 is the control input of block 2, the output of multiplexer 2.6 is connected to the information input (input X) of the minimum storage register 2.5. The output of the minimum amount storage register 2.5 is connected to the first input (input A) of the comparator 2.4, the output of which is connected to the control input (input W) of the minimum amount 2.5 storage register, and is also the output of selection block 2.

 Subtractor 2.1 is intended for determining the difference by the values of q-ary symbols of a hashed noise-resistant cryptogram block and the corresponding q-ary symbols of the information block of q-ary symbols. Subtractor 2.1 is an adder operating in the subtraction mode. The subtractor circuit is known, for example, is given in the book: P. P. Maltsev et al. "Digital Integrated Circuits": Reference. -M.: Radio and communications, 1994, p. 76, and it can, for example, be implemented on the K555IM7 chip (see V. L. Shilo "Popular Digital ICs." - M: Radio and communications. 1987, p. . 159-161).

 Adder 2.2 is designed to summarize the differences between the values of q-ary characters of a hashed noise-resistant block of a cryptogram and an information block of q-ary characters. The adder circuit is known, for example, is given in the book: L.A. Maltseva et al. "Fundamentals of digital technology." -M .: Radio and communications, 1986, p. 53-54, fig. 51 and can be performed, for example, on the K155IM1 microcircuit (see VL Shilo “Popular Digital Microcircuits.” - M.: Communication, 1987, p. 156).

 The controlled switch 2.3 shown in FIG. 7, is designed to ensure that the value of the number is read from the output of the adder 2.2 to the second input of the comparator (input B) 2.4 and to the first information input (input X) of multiplexer 2.6 when the control signal 2.3 is received at the control input of the control switch. By its physical nature, the controlled switch 2.3 is a two-position controlled switch. Schemes of controlled switches are known and are given, for example, in the book; V.L. Shilo "Popular CMOS chips, Reference." -M .: Jaguar, 1993, p. 22.

 Comparator 2.4 is designed to compare the value of the number obtained from the output of the adder 2.2 and the value of the number recorded in the storage register of the minimum amount of 2.5. The comparator circuit is known, for example, is given in the book: P. P. Maltsev et al. "Digital Integrated Circuits: A Guide. -M .: Radio and Communications, 1994, p. 83 and can be implemented, for example, on the K555SP1 chip ( see VL Shilo "Popular digital microcircuits." - M.: Radio and Communications, 1987. p. 183).

 The minimum amount storage register 2.5 is designed to store the minimum value of the number received in the adder 2.2. The scheme of the storage register of the minimum amount of 2.5 is known and is given, for example, in the book: V.A. Batushev, V.N. Veniaminov et al. Microcircuits and their application: Reference manual. - M.: Radio and communications, 1983, p. 134. rice, 4.34. and can be implemented, for example, on the microcircuit K 531IR19 (see VL. Shilo "Popular digital microcircuits." - M .: Radio and communications, 1987, p. 120).

 Multiplexer 2.6 is a two-input multiplexer, the circuit of which is known, is shown, for example, in the book: L.A. Maltseva et al. "Fundamentals of digital technology." -M.: Radio and Communications, 1986, p. 52, Fig. 48, and can be implemented, for example, on the K155KP5 microcircuit (see VL Shilo "Popular Digital Microcircuits." - M .: Radio and 1987, p. 146).

 The hash unit 3 shown in FIG. 3, is intended for hashing noise-resistant blocks of cryptograms by hashing function, secret key and starting block of binary symbols when encrypting the first information block of q-ary symbols and for hashing noise-resistant blocks of cryptograms by hashing function, secret key and noise-resistant block of cryptogram corresponding to the one selected in the previous step the hashed noise-resistant block of the cryptogram when encrypting the next information block of q-ary characters. The hashing block consists of adder 3.1, registers 3.2, 3.6, 3.12, 3.16, 3.19, subtractors 3.3 and 3.8, comparators 3.4, 3.11, 3.13, blocks for calculating the remainder of division 3.5 and 3.18, switch 3.9, switching blocks 3.7 and 3.17, multiplier 3.10 , keys 3.14 and 3.15, elements OR 3.20 and 3.21 and inverter 3.22.

 The first input of adder 3.1 is the read input of the start block of binary characters read from the memory module of the start block when encrypting the first information block of q-ary characters or the read input of the noise-resistant cryptogram block corresponding to the hashed noise-resistant cryptogram block selected in the previous step read from the memory module of the previous the selected cryptogram block 8 when encrypting the next information block of q-ary characters (depending on the value of the control Igna applied to the control input of the switch 5) block. The first input of the adder 3.1 is the first information input of the hashing unit 3. The second input of the adder 3.1 is the read input of the noise-resistant cryptogram block read from the memory module of the noise-resistant cryptogram blocks 10 and is the second information input of the hash block 3. The first information input of the switching block 3.17 is the secret key input hash block 3. The output of adder 3.1 is connected to the first information input of the switching unit 3.3 and in parallel to the first input of the comparator 3.4. The second input of the comparator 3.4 is constantly fed a signal of zero level ("0"). To the control input of the switching unit 3.3, which is the first control input of the hashing unit 3, control signals from the control unit, not shown in the drawings, are supplied. To the control input of the switching unit 3.17, which is the second control input of the hashing unit 3, control signals from the control unit, not shown in the drawings, are supplied. To the control inputs of the blocks for calculating the remainder of division 3.18 and 3.5, which are the third and fourth control inputs of the hash unit 3, respectively, control signals from the control unit, not shown in the drawings, are supplied. To the control input of the key 3.14, which is the fifth control input of the hashing unit 3, control signals from the control unit, not shown in the drawings, are supplied. The output of the switching unit 3.3 is connected to the input of register 3.6, the output of which is connected to the first input of the subtractor 3.8. The second input of the subtractor 3.8 is constantly supplied with a signal of a unit level (1). The output of the subtractor 3.8 is connected to the first input of the comparator 3.11 and in parallel to the second information input of the switching 3.3 and to the first input of the comparator 3.13. The output of the comparator 3.11 is connected to the first input of the OR element 3.20 and in parallel with the first input of the OR element 3.21. The output of comparator 3.13 is connected to the second input of the OR element 3.20 and in parallel with the input of the inverter 3.22. The output of the inverter 3.22 is connected to the second input of the OR element 3.21. The output of the OR 3.20 element is connected to the control input of the switch 3.9. The output of the OR 3.21 element is connected to the control input of the key 3.15. The output of the OR 3.21 element is connected to the control input of the key 3.15. To the second input of the comparator 3.11 the signal of unit level (1) is constantly supplied, and the signal of level zero (0) is constantly supplied to the second input of comparator 3.13. The second output of switch 3.9 is connected to the second information input of switching unit 3.17, the output of which is connected to the first input of the computation unit the remainder of division 3.18. The second input of the remainder of division 3.18 is connected to the output of register 3.19, and the output of the remainder of division 3.18 is connected to the input of register 3.16. The output of register 3.16 is connected to the information input of key 3.14 and in parallel with the information input of the key 3.15. The output of the key 3.14 is connected to the input of the register 3.12. The first input of the multiplier 3.10 is connected to the output of the key 3,15, the second input is connected to the output of the register 3.12, and the output of the multiplier 3.10 is connected to the information input of the switch 3.9. The first output of the switch 3.9 is connected to the second information input of the switching unit 3.7, the control input of which is connected to the output of the comparator 3.4. A signal of a single level ("1") is constantly applied to the first information input of the switching unit 3.7. The first input of the unit for calculating the remainder of division 3.5 is connected to the output of the switching unit 3.7, the second input of the unit for calculating the remainder of division 3.5 is connected to the output of register 3.2, and the output of the unit for calculating the remainder of division 3.5 is the output of the hash unit 3.

 Adder 3.1 is designed to summarize the values of the starting block of binary symbols when encrypting the first information block of q-ary symbols or the noise-resistant cryptogram block corresponding to the hashed noise-resistant cryptogram block selected in the previous step when encrypting the next information block of q-ary symbols (depending on the value of the control signal, applied to the control input of the switching unit 5) with the value of the noise-resistant cryptogram block read from the memory module resilient blocks of cryptograms 10. The adder circuit is known, is shown, for example, in the book: L.A. Maltseva et al. "Fundamentals of digital technology." -M. : Radio and communication, 1986, pp. 53-54, fig. 51 and can be performed, for example, on the K155IM1 microcircuit (see VL Shilo “Popular Digital Microcircuits”, - M .: Radio and Communication, 1987, p. 156).

 Register 3.2 is designed to store the value of a prime q. The register 3.2 scheme is known and is given, for example, in the book: V.A. Batushev, V.N. Veniaminov et al. Microcircuits and their application: Reference manual. - M.: Radio and Communications, 1983, p. 134, Fig. 4.34, and can be implemented, for example, on the K 531IR19 microcircuit (see VL Shilo “Popular Digital Microcircuits.” - M .: Radio and Communication, 1987, p. 120).

 The switching unit 3.3 is identical to the switching unit 3.7 shown in FIG. 4, and is designed to switch the operation of the hash unit 3 from the read mode to the input of register 3.6 of the number value from the output of the adder 3.1 to the read mode to the input of register 3.6 of the number value from the output of the subtractor 3.8.

 Comparator 3.4 is intended for the value of the number received from the output of the adder 3.1, with a zero value. The comparator circuit is known, for example, is given in the book: P.P. Maltsev, etc. "Digital integrated circuits: Reference. -M .: Radio and communications. 1994, p. 83 and can be implemented, for example, on the K555SP1 chip (see VL Shilo" Popular digital circuits ", - M .: Radio and Communication, 1987, p. 183).

 The division residue calculation block Z.5 shown in FIG. 9, is designed to find the remainder of dividing the value of the dividend read from the output of the switching unit 3.7 by the value of the prime number stored in register 3.2. The unit for calculating the remainder of division 3.5 consists of register 3.5.1, subtractor 3.5.2, switch 3.5.3, comparator 3.5.4 and key 3.5.5. The first information input of key 3.5.5 is the first input of the block for calculating the remainder of division 3.5. The output of key 3.5.5 is connected to the input of register 3.5.1. The control input of the key 3.5.5 is the control input of the unit for calculating the remainder of division 3.5. The output of register Z.5.1 is connected to the first input of the subtractor 3.5.2. The second input of the subtractor 3.5.2 in parallel with the first input of the comparator 3.5.4 is the second input of the unit for calculating the remainder of division 3.5. The output of the subtractor 3.5.2 is connected to the second input of the comparator 3.5.4 and in parallel with the information input of the switch 3.5.3. The output of the comparator 3.5.4 is connected to the control input of the switch 3.5.3. The second output of the switch 3.5.3 is the output of the unit for calculating the remainder of division 3.5. The first output of the switch 3.5.3 is connected to the second information input of the key 3.5.5.

 Register 3.5.1 is intended for storing the value of a number read at the input of the unit for calculating the remainder of division 3.5 and storing in the future the value of the intermediate results of the calculation of dividing the read number by a prime number q. The register scheme 3.5.1 is known and is given, for example, in the book: V. A. Batushev, V.N. Veniaminov et al. Microcircuits and their application: Reference manual. - M .: Radio and communications. 1983, p. 134, fig. 4.34 and can be implemented, for example, on the K 531IR19 microcircuit (see VL Shilo “Popular Digital Microcircuits.” - M .: Radio and Communication, 1987, p. 120).

 Subtractor 3.5.2 is used to determine the difference between the value of the dividend read out through register 3.5.1 and the value of the prime number read out at the second input of the block for calculating the remainder of division 3.5. Subtractor 3.5.2. is an adder operating in the subtraction mode. The scheme of the subtractor is known, for example, is given in the book; P.P. Maltsev et al. "Digital integrated circuits; Reference. -M .: Radio and communications, 1994, p. 76. It can be implemented, for example, on the K555IM7 chip (see VL Shilo" Popular digital circuits ". - M.: Radio and communications. 1987, p. 159-161).

 The switch 3.5.3 shown in FIG. 6, it is intended to switch the operation of the remainder of division 3.5 division from the mode of calculating the remainder of the division of the dividend number by the value of the prime number into the read mode from the output of the remainder of division 3.5 division of the calculated remainder value. Switch 3.5.3 contains a first controllable switch 3.5.3.1, a second controllable switch 3.5.3.2, and an inverter 3.5.3.3. The information input of the first managed switch 3.5.3.1 and the information input of the second managed switch 3.5.3.2 connected to it in parallel is the information input of the switch 3.5.3. The control input of the second controlled switch 3.5.3.1 is connected to the output of the inverter 3.5.3.3. The outputs of the first controllable switch 3.5.3.1 and the second controllable switch 3.5.3.1 are respectively the first and second outputs of the switch 3.5.3. The control input of the first controllable switch 3.5.3.1 and the inverter 3.5.3.3 input connected in parallel to it are the control inputs of switch 3.5.3.

 The first controlled switch 3.5.3.1 is designed to read the value of the intermediate results of calculating the remainder of dividing the number by a prime q from the output of the subtractor 3.5.2 to the second information input of the key 3.5.5. The circuit of the first controllable switch 3.5.3.1 is identical to the circuit of the key 3.14 shown in FIG. 7. The second controllable switch 3.5.3.2 is intended for reading from the output of the block for calculating the remainder of division 3.5 the values of the calculated remainder. The circuit of the second controlled switch 3.5.3.2 is identical to the circuit of the key 3.14. shown in FIG. 7. The inverter 3.5.3.3 is designed to generate a control signal supplied to the control input of the second controlled switch 3.5.3.2. The inverter circuit 3.5.3.3 is known and is given, for example, in the book: V.L. Shilo "Popular CMOS chips, a reference." -M .: Jaguar, 1993. p. 22.

 Comparator 3.5.4 is intended for comparing the value of a number read from a subtractor 3.5.2 with the value of a prime number received from the second input of the unit for calculating the remainder of division 3.5. The comparator circuit is known, for example, is given in the book: P.P. Maltsev et al. "Digital integrated circuits; Reference. -M .: Radio and communications. 1984, p. 83 and be implemented, for example, on the K555SP1 chip (see VL Shilo" Popular digital circuits ". -M. : Radio and Communications, 1987, p. 183).

 The key 3.5.5 is designed to switch the operation of the remainder of division 3.5 division from reading the value of the number read to the input of the remainder of division 3.5 block to read the value of the intermediate results of calculating the remainder of dividing the read number by a prime q to the input of register 3.5. 1. The key circuit 3.5.5 is identical to the circuit of the switching unit 3.7 shown in FIG. 4.

 Register 3.6 is designed to store the value of the number read from the output of switching unit 3.3. The register 3.6 scheme is known and is given, for example, in the book: B. A. Batushev. B.N. Veniaminov et al. Microcircuits and their application: Reference manual. - M.: Radio and Communications, 1983, p. 134. Fig. 4.34, and can be implemented, for example, on the K 531IR19 microcircuit (see VL Shilo “Popular Digital Microcircuits.” -M .: Radio and Communications, 1987, p. 120).

 The switching unit 3.7 shown in FIG. 4, is designed to switch the operation of the hashing unit 3 from the reading mode of the intermediate value of the hashed noise-resistant cryptogram block to the reading mode of a single value to the input of the division unit of the remainder of division 3.5. The switching unit 3.7 contains a first controllable switch 3.7.1, a second controllable switch 3.7.2 and an inverter 3.7.3. The information inputs of the first managed switch 3.7.1 and the second managed switch 3.7.1 are respectively the first and second information inputs of the switching unit 3.7. The information outputs of the first and second controlled switches 3.7.1 and 3.7.2 connected in parallel are the output of the switching unit 3.7. The input of the inverter 3.7.3 and the control input of the first controlled switch 3.7.1 connected to it in parallel are the control input of the switching unit 3.7. The output of the inverter 3.7.3 is connected to the control input of the second managed switch 3.7.2. Schemes of controlled switches and inverter are known and are given in the book: V.L. Shilo "Popular CMOS chips, a reference." -M .: Jaguar, 1993, p. 22.

 Subtractor 3.8 is designed to subtract from the value of the number received from the output of register 3.6, a single value. Subtractor 3.8 is an adder operating in the subtraction mode. The scheme of the subtractor is known, is given, for example, in the book: P.P. Maltsev et al. "Digital Integrated Circuits: A Guide. -M .: Radio and Communications, 1994, p. 76, and it can, for example, be implemented on the K555IM7 chip (see V.L. Shilo" Popular Digital Circuits ". - M.: Radio and Communications, 1987, p. 159-161).

 Switch 3.9 is identical to switch 3.5.3 shown in FIG. 6, and is designed to read the value of the number from the output of the multiplier 3.10 to the input of the switching unit 3.7 or to the input of the switching unit 3.17, depending on the values of the output signals of the comparators 3.11 and 3.13 received at the control input of the switch 3.9.

 The multiplier 3.10 is designed to multiply the values of the numbers obtained from the outputs of the register 3.12 and the key 3.15, respectively. The scheme of the multiplier 3.10 is known, is given, for example, in the book: P.P. Maltsev, etc. "Digital Integrated Circuits: A Guide. -M .: Radio and Communications, 1994, p. 82 and it can, for example, be implemented on the K555IP9 chip (see VL Shilo" Popular Digital Circuits ". -M .: Radio and Communication, 1987, pp. 157-169).

 Comparator 3.11 is designed to compare the value of the number received from the output of the subtractor 3.8, with a single value. The comparator circuit is known, for example, is given in the book: P.P. Maltsev et al. "Digital Integrated Circuits: A Guide. -M .: Radio and Communications, 1994. p. 83 and can be implemented, for example, on the K555SP1 chip (see VL Shilo" Popular Digital Circuits ". - M .: Radio and Communications. 1987, p. 183).

 Register 3.12 is designed to store the value of the number received from the output of the key 3.14. Register scheme 3.12. known and given, for example, in the book: V. A. Batushev, V. N, Veniaminov and others. Microcircuits and their application: Reference manual. - M.: Radio and Communications, 1983, p. 134. Fig. 4.34. and can be implemented, for example, on the microcircuit K 531IR19 (see VL Shilo "Popular digital microcircuits." - M .: Radio and communications, 1987, p. 120).

 Comparator 3.13 is designed to compare the value of the number received from the output of the subtractor 3.8, with a zero value. The comparator circuit is known, for example, is given in the book: P.P. Maltsev et al. "Digital Integrated Circuits: A Guide. -M .: Radio and Communications, 1994, p. 83 and can be implemented, for example, on the K555SP1 chip (see VL Shilo" Popular Digital Circuits ". - M .: Radio and communications, 1987, p. 183).

 The key 3.14 shown in FIG. 7, is intended to control the reading of the value of a number from the output of register 3.16 to the input of register 3.12. By physical nature, the key 3.14 is a two-position controlled switch. Schemes of controlled switches are known and are given, for example, in the book: V.L. Shilo "Popular CMOS chips, a reference." -M .: Jaguar, 1993, p. 22.

 The key 3.15 is identical to the key 3.14 shown in FIG. 7, and is intended to control the reading of the value of the number from the output of register 3.16 to the first input of the multiplier 3.10.

 Register 3.16 is intended to store the value of the number received from the output of the unit for calculating the remainder of division 3.18. The register scheme 3.16 is known and is given, for example, in the book: V.A. Batushev, B.N. Veniaminov et al. Microcircuits and their application: Reference manual. - M.: Radio and Communications, 1983, p. 134, Fig. 4.34, and can be implemented, for example, on the K 531IR19 microcircuit (see V. L. Shilo, “Popular Digital Microcircuits.” - M.: Radio and Communication, 1987, p. 120).

 The switching unit 3.17 is identical to the switching unit 3.7 shown in FIG. 4, and is intended to switch the hashing 3 operation from the read mode of the secret key value to the read mode of the intermediate value of the hashed noise-resistant cryptogram block to the first input of the division remainder 3.18. The division remainder 3.18 is identical to the remainder 3.5, shown in FIG. 9, and is intended to find the remainder of dividing the value of the dividend number read from the output of the switching unit 3.17 by the value of the prime number p stored in register 3.19.

 Register 3.19 is designed to store the value of a prime p. The register scheme 3.19 is known and is given, for example, in the book: V.A. Batushev, V.N. Veniaminov et al. Microcircuits and their application: Reference manual. -M.: Radio and Communications, 1983, p. 134, Fig. 4.34, and can be implemented, for example, on the K 531IR19 microcircuit (see VL Shilo “Popular Digital Microcircuits.” - M .: Radio and Communication, 1987, p. 120).

 The OR element 3.2.0 is intended for supplying a signal coming from the output of comparator 3.11, or a signal sprinkling from the output of comparator 3.13 to the control input of switch 3.9. The OR 3.21 element is designed to supply a signal coming from the output of the comparator 3.11 or a signal coming from the output of the inverter 3.22 to the control input of the key 3.15. Schemes of elements OR 3.20 and 3.21 are identical, known and given, for example, in the book: S.A. Biryukov "Digital devices on MOS integrated circuits." - M .: Radio and communications, 1990, p. 5 and can be implemented, for example, on the chip 176LE5.

 The inverter 3.22 is designed to invert the binary signal from the output of the comparator 3.13, and issue it to the second input of the OR 3.21 element. The inverter circuit 3.22 is known and is given, for example, in the book: S.A. Biryukov "Digital devices on MOS integrated circuits." - M .: Radio and communications, 1990, p. 8 and can be implemented, for example, on the chip 176LP11.

 The secret key memory module 4 is designed to store the value of the secret key and provide it to the input of the secret key of the hashing unit 3. As a memory module of the secret key 4, a static random access memory (RAM) can be used, the construction scheme of which is known and is given, for example, in book: B.A. Batushev, B.N. Veniaminov et al. "Microcircuits and their application: Reference manual". - M.: Radio and Communications, 19S3, p. 175, Fig. 5.12. The secret key memory module 4 can be implemented, for example, on a memory chip K 537RU8 (see V.I. Korneychuk, V.P. Tarasenko, "Computing devices on microcircuits: A Reference." -K .: Tekhnika, 1988, p. 85 -87).

 The switching unit 5 is identical to the switching unit 3.7 shown in FIG. 4 and is intended to switch the operation of the device from the value mode of the starting block of binary symbols to the input mode of the value of the noise-resistant block of the cryptogram corresponding to the hashed noise-resistant block of the cryptogram selected in the previous step, to the first information input of the hash block 3.

 The memory module of the starting block 6 is designed to store the value of the starting block of binary characters and output it to the input of the switching unit 5. As a memory module of the starting block 6, a static random access memory (RAM) can be used, the construction scheme of which is known and is given, for example, in book: V.A. Batushev, V.N. Veniaminov et al. "Microcircuits and their application: Reference manual". - M .: Radio and communications, 1983, p. 175, fig. 5.12. The memory module of the starting block b can be implemented, for example, on a memory chip K537RU8 (see V.I. Korneychuk, V.P. Tarasenko, "Computing devices on microcircuits: a Reference." -K.: Tekhnika, 1988, p. 85- 87).

 The memory module of the cryptogram block 7 is designed to record the value of the noise-resistant cryptogram block corresponding to the selected hashed noise-resistant cryptogram block, storing and issuing it to the input of the direct communication channel. As a memory module of cryptogram unit 7, a static random access memory (RAM) can be used, the construction scheme of which is known and is given, for example, in the book: V.A. Batushev, V.N. Veniaminov et al. "Microcircuits and their application: Reference manual". - M.: Radio and communications. 1983, p. 175, fig. 5.12. The memory module of the cryptogram unit 7 can be implemented, for example, on a memory chip K537RU8 (see V.I. Korneychuk, V.P. Tarasenko "Computing devices on microcircuits: A reference book." -K.: Tekhnika, 1988. p. 85- 87).

 The memory module of the previous cryptogram block 8 is intended for recording the value of the noise-resistant cryptogram block corresponding to the selected hashed cryptogram block, storing and delivering it to the input of the switching unit 5. As a memory module of the previous cryptogram block 8, a static random access memory (RAM) can be used, circuit whose construction is known and given, for example, in the book: V.A. Batushev, V. N. Veniaminov and others. "Microcircuits and their application; Reference manual". - M.: Radio and Communications, 1983, p. 175, Fig. 5.12. The memory module of the previous block of cryptogram 8 can be implemented, for example, on a memory chip K 537RU8 (see V.I. Korneychuk, V.P. Tarasenko "Computing devices on microcircuits: a Reference." -K .: Tekhnika, 1988, p. 85-87).

 Switch 9 is identical to switch 3.5.3 shown in FIG. 6, and is intended to switch the operation of the device from reading the value of the noise-resistant cryptogram block to the input of the hash block 3 into the reading mode to the input of the memory module of the selected cryptogram block 7 and to the input of the memory module of the previous selected cryptogram block 8.

 The memory module of noise-resistant blocks of cryptograms 10 shown in FIG. 10, is designed to store the values of previously generated noise-resistant blocks of cryptograms and read them to the information input of the switch 9. The memory module of noise-resistant blocks of cryptograms consists of a signal address generator 10.1, an address storage register 10.2, a multiplexer, 10.3 and a memory module 10.4. The write permission input (input W) of the address storage register 10.2 is the information input of the memory module of the noise-resistant blocks of cryptograms 10. Control signals are supplied to the input of the signal address generator 10.1 and the control input (input S) of the multiplexer 10.3. The output of the signal generator 10.1 is connected in parallel with the information input (input N) of the address storage register 10.2 and the second information input (input X2) of the multiplexer 10.3. The first information input (input X1) of the multiplexer 10.3 is connected to the output of the address storage register 10.2. The output of the multiplexer 10.3 is connected to the input of the storage module 10.4, the output of the storage module 10.4 is the output of the memory module of noise-resistant blocks of cryptograms 10.

 The signal address generator 10.1 is designed to generate the address of the noise-resistant block of the cryptogram read out from the storage module 10.4 and generate the address corresponding to the selected hashed noise-resistant block of the cryptogram of the noise-resistant block of the cryptogram. The signal address generator 10.1 in physical essence is a counter, the circuit of which is known, is shown, for example, in the book: A.A Sikarev, ON Lebedev "Microelectronic devices for the formation and processing of complex signals", -M. : Radio and communication, 1983, p. 128, fig. 518, and can be implemented, for example, on the K155IE6 microcircuit (see VL Shilo “Popular Digital Microcircuits.” -M .: Radio and Communication, 1987, p. . 90-93).

 The address storage register 10.2 is intended to store the address corresponding to the selected hashed noise-resistant cryptogram block of the noise-resistant cryptogram block. The storage register scheme for address 10.2 is known, for example, is given in the book of V.A. Batushev, V.N. Veniaminov et al. “Microcircuits and their application”: A reference manual. ”- M.: Radio and Communications, 1983, p. 134, Fig. 4.34, and can be implemented, for example, on the K531IR19 chip (see V. L. Shilo "Popular digital microcircuits." - M.: Radio and Communications, 1987, p. 120).

 Multiplexer 10.3 is designed to switch the memory module of noise-resistant blocks of cryptograms 10 from the readout mode of values of N noise-resistant blocks of cryptograms to the reading mode of noise-resistant blocks of cryptograms corresponding to the selected hashed noise-resistant block of cryptograms from the memory module 10.4. The multiplexer circuit 10.3 is known, is given in the book of L.A. Maltseva et al. "Fundamentals of digital technology." -M.: Radio and Communications, 1986, p. 52, Fig. 48, and can be implemented, for example, on the K155KP5 microcircuit (see VL Shilo "Popular Digital Microcircuits". - M .: Radio and Communication, 1987, p. 146).

 The storage module 10.4 is designed to store the values of N noise-resistant blocks of cryptograms.

 The storage module 10.4 is a ROM, the circuit of which is known, is shown, for example, in the book B.A. Batushev, B.N. Veniaminov et al. "Microcircuits and their application: Reference manual". - M.: Radio and Communications, 1983, p. 182, Fig. 5.17 and can be performed, for example, on memory chips of the type K556RT5 (see AA Sikarev, ON Lebedev "Microelectronic devices for the formation and processing of complex signals." -M .: Radio and communications, 1983, p. 133 Table 5.13).

 The memory module of the received cryptogram block 11 is intended for recording the values of the received noise-resistant cryptogram block from the output of the direct communication channel, storing and reading it to the first information input of the identification block 12 and in parallel to the information input of the key 14, as well as to erase the received unidentified noise-resistant cryptogram block. As a memory module of the received block of cryptogram 11, a static random access memory (RAM) can be used, the construction scheme of which is known and is given, for example, in the book: V.A. Batushev, V. N. Veniaminov and others. Microcircuits and their application: a Reference manual. - M.: Radio and Communications, 1983, p. 175, Fig. 5.12. The memory module of the received cryptogram block 11 can be implemented, for example, on the memory chip K537RU8 (see V. I. Korneichuk, V. P. Tarasenko "Computing devices on microcircuits: a Reference." - K.: Tehnika, 1988, p. 85 -87).

The identification unit 12 shown in FIG. 5 is intended to identify the values of the received noise-resistant cryptogram block with the values of N noise-resistant blocks of cryptograms stored in the memory module of the noise-resistant blocks of cryptograms 13. The identification block 12 consists of a comparator 12.1, an address generator 12.2 and a shaper 12.3. The first information input of the comparator 12.1 is the first information input of the identification unit 12, the second information input of the comparator 12.1 is the second information input of the identification unit 12, the output of the comparator 12.1 is connected to the input of the address generator 12.2 and in parallel with the input of the driver 12.3. The output of the address generator 12.2 is the first control output of the identification unit 12. The output of the comparator 12.1 is the second control output of the identification unit 12. The output of the driver 12.3 is the third control output of the identification unit 12.,
Comparator 12.1 for comparing the value of the number received from the output of the memory module of the received cryptogram block 11 with N values of the noise-resistant blocks of cryptograms stored in the memory module of the noise-resistant blocks of cryptograms 13, as well as for generating a control signal from the second control output of the identification block 12 to the control input key 14. This control signal is generated by the comparator 12.1, if the received noise-resistant block of the cryptogram is identified with any of the N noise-resistant blocks of the cryptogram mm The comparator circuit is known, for example, is given in the book of P. P. Maltsev et al. "Digital Integrated Circuits: A Guide. -M.: Radio and Communications, 1994, p. 83 and can be implemented, for example, on the K555SP1 chip (see VL Shilo "Popular digital microcircuits." - M .: Radio and communications, 1987, p. 183).

Address generator 12.2 is designed to generate the address of the noise-resistant cryptogram block read from the memory module of noise-resistant blocks of cryptograms 13. Address generator 12.2 in physical essence is a counter with a control input for resetting the counter to a zero value, the circuit of which is known, for example, see the book: A .A Sikarev, O.N. Lebedev
"Microelectronic devices for the formation and processing of complex signals." -M "Radio and communications, 1983, p. 128, Fig. 5.18, and is implemented, for example, on the K155IE6 microcircuit (see VL Shilo" Popular digital microcircuits ". - M .: Radio and communications, 1987. p. . 90-93).

 Shaper 12.3 is intended for generating a control signal controlling the retransmission of the noise-resistant cryptogram block corresponding to the selected hashed noise-resistant cryptogram block to the message recipient, as well as controlling the erasure of this noise-resistant cryptogram from the memory module of the selected cryptogram block 7. Control signal for retransmission of the noise-resistant block cryptogram block to the message recipient corresponding to the selected hashed noise block cryptograms, is formed if the received noise-resistant block of the cryptogram is unidentified. In this case, the control signal controls the erasure of the received noise-resistant cryptogram block from the memory module of the received cryptogram block 11. The shaper circuit 12.3 is known, in its physical nature it is an inverter and is identical to the inverter 3.22 circuit.

 The memory module of noise-resistant blocks of cryptograms 13 is designed to store noise-resistant blocks of cryptograms and read them to the input of the identification block 12. As a memory module of noise-resistant blocks of cryptograms 13, a static random access memory (RAM) can be used, the construction scheme of which is known and is given, for example, in book: V. A. Batushev, B. N. Veniaminov and others. Microcircuits and their application: Reference manual. -M. : Radio and communication, 1983, p. 175, fig. 5.12. The memory module of noise-resistant blocks of cryptograms 13 can be implemented, for example, on a memory chip K537RU8 (see V.I. Korneychuk, V.P. Tarasenko "Computing devices on microcircuits: a Reference." -K .: Tehnika, 1988, p. 85 -87).

 The key 14 is identical to the key 3.14 shown in FIG. 7, and is intended to control the reading of the received identified noise-resistant cryptogram block from the output of the memory module of the received cryptogram block 11 to the second information input of the hash block 16 and in parallel to the input of the memory module of the previous received cryptogram block 18. Reading is allowed when a control signal is received from the third control output of the block identification 12 to the control input of the key 14.

 The secret key memory module 15 is intended for storing the secret key and issuing it to the input of the secret key of the hashing unit 16. As a secret key memory module 1.5, a static random access memory (RAM) can be used, the construction scheme of which is known and is given, for example, in the book : V.A. Batushev, V.N. Veniaminov et al. "Microcircuits and their application: Reference manual". - M.: Radio and Communications, 1983, p. 175, Fig. 5.12. The secret key memory module 15 can be implemented, for example, on a memory chip K537RU8 (see V.I. Korneychuk, V.P. Tarasenko, "Computing devices on microcircuits: a Reference." -K .: Tekhnika, 1988, p. 85- 87).

 The hash unit 16 is identical to the hash unit 3 shown in FIG. 3, and is designed to hash the received identified noise-resistant cryptogram block by hashing function, secret key and the starting block of binary symbols when decrypting the first information block of q-decimal symbols or by the previous received identified noise-resistant cryptogram block when decrypting the next information block of q-decimal symbols.

 The switching unit 17 is identical to the switching unit 3.7 shown in FIG. 4, and is designed to switch the operation of the device from reading the value of the starting block of binary symbols to decrypting the first information block of q-ary symbols to the reading mode of the previous received identified noise-resistant block of cryptogram when decrypting the next information block of q-ary symbols to the first information input of the hashing block 16.

 The memory module of the previous received cryptogram block 1.8 is intended for recording the received identified noise-resistant cryptogram block, storing and issuing it to the second input of the switching unit 17. As a memory module of the previous received cryptogram block 18, a static random access memory (RAM) can be used, the construction scheme of which known and given, for example, in the book: V.A. Batushev, V. N. Veniaminov and others. "Microcircuits and their application: Reference manual". - M .: Radio and communications. 1983, p. 175, fig. 5.12. The memory module of the previous accepted cryptogram block 18 can be implemented, for example, on a memory chip K537RU8 (see V.I. Korneychuk, V.P. Tarasenko "Computing devices on microcircuits: a Reference." -K .: Tehnika, 1988, p. 85-87).

 The memory module of the start block 19 is designed to store the start block of binary characters and read it to the first input of the switching unit 17. As a memory module of the start block 19, a static random access memory (RAM) can be used, the construction scheme of which is known and is given, for example, in book: V.A. Batushev, V.N. Veniaminov et al. "Microcircuits and their application; Reference manual". - M .; Radio and Communications, 1983, p. 175, fig. 5.12. The memory module of the starting block of binary symbols 19 can be implemented, for example, on a memory chip K537RU8 (see V.I. Korneychuk. V.P. Tarasenko "Computing devices on microcircuits: A Reference." -K .: Tehnika, 1988, p. 85-87).

 The claimed device encryption / decryption messages hashing function works as follows.

 Previously, the values of N pre-formed noise-resistant cryptogram blocks are recorded in memory modules of the noise-resistant blocks of cryptograms 10 and 13, the value of the binary characters previously transmitted between the sender and the recipient of messages of the messages of the starting block of messages is written to the memory modules of the start block 6 and 19 and written into the memory modules of the secret key 4 and 15 the value of the secret key previously transmitted between the sender and recipient of messages.

 The information sequence of q-ary characters from the output of the analog-to-digital message converter, not included in the inventive device and not shown in the drawings, is input to the message encryption / decryption device by the hashing function shown in Fig. 1 and is read to the input of the information memory module block 1. As an analog-to-digital message converter can be used, for example, a pulse-code modulation encoder that generates q-ary characters at the output. The splitting of messages represented by an information sequence of q-ary characters is implemented by sequentially writing n consecutive q-ary characters into a memory module of information block 1. Control signals received at the control input of a memory module of information block 1 and controlling the recording of n q-ary characters of the first and subsequent information q-ary symbols are shown in FIG. 12 (a). According to the zero level sending signal shown in FIG. 12 (m) applied to the control input (input S) of multiplexer 2.6, which is the second control input of selection block 3, the second information input (input Y) of multiplexer 2.6 is turned off and its output is written to all memory cells of the storage register with a minimum of 2.5 blocks select 2 information signal in the form of a code combination consisting of single characters "1", which ensures the initial filling of the storage register of the minimum amount of 2.5 with the maximum value of the stored number.

 To encrypt the first information block of q-ary characters, N error-correcting blocks of cryptograms are hashed by the hash function, the secret key and the start block of binary symbols in the hash block 3. For this, the value of the secret key stored in the secret key memory module 4 is read N times the secret input the key of the hash block 3 according to the control signal shown in FIG. 12 (b) supplied to the control input of the secret key memory module 4. The value of the starting block of binary characters stored in the memory module of the starting block 6 is read N times to the first input of the switching unit 5 by the control signal shown in FIG. 12 (c) to the control input of the memory module of the starting block 6. To encrypt the first information block of q-ary characters, the first input of the switching block 5 is switched to the output of this block. Such switching is performed upon receipt of a unit level control signal shown in FIG. 12 (d), and provides reading the value of the starting block of binary symbols to the first information input of the hash block 3.

 The values of N noise-resistant blocks of cryptograms stored in the memory module of noise-resistant blocks of cryptograms 10 are, alternately, from the first to the Nth, read to the information input of the switch 9 by the control signal shown in FIG. 12 (g) supplied to the second control input of the memory module of noise-resistant blocks of cryptograms 10. These control signals are calculated by the counter 10.1. The output signal of the counter 10.1, which is input to the second information input (input X2) of the multiplexer 10.3, is switched to the input of the storage module 10.4 by applying to the control input (input S) of the multiplexer 10.3 a zero level control signal shown in FIG. 12 (h). In the hash mode of N noise-resistant blocks of cryptograms, the information input of the switch 9 is switched to its first information output under the control of a control signal of a single level arriving at the control input of the switch 9 and shown in FIG. 12 (m). In turn, the first information output of the switch 9 is connected to the second information input of the hash block 3, which provides sequential, from the first to the Nth, reading of the values of N noise-resistant blocks of cryptograms to the second information input of the hash block 3.

 In the hash block 3, the steps of raising the value of the secret key a to the power of the total value of the starting block of binary symbols and the value of the first, and then subsequent, noise-resistant cryptogram block, and calculating the result from the value modules of primes p and q are performed as sequential actions: the total value is calculated the starting block of binary symbols and the values of the first, and then subsequent, noise-resistant cryptogram block, if the calculated total value is zero, from the output of the block he 3, a single value is read as the value of the hashed noise-resistant cryptogram block. If the calculated total value is unity, then in the block for calculating the remainder of division 3.5, the value of the secret key is calculated modulo the number p, and is read from the output of hash block 3 as the value of the hashed noise-resistant block of the cryptogram. If the calculated total value is neither unit nor zero, then the value of the secret key is multiplied by its own value the number of times equal to the total value reduced by a unit value, the values of the intermediate results of the multiplications are calculated modulo the number q, the final value of the result of the multiplications is calculated modulo the number p, and is read from the output of the hash block 3 as the value of the hashed noise-resistant block of the cryptogram.

 The hashing of the error-correcting cryptogram block in the hash block 3 is performed as follows. The value of the secret key is read into the input of the secret key of the hash block 3. The value of the secret key is recorded by the control signal supplied to the control input of the switching unit 3.17, which is the second control input of the hash block 3. The form of this control signal is shown in Fig. 13 (a). This control signal switches the first information input of the switching unit 3.17 to its output, thereby providing a record of the value of the secret key at the first input of the unit for calculating the remainder of division 3.18. The signal type of the secret key is shown in Fig. 13 (b). From the output of register 3.19, the value of the number p is read at the second input of the unit for calculating the remainder of division 3.18. To record the values of the secret key and the number p and then calculate the remainder of the division, the control signal, the form of which is shown in Fig. 13 (c), is supplied to the control input of the division remainder unit 3.18, which is the third control input of the hash unit 3. In the block for calculating the remainder of division 3.18, the value of the secret key is supplied to the first information input of the key 3.18.5, turned on its output, and is recorded in register 3.18.1. From register 3.18.1, the value of the secret key is fed to the first input of the subtractor 3.18.2. On the second input of the subtractor 3.18.2 sprinkles the value of the number p. The calculated differential value from the output of the subtractor 3.18.2 goes to the second input of the comparator 3.18.4. If the difference value is less than the value of the number p, then the output signal of the comparator 3.18.4, fed to the control input, switches the information input of the switch 3.18.3 to its second output, which is the output of the unit for calculating the remainder of division 3.18. Otherwise, the output signal of the comparator 3.18.4 switches the information input of the switch 3.18.3 to its first output, the difference value from the output of the subtractor 3.18.2 is written to the register 3.18.1, the value of the number p is subtracted from the subtractor 3.18.2, and the described earlier actions are repeated.

 Since in this case the value of the number p is greater than the value of the secret key a, and therefore a mod p = a, then the value a is written to the register 3.16 from the output of the unit for calculating the remainder of division 3.18. The control input of the key 3.14, which is the fifth control input of the hashing unit 3, is supplied with a control signal, the form of which is shown in FIG. 13 (g). This control signal opens the key 3.14 and, through the public key 3.14, the value a written in register 3.16 is transferred to register 3.12.

 The first and second inputs of adder 3.1, which are the first and second information inputs of the hash block 3, read the value of the starting block of binary symbols and the value of the first, and then subsequent, noise-resistant cryptogram block. Their total value, which is shown in FIG. 13 (e), from the output of the adder 3.1 is read to the first information input of the switching unit 3.3 and the first input of the comparator 3.4. In comparator 3.4, the total value is compared with a zero value and, if they are equal, the signal generated at the output of comparator 3.4 is fed to the control input of switching unit 3.7, allowing a single value signal to pass from the first information input of switching unit 3.7 to its output and recording this signal at the first input of the block calculating the remainder of division 3.5. The control input of the remainder of division 3.5 division block, which is the fourth control input of the hash block 3, receives control signals, the form of which is shown in FIG. 13 (g). From the output of register 3.2 to the second input of the unit for calculating the remainder of division 3.5, the value of q is read. The sequence of actions performed in the unit for calculating the remainder of division 3.5 is identical to the previously described sequence of actions performed in the unit for calculating the remainder of division 3.18. Since the value of the number q is greater than the unit value, and therefore 1 mod q = 1, from the output of the unit for calculating the remainder of division 3.5, the unit value is read to the output of the hash unit 3 as the value of the hashed noise-resistant cryptogram unit. A view of the hashed noise-resistant block of the cryptogram is shown in FIG. 13 (h).

 If the total value read to the input of the comparator 3.4 is not equal to zero, then the control signal from the output of the comparator 3.4 switches the second information input of the switching unit 3.7 to its output. The unit value of the control signal, which is shown in FIG. 13 (e), is fed to the control input of the switching unit 3.3, which is the first control input of the hashing unit 3, and the first information input of the switching unit 3.3 is turned off at its output. The total value from the output of the adder 3.1 through the switching unit 3.3 is read into register 3.6 and copied to the first input of the subtractor 3.8. A unit value is subtracted from the recorded total value in the subtractor 3.8. The value reduced by one is compared in the comparator 3.13 with a zero value and, if they are equal, the signal from the output of the comparator 3.13 through the OR 3.20 element is fed to the control input of the switch 3.9. The value of a from the register 3.12. it is read to the second input of the multiplier 3.10, and in the absence of a second factor, the value of a is read from the output of the multiplier 3.10 to the input of the switch 3.9, switched to its output. The output signal of the comparator 3.4 switches the second information input of the switching unit 3.7 to its output and the value of a is read to the input of the block for calculating the remainder of division Z. 5, in which the value of a mod p is read to the output of the hash unit 3 as the value of the hashed noise-resistant cryptogram block.

 At the same time, the value from the output of the subtractor 3.8 is compared with a single value in the comparator 3.11 and, if they are equal, the output signal of the comparator 3.11 through the OR element 3.20 switches the second information input of the switch 3.9 to its output. The same output signal of the comparator 3.11, inverted in the inverter 3.22, passes through the OR 3.21 element and switches the information input of the key 3.15 to its output. Therefore, the value of a is read from register 3.16 through the public key 3.15 to the first input of the multiplier 3.10 and at the output of the multiplier 3.10 the value a mod p is generated. This value from the output of the multiplier 3.10 through the switch 3.9 and the switching unit 3.7 is fed to the input of the unit for calculating the remainder of division 3.5, in which the previously described actions are performed.

 If the value from the output of the subtractor 3.8 is not equal to either a single or a zero value, then with a zero value of the control signal supplied to the control input of the switching unit 3.3 shown in FIG. 13 (e), this value from the second information block of switching 3.3 is read to its output, and the steps described above are repeated until the value of the secret key in the degree of the total value taken modulo the number is received at the input of the block for calculating the remainder of division 3.5 R.

 The values of the digital representation of the k-th q-ary characters of the i-th hashed error-correcting block of cryptogram read from the hash block 3 are fed to the input (input B) of the subtractor 2.1 of block 2. The form of the 3 hashed noise-tolerant blocks read from the hash block is shown in Fig. 12 (and ) To the second input (input A) of the subtractor 2.1 in accordance with the control signal supplied to the control input of the memory module of the information block 1 shown in FIG. 12 (k), the values of the digital representation of the k-th q-ary characters of the information block are received from the memory module of the information block 1. In the subtractor 2.1, the i-th character (i = 1,2 , .., N) of the hashed error-correcting block of the cryptogram of the corresponding value of the digital representation of the q-symbol of the information block symbol. Adder 2.2 sequentially adds the values of the resulting differences.

 With the arrival of the control signal shown in FIG. 12 (l), to the control input of the controlled switch 2.3, which is the first control input of selection block 2, the obtained value from the output of adder 2.2 is fed to the input (input B) of comparator 2.4 and simultaneously to the first information input (input X) of multiplexer 2.6. The control input (input S) of the multiplexer 2.6, which is the second control input of the selection unit 2, receives a unit level control signal shown in FIG. 12 (m). This control signal comments the output of the adder 2.2 to the input X of the storage register of the minimum amount of 2.5. The second input (input A) of the comparator 2.4 receives the value stored in the storage register of the minimum amount of 2.5. A control signal is generated at the output (output A≥B) of the comparator 2.4, provided that the signal value at the second input (input B) is not greater than the signal value at the first input (input A). This control signal, applied to (input W) permissions to record the minimum register 2.5 storage register, provides the update of the minimum register 2.5 storage register with the signal from the output of the adder 2.2 through the controlled switch 2.3. At every ith step of operation of selection block 2, a new value from the output of adder 2.2 is written to the minimum 2.5 storage register, provided that the newly compared value is less than the stored value in the memory of the minimum 2.5 storage register.

 The control signal generated at the output of comparator 2.4, which is the output signal of selection block 2, is fed to the write enable input (input W) of the storage register of address 10.2 of the memory module of noise-resistant blocks of cryptograms 10 and provides the recording of the next ith value of the block address from the output of the address generator 10.1 address storage register 10.2. A new address value will be written to the address storage register 10.2, provided that a new control signal is generated at the output of the comparator 2.4 of selection block 2. After N cycles of operation of selection block 2, the minimum sum of the differences obtained will be recorded in the minimum amount 2.5 storage register, and the value of the address of the noise-resistant cryptogram block corresponding to the selected hashed noise-resistant cryptogram block will be written in the address storage register 10.2. The selected hashed error-correcting cryptogram block is closest to the first information block of q-ary characters.

 Upon receipt of the zero level control signal shown in FIG. 12 (e), to the control input of the switch 9, its information input is switched to its second information output. Upon receipt of the control signal of the unit level shown in Fig. 12 (h) to the first control input of the memory module of the noise-resistant blocks of the cryptogram 10, the value of the address of the noise-resistant block of the cryptogram corresponding to the selected hashed noise-resistant block of the cryptogram is read from the storage register of the address 10.2 through the multiplexer 10.3 to the input memory module 10.4. The value of the noise-resistant cryptogram block corresponding to the selected hashed noise-resistant cryptogram block is read through the second information output of the switch 9 to the information input of the memory module of the cryptogram block 7 and in parallel to the information input of the memory module of the previous cryptogram block 8. By the same control signal supplied to the control input of the module the memory of the cryptogram block 7 and the control input of the memory module of the previous cryptogram block 8, into the memory module of the cryptogram block 7 and previous block memory unit 8 writes the value of the cryptogram noiseproof cryptogram block corresponding to the selected block hashed IMMUNITY cryptogram.

 Upon receipt of the control signal shown in FIG. 12 (n), to the second control input of the memory module of the cryptogram unit 7, from the information output of this module, the value of the noise-resistant cryptogram block corresponding to the selected hashed noise-resistant cryptogram block is transmitted through the forward communication channel to the message recipient.

 At the receiving node, from the output of the direct communication channel, the received noise-resistant cryptogram block is read to the input of the memory module of the received cryptogram block 11. The recording of n q-ary characters of the noise-resistant cryptogram block is controlled by the control signals received at the control input of the memory module of the received cryptogram block 11, shown in FIG. 12 (o).

 Upon receipt of the control signals shown in FIG. 12 (p), to the control input of the memory module of the received cryptogram block 11, from the output of this module, the value of the received noise-resistant cryptogram block is read to the first information input of the identification block 12. Upon receipt of the control signal shown in FIG. 12 (p), the address generator 12.2 is initialized to the control input of the identification unit 12; I sequentially generates from the first to the Nth addresses of noise-resistant blocks of cryptograms, read from the memory module of noise-resistant blocks of cryptograms 13. From the first to the Nth noise-resistant blocks of cryptograms in accordance with the generated address are read to the second information input of the identification unit 12. If the values of the received noise-resistant cryptogram block coincide with one of the noise-resistant cryptogram blocks the comparator 12.1 is triggered and generates a control signal coming from the second control output of the identification unit 12 and the open key 14. If the received noise-resistant cryptogram block is not identified, that is, the comparator 12.1 will not work during the reading of N noise-resistant blocks of cryptograms, (generator 12.3 generates a control signal controlling the retransmission of the error-correcting cryptogram block corresponding to the selected hashed noise-resistant cryptographic block to the message recipient mma, as well as erasing the unidentified received noise-resistant cryptogram block from the memory module of the received cryptogram block 11. This unit level control signal shown in FIG. 12 (c), is generated at the third control output of the identification unit 12. When the cryptogram unit 7 receives this control signal of the zero level at the first control input of the memory module, the noise-resistant cryptogram block corresponding to the selected hashed noise-resistant cryptogram block is erased, and when the signal of the unit level is received, a second transmitting a noise-resistant cryptogram block corresponding to the selected hashed noise-resistant cryptogram block.

 To decrypt the first information block of q-ary symbols, the received identified noise-resistant cryptogram block is hashed by the hash function, the secret key and the start block of binary symbols in the hash block 16. For this, the value of the secret key stored in the memory module of the secret key 15 is read to the input of the secret key the hash unit 16 according to the control signal shown in FIG. 12 (t) to the control input of the secret key memory module 15. The value of the binary character start block stored in the memory module of the start block 19 is read to the first information input of the switching unit 17 by the control signal shown in FIG. 12 (y) supplied to the control input of the memory module of the starting block 19. To decrypt the first information block of q-ary characters, the first information input of the switching block 17 is switched to the output of the block. Such switching is performed upon receipt of a unit level control signal shown in FIG. 12 (f), and provides reading the value of the starting block of binary symbols to the first input of the hash block 16. Through the information output of the public key 14 to the second information input of the hash block 16, the value of the received identified noise-resistant block of the cryptogram is read.

 After writing the value of the secret key, the values of the starting block of binary symbols and the value of the received identified noise-resistant block of the cryptogram to the hashing block 16, the hash of the received identified noise-resistant block of the cryptogram is performed in a manner identical to the hashing of the noise-resistant block of the cryptogram in the hashing block 3.

 From the output of the hash block 16, which is the output of the device, the first decrypted information block of q-ary characters is read.

 To encrypt the next information block of q-ary characters, the form of which is shown in FIG. 12 (a), N noise-resistant cryptogram blocks are re-hashed with a hash function, a secret key and a noise-resistant cryptogram block corresponding to the selected hashed noise-resistant cryptogram block, and perform the following actions. The difference between the actions performed and the actions during encryption / decryption of the first information block of q-ary characters is as follows.

 At the transmitting unit, the control input of the switching unit 5 receives the control signal of the zero level, shown in FIG. 12 (d), and provides reading the value of the noise-resistant cryptogram block corresponding to the selected hashed noise-resistant cryptogram block to the first information input of the hashing block 3. The value of the noise-resistant cryptogram block corresponding to the selected noise-resistant cryptogram block stored in the module of the previous cryptogram block of the second input 8 is read the switching unit 5 by the control signal shown in FIG. 12 (x) to the control input of the memory module of the previous block of cryptogram 8. To encrypt the next information block of q-ary characters, the second information input of switching block 5 is switched to the output of the same block, which ensures that the values of the noise-resistant block are read to the information input of the hash block 3 cryptograms corresponding to the selected hashed noise-resistant cryptogram block. Subsequent actions when encrypting the next information block of q-ary characters are performed identically to actions when encrypting the first information block of q-ary characters.

 At the receiving node, the value of the previous received identified noise-resistant cryptogram block stored in the memory module of the previous received cryptogram block 18 is read to the second information input of the switching block 17 by the control signal shown in FIG. 12 (c) supplied to the control input of the memory module of the previous received cryptogram block. To decrypt the next information block of q-ary characters, the second information input of the switching block 17 is switched to the output of the same block. Such switching is performed when a control signal of the zero level shown in FIG. 12 (f).

 To decrypt the next information block of q-ary symbols, the received identified noise-resistant cryptogram block is hashed by the hash function, the secret key and the previously received identified noise-resistant cryptogram block in the hash block 16. The hash of the received identified noise-resistant cryptogram block by the hash function, the secret key and the previous received the noise-resistant cryptogram block in the hash block 16 are executed and identical to the hashing actions of the received identified error-correcting cryptogram block according to the hashing function, the secret key and the starting block of binary symbols.

 The next decrypted information block of q-ary characters is read from the output of the hash block 16, which is the output of the device, and the described actions are performed until the next information blocks of q-ary characters arrive.

Claims (4)

 1. A method of encrypting / decrypting messages with a hashing function, which consists in preliminarily generating a hash function, a secret key and a starting block of binary characters, transmitting between the sender and receiver of messages a secret key and a starting block of binary characters, splitting the message into information blocks of characters, hashing the sender of message blocks binary characters, transmitting to the message recipient binary character blocks and hashing the received binary character blocks, characterized in that additionally, N noise-resistant blocks of cryptograms are preliminarily formed, where N> 2, noise-resistant blocks of cryptograms are hashed by hashing function, secret key and start block of binary symbols, each i-th one is compared, where i = 1, 2, ..., N, hashed noise-tolerant a cryptogram block with a first information block of q-ary symbols, where q> 2, among the N hashed noise-resistant blocks of cryptograms, the one closest to the first information block of q-ary symbols is selected, transmitted via a direct communication channel to the message recipient the noise-resistant cryptogram block corresponding to the selected hashed noise-resistant cryptogram block, identify the received noise-resistant cryptogram block with N noise-resistant cryptogram blocks and, if it is not identified, erase the received noise-resistant cryptogram block and transmit the control signal for the error transmission block to the receiver for receiving the cryptogram corresponding to the selected hashed error-correcting cryptogram block, received ID a cryptogram that has been authenticated as a noise-proof block hash by a hash function, a secret key and a binary start block, N hash blocks of a cryptogram is hashed by a hash function, a secret key and a noise-resistant cryptogram block corresponding to the hashed noise-resistant block of a cryptogram selected in the previous step, compare each cryptogram where i = 1, 2, ..., N, the hashed noise-resistant cryptogram block with the next information block of q-ary characters, choose among N interference of stable blocks of cryptograms closest to the next information block of q-ary characters, transmit a noise-resistant cryptogram block corresponding to the selected hashed noise-resistant block of cryptograms via a direct communication channel to the received cryptogram block, the received noise-resistant block of cryptograms with N noise-resistant blocks of cryptograms are identified, and if they are not identified, the received noise-resistant block of the cryptogram and transmit a control signal for reverse transmission over the reverse communication channel the message teacher of the noise-resistant cryptogram block corresponding to the selected hashed noise-resistant cryptogram block hash the received identified noise-resistant cryptogram block by the hash function, the secret key and the previous identified identified noise-resistant cryptogram block, while re-hashing the noise-resistant cryptogram blocks until The next information blocks of q-ary characters arrive.  2. The method according to claim 1, characterized in that the formation of N error-correcting blocks of cryptograms is performed by multiplying each of the N blocks of binary symbols by a generating matrix of a binary error-correcting code.  3. The method according to claim 1, characterized in that for comparing each i-th, where i = 1, 2, ..., N, a hashed noise-resistant cryptogram block with an information block of q-ary symbols from the value of each q-ary sample the i-th hashed noise-resistant cryptogram block subtract the corresponding value of the q-ary sample of the information block of q-symbols, for each i-th hashed noise-resistant cryptogram block, the absolute values of the received differences are summed, and the closest hashed noise-resistant crypto block grams to the information block of q-ary characters choose the corresponding minimum sum of the differences.  4. A device for encrypting / decrypting messages with a hashing function, comprising, on the transmitting node, a memory module of the information block whose input is the input of the device, a hash block whose secret key input is connected to the output of the secret key memory module, the first information input of the hash block is connected to the output of the switching block , the first input of the switching unit is connected to the output of the memory module of the starting block, the second input of the switching unit is connected to the output of the memory module of the previous selected crypto block frames, the memory module of the selected cryptogram block, the information output of which is connected to the input of the direct communication channel, and at the receiving node, the memory module of the received cryptogram block, the input of which is connected to the output of the direct communication channel, a hashing block, the secret key of which is connected to the output of the secret memory module key, the first information input of the hash block is connected to the output of the switching block, the first input of the switching block is connected to the output of the memory module of the starting block, the second input of the switching block is connected is connected to the output of the memory module of the previous received cryptogram block, characterized in that an additional selection block is introduced at the transmitting node, the first information input of which is connected to the memory module of the information block, the second information input of the selection block is connected to the output of the hash block, the output of the selection block is connected to the information the input of the memory module of noise-resistant blocks of cryptograms, the output of which is connected to the information output of the switch, the first information output of the switch is connected to the second to the formation input of the hash block, the second information output of the switch is connected to the information input of the memory module of the cryptogram block and in parallel to the input of the memory module of the previous cryptogram block, the first control input of the memory module of the cryptogram block is connected to the output of the reverse communication channel, and an identification block is additionally introduced at the receiving node, the first information input of which is connected to the output of the memory module of the received cryptogram block, the second information input of the identification block is connected to the output by the memory module of noise-resistant cryptogram blocks, the first control output of the identification block is connected to the control input of the memory module of noise-resistant cryptogram blocks, the second control output of the identification block is connected to the control input of the key, the third control output of the identification block is connected to the input of the reverse communication channel and in parallel with the module erase input the memory of the received cryptogram block, the information input of the key is connected to the output of the memory module of the received cryptogram block, the information output The key is connected to the second information input of the hash block and in parallel with the input of the memory module of the previous received cryptogram block, the output of the hash block is the output of the device, the memory module of the information block, the selection block, the hash block, the secret key memory module, the switching block, the start memory module block, memory module of the cryptogram block, memory module of the previous cryptogram block, memory module of noise-resistant cryptogram blocks, the switch on the transmitting node, the memory module is accepted addition to the cryptogram blocks, the identification block, the switching block, the secret key memory module, the hashing block, the switching block, the memory module of the previous received cryptogram block, the starting block memory module at the receiving node are provided with control inputs.

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