JP2721582B2 - Secret device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a secret talker suitable for use in, for example, wired or wireless digital communication.

[Prior Art] In communication, when communication contents are confidential, it is necessary to perform confidential communication. In this case, on the transmitting side, the communication data (plaintext) is encrypted, and the encrypted data (ciphertext) is transmitted. Then, on the receiving side, the ciphertext is decrypted into plaintext.

 FIG. 9 shows a conventional secret device.

In the figure, on the transmission side, a plaintext is supplied to an encryption circuit 13 and converted into an encrypted text according to an encryption key 15. The cipher text from the encryption circuit 13 is supplied to the receiving side via a wired or wireless communication section. On the receiving side, the ciphertext is supplied to the decryption circuit 14 and converted into plaintext according to the decryption key 16.

[Problem to be Solved by the Invention] According to the example in FIG. 9, the transmitting side and the receiving side need to have, for example, the same key for encryption and decryption. For this reason, the transmitting side could not freely change the encryption key. However, it is necessary to frequently change the encryption key in order to secure communication secret.

Therefore, the present applicant has previously proposed a secret device capable of freely changing the encryption key (Japanese Patent Laid-Open No. 1-70200). Less than,
This secret talk device will be described.

 FIG. 6 is a block diagram of the transmitting side.

In FIG. 1, reference numeral 20 denotes a pseudo-random signal generation circuit. The pseudo-random signal generation circuit 20 includes a cascade connection stage 1 of six shift registers SR1 to SR6 and a cascade connection stage 1
And a switching circuit 2 for selecting the feedback path.

The load and shift states of the shift registers SR1 to SR6 in the cascade connection stage 1 are controlled by a control signal S / L from a microcomputer 6 as control means. Control signal S / L
Are loaded, initial value data D1 to D6 from the microcomputer 6 are loaded into the shift registers SR1 to SR6. The shift registers SR1 to SR6 operate in synchronization with the clock CK.

The switching circuit 2 includes a gate and an inverter. That is, the shift register SR
5 and the control data D7 from the microcomputer 6 are supplied. The output signal of the shift register SR1 is supplied to the AND gate 23, and the control data D7 is supplied via the inverter 22. The output signals of the AND gates 21 and 23 are supplied to the OR gate 24. Therefore, the control data
OR gate 24, depending on whether D7 is high or low
Outputs the output signal of the shift register SR or SR5.

The exclusive OR gate 25 has an OR gate.
24 output signals are supplied and the shift register SR6
Are supplied. Then, the output signal of the exclusive OR gate 25 is fed back to the shift register SR1. Therefore, when the shift registers SR1 to SR6 perform the shift operation, the shift register SR6 outputs the initial value data D1 to D6 and the pseudo random signal according to the selection of the switching circuit 2.

Reference numeral 5 denotes an encryption key setting means. The encryption key setting means 5 includes seven connection switches for selecting a high level or a low level. One end of each of these seven connection switches is connected to a power supply terminal, and the other end is connected to terminals Pi1 to Pi7 of the microcomputer 6.

Reference numeral 3 denotes a storage circuit constituted by, for example, a ROM (Read Only Memory). The storage circuit 3 stores initial value data D1 to D6 supplied to the shift registers SR1 to SR6 of the cascade connection stage 1, and a switching circuit. Control data D7 supplied to 2
Are stored in plural sets.

In this case, address data corresponding to the encryption key set by the encryption key setting means 5 is supplied from the microcomputer 6 to the storage circuit 3, and the corresponding initial value data D1 to D6 and control data D7 are read. The initial value data D1 to D6 and the control data D7 are stored in the microcomputer 6
Are supplied to the shift registers SR1 to SR6 and the switching circuit 2 via the terminals Po1 to Po7, thereby initializing the pseudo random signal generation circuit 20.

The address data from the microcomputer 6 is converted into a serial signal by the parallel / serial conversion circuit 4 and output.

Reference numeral 7 denotes an encryption circuit constituted by an exclusive OR gate. The encryption circuit 7 includes a pseudo random signal from the pseudo random signal generation circuit 20 and serial data from a data generation means (not shown). (For example, audio data), and the serial data is encrypted.

Reference numeral 8 denotes a data / control signal switching circuit. The switching circuit 8 includes address data output from the conversion circuit 4, encrypted data output from the encryption circuit 7, and a synchronization signal from the synchronization signal generation circuit 9. Is supplied.
Under the control of the microcomputer 6, these signals are switched in synchronization with the clock CK and output to a wired or wireless communication line. FIG. 8 shows a configuration example of the communication signal.

In this way, on the transmitting side, the data is encrypted according to the setting of the encryption key by the encryption key setting means 5 and output to the communication line together with the synchronization signal and the address signal.

FIG. 7 is a block diagram of the receiving side. In FIG. 7, parts corresponding to those in FIG. 6 are denoted by the same reference numerals.

In the figure, a signal from a communication line is supplied to a synchronization signal detection circuit 12 via a data / control signal switching circuit 8, and a synchronization signal (see FIG. 8) detected by the synchronization signal detection circuit 12 is a microcomputer. 6.

The switching circuit 8 includes a microcomputer 6
The control signal and the clock CK are supplied according to the synchronization signal. Then, the address data included in the signal from the communication line is converted by the switching circuit 8 into a parallel signal by the serial / parallel conversion circuit 10, and then supplied to the microcomputer 6. Then, the address data is supplied from the microcomputer 6 to the storage circuit 3, and the corresponding initial value data D1 to D6 and the control data D7 are read. The initial value data D1 to D6 and the control data D7 are supplied to the shift registers SR1 to SR of the pseudo random signal generation circuit 20 via the terminals Po1 to Po7 of the microcomputer 6.
It is supplied to R6 and the switching circuit 2. Thereby, the pseudo random signal generation circuit 20 is initialized.

In this case, the storage contents of the storage circuits 3 on the reception side and the transmission side are the same, and the pseudo random signal generation circuits 20 on the reception side and the transmission side have the same configuration. Generates a pseudo-random signal similar to that on the transmitting side.

Reference numeral 11 denotes a decoding circuit constituted by an exclusive OR gate. The decoding circuit 11 is supplied with the pseudo random signal from the pseudo random signal generation circuit 20 and the encrypted data from the switching circuit 8. , The encrypted data is decrypted and output.

As described above, according to the secret talk apparatus shown in FIGS. 6 and 7, there is no need to input the decryption key on the receiving side, and the encryption key can be freely changed on the transmitting side.

By the way, ciphers always have a risk of being decrypted by a third party, and a device with higher confidentiality is required.

In view of the above, the present invention provides a confidential communication device with further enhanced confidentiality.

[Means for Solving the Problems] The secret device according to the first invention is configured as follows.

On the transmission side, a first pseudo-random signal generation circuit configured using a first shift register, encryption key setting means for setting an encryption key, and an output signal of the first pseudo-random signal generation circuit An encryption circuit for encrypting input data according to the first and second pseudo-random signal generation circuits; a stage number setting data for setting a stage number of the first shift register for outputting to the encryption circuit; A first memory storing initial setting data including tap position setting data for setting a tap position for selecting the number of stages of the first shift register for feeding back to the first shift register.
And the initial setting data is read from the first storage circuit by using the address data corresponding to the encryption key from the encryption key setting means, and the number of stages of the first shift register is set based on the stage number setting data. And first control means for setting tap positions based on the tap position setting data, respectively, and the output data of the encryption circuit and the address data are transmitted.

On the receiving side, a second pseudo-random signal generation circuit constituted by using a second shift register, and a decoding circuit for decoding data received by an output signal of the second pseudo-random signal generation circuit And the initial value data of the second pseudo-random signal generation circuit, the stage number setting data for setting the stage number of the second shift register to be output to the decoding circuit, and feedback to the second shift register. A second storage circuit storing initial setting data including tap position setting data for setting a tap position for selecting the number of stages of the second shift register for the second shift register, and initializing data from the second storage circuit based on the received address data. The setting data is read, and the second shift register in the second pseudo-random signal generator sets the number of stages and the tap position of the second shift register. And control means are provided.

[Operation] In the first invention, the number of stages and tap positions of the pseudo-random signal generation circuit can be freely set, and the secrecy can be further improved.

[Embodiment] Hereinafter, an embodiment of the first invention will be described with reference to the drawings.

FIG. 1 is a block diagram on the transmitting side. In FIG. 1, parts corresponding to those in FIG. 6 are denoted by the same reference numerals, and detailed description thereof will be omitted.

In this example, the encryption key from the encryption key setting means 5 is supplied to the microcomputer 6 via the encryption key conversion circuit 17 composed of an arithmetic circuit. The conversion circuit 17 is supplied with data on the number of communication times from the microcomputer 6, and the encryption key supplied from the encryption key setting means 5 is changed so as to be different for each communication.

Examples of arithmetic processing for such a change include simple processing such as adding “1” for each communication, to complicated processing such as scrambling, multiplication, division, and various calculations by a PN generation circuit. Conceivable.

Further, in this example, the pseudo random signal generation circuit 20 includes:
It comprises a cascade connection stage 1 of six shift registers SR1 to SR6, and a switching circuit 2 'for switching the number of shift registers to be used and a tap position for feedback. The load and shift states of the shift registers SR1 to SR6
As in the example shown in FIG.
Controlled by S / L.

The output signals of the shift registers SR1 to SR6 are supplied to the exclusive OR gate 26 via the connection switches SW11 to SW16, respectively.
It is supplied to the exclusive OR gate 26 and the encryption circuit 7 via the SW 26. Then, the output signal of the exclusive OR gate 26 is supplied to the shift register SR1.

ON / OFF of the connection switches SW11 to SW16 is controlled by output signals of the tap switching decoder 27, respectively. That is, one of them is turned on, and the tap position for return is set.

ON / OFF of the connection switches SW21 to SW26 is controlled by an output signal of the decoder 28 for switching the number of stages.
That is, one of them is turned on, and the number of stages of the shift register to be used is set.

In this example, the storage circuit 3 stores the initial value data D1 to D1 supplied to the shift registers SR1 to SR6 of the cascade connection stage 1.
D6, a plurality of sets of stage number setting data supplied to the stage number switching decoder 28 and tap position setting data supplied to the tap number switching decoder 27 are stored.

In the above configuration, when transmitting, the conversion circuit 17
The address data corresponding to the changed encryption key is supplied from the microcomputer 6 to the storage circuit 3, and the corresponding initial value data D1 to D6, stage number setting data, and tap position setting data are read out.

Then, the initial value data D1 to D6 are supplied to the shift registers SR1 to SR6 via the terminals Po1 to Po6 of the microcomputer 6, and the initial value data D1 to D6 are supplied to the shift register SR1.
Loaded into ~ SR6 and the initial value is set.

The step number setting data is stored in the terminal Po7 of the microcomputer 6.
Is supplied to the number-of-stages switching decoder 28, and a signal corresponding to the number-of-stages setting data is output from the decoder 28, whereby the on / off of the connection switches SW21 to SW26 is controlled to set the number of stages.

The tap position setting data is supplied to the tap switching decoder 27 via the terminal Po7 of the microcomputer 6, and a signal corresponding to the tap position setting data is output from the decoder 27, whereby the connection switches SW11 to SW
The on / off control of 16 is controlled, and the tap position is set.

As a result, the pseudo random signal generation circuit 20 outputs a pseudo random signal according to the initial values set in the shift registers SR1 to SR6, the set number of stages, and the set tap positions, and the encryption circuit 7 Data is encrypted with this pseudo random signal.

The other parts are the same as in the example of FIG. 6, and the description is omitted.

Next, FIG. 2 is a block diagram of the receiving side. In FIG. 2, portions corresponding to those in FIG. 7 are denoted by the same reference numerals, and detailed description thereof will be omitted.

In this example, the pseudo random signal generation circuit 20 and the storage circuit 3 are configured in the same manner as the transmission side in FIG.

In the above configuration, when receiving, the address data included in the signal from the communication line is supplied from the switching circuit 8 to the microcomputer 6 via the serial / parallel conversion circuit 10. Then, the address data is supplied from the microcomputer 6 to the storage circuit 3, and the corresponding initial value data D1 to D6, stage number setting data and tap position setting data are read out.

Then, the initial value data D1 to D6 are supplied to the shift registers SR1 to SR6 via the terminals Po1 to Po6 of the microcomputer 6, and the initial value data D1 to D6 are supplied to the shift register SR1.
Loaded into ~ SR6 and the initial value is set.

The step number setting data is stored in the terminal Po7 of the microcomputer 6.
Is supplied to the number-of-stages switching decoder 28, and a signal corresponding to the number-of-stages setting data is output from the decoder 28, whereby the on / off of the connection switches SW21 to SW26 is controlled to set the number of stages.

The tap position setting data is supplied to the tap switching decoder 27 via the terminal Po7 of the microcomputer 6, and a signal corresponding to the tap position setting data is output from the decoder 27, whereby the connection switches SW11 to SW
The on / off control of 16 is controlled, and the tap position is set.

In this case, the storage contents of the recording circuits 3 on the reception side and the transmission side are the same, and the pseudo random signal generation circuits 20 on the reception side and the transmission side have the same configuration. A pseudo-random signal similar to that set on the transmitting side is generated similarly.

Therefore, in the decryption circuit 11, the encrypted data from the switching circuit 8 is accurately decrypted by the pseudo random signal, and the data is output.

The other parts are the same as in the example of FIG. 7, and the description is omitted.

Thus, according to the secret device shown in FIGS. 1 and 2, there is no need to input the decryption key on the receiving side, and the transmitting side can freely change the encryption key.

In addition, not only the initial value of the pseudo-random signal generation circuit 20 but also the hardware configuration (the number of stages and the tap positions) are changed according to the encryption key, so that secrecy can be enhanced.

Further, since the encryption key is changed in the conversion circuit 17 so as to be different for each communication, it is possible to keep the communication secret sufficiently without bothering the user.

 Next, an embodiment of the second invention will be described.

FIG. 3 is a block diagram on the transmission side. 3, parts corresponding to those in FIG. 6 are denoted by the same reference numerals, and detailed description thereof will be omitted.

In this example, the encryption key from the encryption key setting means 5 is supplied to the microcomputer 6 via the encryption key conversion circuit 17 composed of an arithmetic circuit. The conversion circuit 17 is supplied with data on the number of communication times from the microcomputer 6, and the encryption key supplied from the encryption key setting means 5 is changed so as to be different for each communication.

Examples of arithmetic processing for such a change include simple processing such as adding “1” for each communication, to complicated processing such as scrambling, multiplication, division, and various calculations by a PN generation circuit. Conceivable.

Further, in this example, the pseudo random signal generation circuit 20
In addition, a pseudo-random signal generation circuit having a similar configuration
20 'is provided. Shift register SR1 of cascade connection stage 1
The load and shift states of .about.SR6 are controlled by a control signal S / L from the microcomputer 6.

The initial setting of the pseudo-random signal generation circuit 20 'is performed by inputting the initial value data D1' to the shift registers SR1 to SR6 of the cascade connection stage 1 from the terminals Po1 to Po6 of the microcomputer 6.
D6 'is supplied and set, and the control data D is supplied to the switching circuit 2 from the terminal Po7 of the microcomputer 6.
7 'is supplied to set a tap position for return. In this case, the initial value data D1 'to D6', the control data D
7 'is a fixed value.

The pseudo-random signal from the pseudo-random signal generation circuit 20 'is supplied to an encryption circuit 7' composed of an exclusive OR gate. The address data converted into serial data by the parallel / serial conversion circuit 4 is supplied to the encryption circuit 7 ', and is encrypted with a pseudo random signal. The encrypted address data from the encryption circuit 7 'is supplied to the data / control signal switching circuit 8.

In the above configuration, when transmitting, the conversion circuit 17
The address data corresponding to the changed encryption key is supplied from the microcomputer 6 to the storage circuit 3, and the corresponding initial value data D1 to D6 and the control data D7 are read. Then, the initial value data D1 to D6 and the control data D7 are sent to the shift registers SR1 to SR of the pseudo random signal generation circuit 20 via the terminals Po1 to Po7 of the microcomputer 6.
This is supplied to R6 and the switching circuit 2, whereby the pseudo-random signal generation circuit 20 is initialized.

As a result, the pseudo random signal generation circuit 20 outputs a pseudo random signal corresponding to the initial values set in the shift registers SR1 to SR6 and the tap position set by the switching circuit 2, and the encryption circuit 7 The data is encrypted by the pseudo random signal, and the encrypted data is supplied to the switching circuit 8.

The initial value data D1 'to D6' and the control data D7 ', which are fixed values, are supplied to the terminals Po1 to Po7 of the microcomputer 6.
Is supplied to the shift registers SR1 to SR6 of the pseudo-random signal generation circuit 20 'and the switching circuit 2, whereby the pseudo-random signal generation circuit 20' is initialized.

As a result, the pseudo random signal generation circuit 20 outputs a pseudo random signal corresponding to the initial value set in the shift registers SR1 to SR6 and the tap position set by the switching circuit 2, and the encryption circuit 7 ' The address data is encrypted with the pseudo random signal, and the encrypted address data is supplied to the switching circuit 8.

Therefore, the switching circuit 8 sends the fifth communication line to the communication line.
A communication signal as shown in the figure is output.

The other parts are the same as in the example of FIG. 6, and the description is omitted.

Next, FIG. 4 is a block diagram of the receiving side. 4, parts corresponding to those in FIG. 7 are denoted by the same reference numerals, and detailed description thereof will be omitted.

In this example, a pseudo random signal generating circuit 20 'having the same configuration as that of the transmitting side is provided. The load and shift states of the shift registers SR1 to SR6 of the cascade connection stage 1 are controlled by a control signal S / L from the microcomputer 6. The initial setting of the pseudo random signal generation circuit 20 'is as follows.
Fixed initial value data D1 'to D6' and control data D7 'are supplied to shift registers SR1 to SR6 and switching circuit 2 from terminals Po1 to Po7 of microcomputer 6.

The pseudo-random signal from the pseudo-random signal generation circuit 20 'is supplied to a decoding circuit 11' composed of an exclusive OR gate. The address data encrypted by the switching circuit 8 is supplied to the decryption circuit 11 '. The output signal of the decoding circuit 11 'is serial /
It is supplied to the parallel conversion circuit 10.

In the above configuration, upon reception, the initial value data D1 'is sent to the pseudo random signal generation circuit 20' from the terminals Po1 to Po7 of the microcomputer 6 based on the synchronization signal included in the signal from the communication line. ~ D6 'and control data D7' are supplied and initialized.

Then, the encrypted address data included in the signal from the communication line is transmitted from the switching circuit 8 to the decryption circuit 11 '.
And decoded by the pseudo random signal from the pseudo random signal generation circuit 20 '.

In this case, the pseudo random signal generation circuits 20 'on the reception side and the transmission side have the same configuration, and fixed initial value data D1'
.. D6 'and control data D7', so that a pseudo-random signal similar to that on the transmitting side is generated from the pseudo-random signal generating circuit 20 'on the receiving side. Therefore, the decoding circuit 11 'correctly decodes and outputs the address data.

The address data from the decoding circuit 11 'is serial /
The data is supplied to the microcomputer 6 via the parallel conversion circuit 10. Then, the address data is supplied from the microcomputer 6 to the storage circuit 3, and the corresponding initial value data D1 to D6 and control data D7 are read out, and the pseudo random signal is generated via the terminals Po1 to Po7 of the microcomputer 6. The data is supplied to the circuit 20 and initialized.

Then, the encrypted data included in the signal from the communication line is supplied from the switching circuit 8 to the decryption circuit 11, and is decrypted with the pseudo random signal from the pseudo random signal generation circuit 20.

In this case, the storage contents of the storage circuits 3 on the reception side and the transmission side are the same, and the pseudo random signal generation circuits 20 on the reception side and the transmission side have the same configuration. Similarly, a pseudo-random signal similar to that of the transmission type is generated. for that reason,
The decoding circuit 11 correctly decodes the data and outputs the data.

The other parts are the same as in the example of FIG. 7, and the description is omitted.

As described above, according to the secret talk apparatus shown in FIGS. 3 and 4, it is not necessary to input the decryption key on the receiving side, and the transmitting side can freely change the encryption key.

In addition, since the address data is also transmitted after being encrypted, it is necessary to decrypt the address data on the receiving side, and the secrecy can be enhanced.

Further, since the encryption key is changed so as to be different for each communication by the conversion circuit 17, the secret of the communication can be sufficiently maintained without bothering the user.

In the above embodiment, the number of shift registers in the cascade connection stage 1 is six, but may be any number.

Further, in the example of FIG. 3 and the example of FIG. 4, the pseudo random signal generation circuits 20 and 20 'have the same configuration, but may have different configurations.

[Effects of the Invention] As described above, according to the first aspect, it is not necessary to input the decryption key on the receiving side, and the encryption key can be freely changed on the transmission side, and the decryption key can be changed according to the encryption key. Therefore, not only the initial value of the pseudo-random signal generation circuit 20 but also the hardware configuration (the number of stages and the tap positions) are changed, so that the secrecy of communication can be sufficiently maintained.

[Brief description of the drawings]

FIGS. 1 and 2 are block diagrams showing an embodiment of the first invention, FIGS. 3 and 4 are block diagrams showing an embodiment of the second invention, and FIG. FIG. 6 is a block diagram on the transmitting side of the confidential communication device, FIG. 7 is a block diagram on the receiving side of the confidential communication device, FIG. 8 is a diagram showing a configuration of a communication signal, and FIG. It is a block diagram of an apparatus. 3 ... memory circuit 4 ... parallel / serial conversion circuit 5 ... encryption key setting means 6 ... microcomputer 7,7 '... encryption circuit 8 ... data / control signal switching circuit 9 ... sync signal generation circuit 10: Serial / parallel conversion circuit 11, 11 ': decryption circuit 12: synchronization signal detection circuit 17: encryption key conversion circuit 20, 20': pseudo-random signal generation circuit

Claims (1)

(57) [Claims] 1. A transmitting side comprising: a first pseudo-random signal generation circuit configured using a first shift register; encryption key setting means for setting an encryption key; An encryption circuit for encrypting input data with an output signal of the generation circuit; and initial value data of the first pseudo random signal generation circuit;
Step number setting data for setting the number of steps of the first shift register to be output to the encryption circuit, and a tap position for selecting the number of steps of the first shift register for feedback to the first shift register are set. A first storage circuit storing initial setting data including tap position setting data, and reading the initial setting data from the first storage circuit using address data corresponding to an encryption key from the encryption key setting means, First control means for setting the number of stages of the first shift register based on the number-of-stages setting data, and respectively setting the tap positions based on the tap position setting data; and output data of the encryption circuit and the address data Is transmitted to the receiving side, and the second pseudo-random signal generation circuit configured using the second shift register is transmitted to the receiving side. When, the a decoding circuit for compositing the received data by the output signal of the second pseudo random signal generation circuit, said second pseudo random signal generation circuit of the initial value data,
A stage number setting data for setting the number of stages of the second shift register to be output to the decoding circuit and a tap position for selecting the number of stages of the second shift register for feedback to the second shift register are set. A second storage circuit storing initial setting data including tap position setting data to be read, and initial setting data read from the second storage circuit based on the received address data. And a second control means for setting the number of taps and the tap position of the second shift register, respectively.