JPH02249333A - Privacy telephone set - Google Patents

Abstract

PURPOSE:To eliminate the need for revision of a key in the case of revising a cipher by providing a pseudo random signal generating circuit, a storage circuit, a control means and a conversion circuit respectively to a transmission side and a reception side, providing a ciphering key setting means, a ciphering circuit to the transmission side and a decoding circuit to the reception side. CONSTITUTION:First and 2nd pseudo random signal generating circuits 1, 2 at the transmission side an the reception side employ shift registers having a feedback path capable of switching and generate various different pseudo random signals by revising the feedback path and the initial value. On the other hand, 1st and 2nd storage circuits 3, 3 store the plural sets of initial values and feedback path setting data of the pseudo random signal generating circuits 1, 2, read the storage content of the storage circuit 3 in response to the setting of a ciphering key setting means 5 to set the pseudo ran dom signal generating circuits 1, 2, thereby generating different pseudo random signals. Then the reception side selects the pseudo random signal from the pseudo random signal generating circuits 1, 2 to make the pseudo random signal identical to the transmission side and the reception side. Thus, it is not required to replace the cipher ing key itself and the setting and revision of the key are attained easily and freely.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a secure communication device in wired and wireless digital communications.

[Prior Art] In wired and wireless communications, if the content of the communication is confidential, it is necessary to perform confidential communication. Therefore, on the sending side, 1
Ordinary data (plaintext) is encrypted and the encrypted data (ciphertext) is communicated over a wired or wireless communication section. Then, on the receiver 1δ side, this ciphertext is encoded into a converted text as a national code.

The fourth jump indicates the conventional confidential story H position. On the sending side,
The encryption circuit 13 uses an encryption key (means for controlling encryption)
Convert plaintext to ciphertext according to 15.

The ciphertext from the encryption circuit 13 is supplied to the receiving side via a wired or wireless communication section.

On the receiving side, a decryption circuit 14 converts the ciphertext into plaintext according to the decryption type (means for controlling decryption) 16.

[Invention tries to solve! ! ! l] In the conventional privacy device shown in FIG. 4, the sender and receiver need to possess the same or independent keys for encryption and decryption. These keys need to be determined in advance according to the cipher, and each time the cipher is changed, a new key must be determined.

Therefore, it is extremely troublesome to set or change the encryption key. However, to ensure the secrecy of communications, it was necessary to frequently change the encryption key.

Therefore, an object of the present invention is to provide a secret communication device that allows easy setting and changing of the cipher without the need to change the key when changing the cipher.

[Means for solving problems] The confidential communication device of the present invention is divided into a transmitting side and a receiving side.

The transmitting side includes a first pseudo-random signal generation circuit using a shift register having a switchable return path, an encryption key setting means for setting an encryption key, and an initial value and feedback path setting data of the pseudo-random signal generation circuit. a first storage circuit that stores a first storage circuit; a first control means that reads initial values and return path setting data from the first storage circuit in accordance with an encryption key, and sets a first pseudo-random signal generation circuit; The present invention includes a 15R conversion circuit that converts the parallel ♦ address signal into a serial address signal, and an encryption circuit that encrypts human data using the output signal of the first pseudo-random signal generation circuit.

Then, the transmitting side transmits the output data of the encryption circuit and the serial address signal.

Further, the receiving side includes a second pseudo-random signal generating circuit having the same configuration as the first pseudo-random signal generating circuit, a second memory circuit that stores the same contents as the first memory circuit, and a parallel circuit for transmitting the received serial address signal. - A second conversion circuit converts into an address signal, and a parallel address signal from the second conversion circuit reads the initial value and feedback path setting data from the second storage circuit, and sets the second pseudo-random signal generation circuit. The apparatus includes a second control means and a country code conversion circuit that converts the received data into a country code based on the output signal of the second pseudo-random signal generation circuit.

[(However, the first and second pseudo-random signal generation circuits on the transmitting side and receiving side use shift registers with switchable feedback paths. Therefore, the 11th return path and the initial value are By changing this, it is possible to generate pseudo-random signals that differ from time to time.

On the other hand, the first and second storage circuits store >U sets of initial nB bα and feedback path setting data of the pseudorandom signal generation circuit. Therefore, different pseudo-random signals can be generated by reading out the contents of the storage circuit and setting the pseudo-random signal generation circuit according to the settings of the encryption key setting means.

That is, on the transmitting side, the type of pseudo-random signal of the first pseudo-random signal generation circuit is determined by the parallel contention address signal according to the setting of the encryption key setting means. This parallel address signal is converted into one serial address word, and one word is sent from the transmitting side to the receiver 11.

The receiving Ig (R1) converts the serial address signal into a parallel address signal and selects the pseudorandom signal of the second pseudorandom signal generation circuit.

Therefore, the pseudo-random signals are the same on the transmitting side and on the receiving side (N%), and encrypted data can be reliably decrypted.

Therefore, by simply changing the encryption key setting means on the sending side, the encryption can be changed without changing the reception.

[Embodiments] Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a block diagram of the transmitting side. The pseudo-random signal generation circuit consists of six stages of shift registers SRI to 5R (
The circuit is comprised of three cascade-connected stages 1 and a switching circuit 2 that selects the feedback path of the cascade-connected stage I.

The loading and shifting states of the shift register of the cascade stage 1 are controlled by the control signal S/L from the microcombi 1-talo which is the control means. When the control 81 word S/L is in the load 4 state, the shift registers SRI to SR6 load the first 1tllfa data Pol to PoO from the microcomputer 6.

In addition, these registers are clock 1 word C.
It operates in synchronization with I(.

The switching circuit 2 is composed of various gates and inverters. That is, the ant gate 21 receives the output signal of the shift register SR5 and the Lu1 Cape No. 18 P07 from the microcomputer 6, and the inverter 22 inverts the control signal Po7. AND gate 23 is a shift
The OR gate 24 receives the output signals of the register SRI and the inverter 22, and the output signals of the AND gates 21 and 23.

Therefore, depending on whether the control signal Po7 is high or low, the shift
The output signal of register SRI or SR5 is OR gate 2
This results in an output signal of 4.

Furthermore, in the switching circuit 2, the exclusive OR gate 25
receives the output signals of OR gate 24 and shift register SRG, and feeds back the exclusive OR result to shift register SRI.

Therefore, when shift registers 5RI-5R6 perform a shift operation, a pseudo-random signal corresponding to the period data and the selection of switching circuit 2 is generated from shift register SRG.

The encryption key setting means 5 is a six-light switch for selecting ground (low) or open/high, and supplies the setting #i to the terminals Pjl to Pi6 of the microcomputer 6.

Read-only memory (RONl) 3 which is a memory circuit
stores the period (+fI) of the shift register of the cascade connection stage 1 and feedback path setting data by the switching circuit 2.

The microcomputer 6 specifies the address of the ROM 3 according to the setting of the encryption key setting means 5, receives the corresponding period value and return path setting data, and outputs the Rpl tall signal Pal.
~Po7 is generated to set the pseudo random signal generation circuit.

Further, the microcomputer 6 generates a parallel address No. 18 at the terminals Pa8 to Po14 in accordance with the setting of the encryption key setting means 5. The twelfth call circuit 4 converts the parallel address signal from the microcomputer 6 into a serial address No. 18 and outputs it.

The scramble circuit 7, which is an encryption circuit, is
Configure the gate. This gate is a pseudo-random IK4
A data/control signal switching circuit that outputs the result of exclusive OR of the pseudo-random signal from the generation circuit and serial data (for example, audio data) from the data generation means (not shown) as a ciphertext. 8 is the serial address No. 18 (ROM address specification υ1) from the conversion circuit 4.
control signal>, ciphertext data (audio data) from the scramble circuit 7, and synchronization signal from the same signal optical 'tE circuit 9 are switched to the rik fH number under the control of the microcomputer 6. , output to a wired or wireless communication line. An example of the timing at this time is shown in FIG.

In this way, on the transmitting side of FIG. 1, data is encrypted according to the settings of the aaa key setting means 5, and is output to the communication line together with the peer signal and the ROM address designation control signal.

FIG. 2 is a block diagram of the receiving side. Blocks that are the same as in FIG. 1 are designated by the same reference numerals, and only the different parts will be described below.

The data/control signal switching circuit 8 receives a signal from the communication line and supplies this signal to the synchronization signal detection circuit x2. same! As shown in FIG. 3, the tilla number detection circuit 12 detects the ll+1 signal included in the signal from the communication line, and notifies the microcomputer 6, which is the second control means, of this detection result.

Roughly speaking, the data/control signal switching circuit 8 is
Control signal P from the microcomputer 6 according to the signal
o17 and clock signal, R from 18 line.
The OM address designation control signal (serial address signal) is supplied to the second conversion circuit 10, and the ciphertext data is supplied to the descrambling circuit 11 which is a (π-external circuit).

The second conversion circuit IO converts the serial address signal into a parallel address signal and supplies it to the terminals Pi8 to P i I /1 of the microcomputer 6.

The microcomputer 6 reads the initial l!II value and the U feedback path setting data from the ROM 3 in accordance with this address (No. 8), and sets the cascade connection stage l and the second pseudo-random signal generation circuit of the switching circuit 2. .

The storage contents of the ROM 3 on the receiving side are the same as the storage contents of the ROM 3 on the transmitting side, and the pseudo random signal generation circuits on the receiving side and the transmitting side are the same. On the side, L. pseudo-Randano, No. 18 is generated.

The descrambling circuit 11 is an exclusive OR gate that receives pseudo-random output from the shift register SR6 and ciphertext data from the data/control switching circuit 8. This configuration is the opposite configuration to the scramble circuit 7 on the transmitting side, so that ciphertext data can be converted to plaintext data.

While the foregoing describes preferred embodiments of the invention,
Various modifications may be made without departing from the spirit of the invention.

For example, the number of shift registers in the cascaded stages may be any number, and the feedback path may be the output of any shift register.

[Effects of the Invention] As described above, according to the secret communication device of the present invention, keys can be easily and freely set and changed on the sending and receiving sides without replacing the encryption key itself.

8...Data/control i3u I, No. 1 Ritori))・E circuit 11...1! encoding circuit

[Brief explanation of drawings]

FIG. 1 is a block diagram of a transmitting side according to the present invention, FIG. 2 is a block diagram of a receiver according to the present invention, FIG. 3 is a timing diagram of communication according to the present invention, and FIG. FIG. 2 is a block diagram of a secret device.

Claims (1)

[Claims] (1) The transmitting side includes a first pseudo-random signal generation circuit using a shift register having a switchable return path, an encryption key setting means for setting an encryption key, an initial value of the pseudo-random signal generation circuit, and an encryption key setting means for setting an encryption key. a first storage circuit that stores return path setting data; and a first control that reads the initial value and return path setting data from the first storage circuit in accordance with the encryption key and sets the first pseudorandom signal generation circuit. means, a first conversion circuit that converts a parallel address signal into a serial address signal according to the encryption key, and an encryption circuit that encrypts input data using an output signal of the first pseudorandom signal generation circuit. transmitting the output data of the encryption circuit and the serial address signal, the receiving side comprising: a second pseudorandom signal generation circuit having the same configuration as the first pseudorandom signal generation circuit; and the first storage circuit. a second memory circuit that stores the same content; a second conversion circuit that converts the received serial address signal into a parallel address signal; and a parallel address signal from the second conversion circuit that causes the second memory circuit to a second control means for reading out the initial value and feedback path setting data from and setting the second pseudo-random signal generation circuit; and an output signal of the second pseudo-random signal generation circuit;
A secret communication device comprising a decoding circuit that decodes received data.