KR100287067B1 - Internal controller of cryptographic algorithm chip which enables the generation of multiple key streams - Google Patents

Abstract

PURPOSE: A device for controlling internal of a password algorithm chip is provided to generate password algorithms of a plurality of channels with one chip by generating a plurality of password key streams without breaking the synchronization of each algorithm. CONSTITUTION: An input register(201) converts parallel data inputted from an external processor into serial data. The input register(201) outputs the data converted. A linear feedback shift register(202) converts the serial data into linear feedback data. In addition, the linear feedback shift register(202) outputs the data converted. An output register(205) converts the serial data outputted from the linear feedback shift register(202). The output register(205) outputs the data converted to the outside. An output latch circuit(206) latches the parallel data outputted from the output register(205). In addition, the output latch circuit(206) provides the data to the outer processor. A control signal generator(207) respectively generates an output signal for controlling the input register(201), the linear feedback shift register(202), the output register(205) and the output latch circuit(206). A key stream/register selection circuit(211) is connected between the linear feedback shift register(202) and the output register(205). In addition, the key stream/register selection circuit(211) outputs data among key stream data and data outputted from a plurality of shift register according to an output signal of the control signal generator(207).

Description

Internal controller of cryptographic algorithm chip which enables the generation of multiple key streams}

The present invention relates to an internal control apparatus of a cryptographic algorithm chip that enables the simultaneous output of multiple independent cryptographic keystreams as one algorithm chip.

The present invention can be obtained by adding an additional circuit to the "external connection device of the information protection algorithm chip that can be easily accessed by a general processor" filed December 21, 1996 (Applicant No. 69799) Device.

TECHNICAL FIELD The present invention relates to the design of a cryptographic algorithm chip used in a communication information protection system for preventing a third party from illegally finding out key communication information between parties. The communication information protection system encrypts and transmits the information on one side, and decrypts the information on the other side that receives the encrypted information to obtain accurate information. In order for such encrypted communication to be possible, the communication party must have the same encryption algorithm chip first, and the input data of the encryption algorithm called a key must be the same, and third, the encryption algorithm chip at the same time when the keys are the same Synchronization of the key to be entered must be correct. In a conventional communication information protection system for a general two-way communication system that transmits and receives simultaneously within a device, an encryption algorithm chip for encryption and an encryption algorithm chip for decryption must exist separately. The reason why the chip must exist separately is that the sharing of the algorithm chip with the transmitting part and the receiving part is required because the synchronization of the keys is applied independently between the transmit part and the receive part in the communication information protection system. It was impossible.

A general communication system receives a signal from the other party when transmitting from one side, and receives from the other side when transmitting from the other side. The system in which communication in both directions can occur at the same time is called a full duplex communication system. In the case of encrypted communication, an encryption operation occurs on the sending side and a decryption operation occurs on the receiving side. In the two-way communication system, since sending and receiving are performed together, encryption and decryption occur independently and simultaneously. Therefore, at least two encryption algorithm chips are required for encryption communication. In addition, when the independent channels such as PCM (Pulse Code Modulation) transmitters encrypt the multiplexed system, multiple encryption algorithm chips that are proportional to the number of multiplexed channels have to be adopted. Adopting multiple cryptographic algorithm chips presents the following disadvantages. In other words, the cryptographic algorithm chip requires a very high degree of integration to achieve high density, so the cost of the chip itself is very expensive, and the price of the cryptographic system also increases. But there is also the disadvantage that the hardware of crypto systems grows.

In order to solve the above problems, the present invention has been focused on the following points. Compared to the data rate of the channel which is usually only a few tens of Kbps, the operation speed of the algorithm chip is now possible up to several tens of MHz. Thus, the multiple operation of the algorithm chip enables the generation of several encryption keystreams by operating one chip. The problem is how these multiple operations get a continuous keystream without breaking the synchronization of each algorithm. To solve this problem, we devised a way to read the shift register value of the linear feedback shift register constituting the algorithm during the operation of the algorithm. In other words, for the A channel encryption communication, the initial value is written (hereinafter referred to as Write), and then the keystream is read (hereinafter referred to as Read). Read the data in the shift register of the linear feedback shift register in the created chip and store it in the memory area designated by the processor. Then, the algorithm initial value of the B channel is written to obtain a keystream of the B channel. When the keystream of A channel is needed again, the value in the shift register of the linear feedback shift register of the B channel is read and stored in the memory area designated by the processor. Write to the algorithm chip exactly as you do. Then read the keystream to get the keystream contiguous with the previous keystream for channel A. If you need a keystream for the B channel again, just repeat the same operation. With this operation, it is possible to obtain keystreams of several channels as one chip. In order to achieve this design goal, reading the data in the chip should be divided into reading the key stream value and reading the shift register value, and selecting the method when the processor reads the chip (Reg / Key selection signal).

The present invention provides an input register for converting and outputting parallel data input from an external processor into serial data, a linear feedback shift register for converting and outputting the serial data into linear feedback data, and an output from the linear feedback shift register. An output register for converting serial data into parallel data and outputting it to the outside; an output latch circuit for latching parallel data output from the output register and supplying data to the external processor; A control signal generator for generating an output signal for controlling each of the input register, the linear feedback shift register, the output register, and the output latch circuit by inputting only a read / write signal which is a control signal, and the linear feedback shift A keystream connected between a register and the output register, for outputting any one of keystream data which is a nonlinear defect output of the linear feedback shift register and data output from a plurality of shift registers according to an output signal of the control signal generator It further comprises a / register selection circuit.

1 is an external connection diagram of an algorithm chip.

2 is a block diagram of an internal control apparatus of an encryption algorithm chip capable of generating a plurality of encryption keystreams according to the present invention.

3 is a processor signal conversion circuit diagram.

4 is an initial value write and register read signal generator circuit diagram.

5 is a circuit diagram of a keystream read signal generator.

<Explanation of symbols for main parts of drawing>

201: input register 202: linear feedback shift register

203: linear connection logic circuit 204: shift register

205: output register 206: output latch circuit

207: control signal generator 209: clock divider

208: initial value recording signal and keystream read signal generator

210: operation / input selection circuit 211: keystream / register selection circuit

Hereinafter, with reference to the accompanying drawings will be described an example of the present invention;

1 is an external connection diagram of an encryption algorithm chip according to the present invention, wherein the data buses D0 to D15 are input signals in the case of initial value write, and output signals in the case of keystream read and register read signals. The read signal / write signal R / W and the chip select signal CE are input signals as connection terminals in both general memory devices. The clock signal CLK is an input signal for receiving a clock for operating this cryptographic algorithm chip. The Reg / Key signal is an input signal that selects whether the processor reads the keystream or the shift register value of the linear feedback shift register. In order to obtain a keystream by operating the algorithm chip, the processor writes the initial value combined with the basic key and the transmission key to the algorithm chip by the number of words (16 bits) predetermined by the size of the linear feedback shift register. Set the Reg / Key signal to Key (0) and read the chip. If a keystream of another channel is needed while reading the keystream, the processor sets Reg / Key to Reg (1), and reads the chip by the number of words (16 bits) predetermined according to the size of the linear feedback shift register. The value is stored in an external fixed memory area and written back to the chip when a continuous key stream is obtained.

FIG. 2 is a diagram showing the internal configuration of the chip of FIG. 1, based on FIG. 1 of "96 Patent Application No. 69799 (External Access Device for Information Protection Algorithm Chip Easily Accessible by a General Processor)", and FIG. 1 The circuit to which the Reg / Key input is added to the write signal and read signal generator 108 of is an initial value write signal and the register / keystream read signal generator 208, and the keystream / register selector circuit 211 is added. It will perform the function of the present invention. The remaining circuit is the same as "96 Patent Application No. 69799".

The input register 201 receives 16-bit parallel data from the processor and automatically transfers the serial data to the shift register which is a component of the linear feedback shift register 202. The basic operation of the algorithm is shown in the original linear feedback shift register 202 is a combination of several non-linear, but only one linear feedback shift register 202 because it is not the scope of the present invention. The linear feedback shift register 202 is configured as a linear connection logic 203 that satisfies the general shift register 204 and the primitive polynomial as the most basic unit of the stream cipher. The output register 205 receives a keystream value made from a nonlinear combination of a plurality of linear feedback shift registers 202 or a register value from which a plurality of shift registers 204 are connected in series and made 16 bits in parallel. The output latch circuit 206 allows the processor to read it. In this case, the circuit for selecting whether the output register 205 accepts the keystream value or reads the value of the serially connected register is the keystream / register selection circuit 211 described above. The control signal generator 207 receives a control signal (CE, R / W, Reg / Key) sent by the processor and plays a role of generating a necessary control signal inside the algorithm chip. Assuming the size of the linear feedback shift register 202 is 64 bits, the processor writes an initial value of 4 words (4X16 = 64 bits) to this algorithm chip. The initial values are sequentially transferred to the shift register 204 of the linear feedback shift register 202 in sequence of 16 bits by the signals generated by the control signal generator 207 every word write. After the initial value of four words has been moved to the shift register 204 of the linear feedback shift register 202, the processor returns Reg / Key to Key (0) and reads this algorithm chip virtually once (dummy read). The registers 202 operate so that their 16-bit keystreams, which are their nonlinear coupling outputs, are transferred to the output registers 205 through the keystream / register selection circuit 211 and finally parallel to the output latch circuits 206. Is entered. After this, the processor sets Reg / Key to Key (0) and reads the keystream that was in the output latch circuit 206. The linear feedback shift register 202 automatically generates the next 16-bit keystream, which is the keystream. It is input to the output latch circuit 206 through the / register selection circuit 211 and the output register 205. Therefore, the processor can obtain a continuous keystream by reading the output latch circuit 206 of the algorithm chip as if the contents of the memory are read. When the processor sets the Reg / Key signal to Reg (1) and reads the chip, the linear feedback shift register 202 does not operate but the current value of the shift register 204 is output. If the current value is stored externally and the continuous keystream of the algorithm is needed again, the current value can be written to the chip to obtain the keystream again. After the initial value is written by the processor and the Reg / Key signal is set to Reg (1) and the chip is read, the written value is read as it is. Therefore, the initial value written by the processor is properly written to the shift register 204 of the linear feedback shift register 202. It has the advantage that it can be used as a tool to test whether it is written.

3 converts the processor signal into an internal signal. In the circuit of FIG. 5 of FIG. 5, the input is Reg / Key and the output is RGR, whereas the input is CE, R / W output is IVW, KSR. IVW is the initial value write signal, KSR is the stream read and RGR is the shift register 204 value read signal of the linear feedback shift register 202.

4 is a circuit for receiving the initial value write signal and the register read signal to generate necessary signals within the circuit. 6 is based on FIG. 6 of "96 Patent Application No. 69799," in which the RGR is added to the circuit of the present invention, compared to one IVW starting point. PE, SEL, CLKIR, and CLKSR signals for controlling the input register 201, operation / input selection circuit 210, shift register 204, and keystream / register selection circuit 211 of FIG.

FIG. 5 generates control signals for receiving various keystream read signals and generating various signals for the processor to read the keystream. &Quot; 96 Patent Application No. 69799, which is based on FIG. 8, in which the CLKLA and CLKOR have been partially changed in the circuit of the present invention. In the CLKWR clock, one clock or two clocks can be changed during one bit keystream period. This clock can be used to control the logic used in stream ciphers, including Stop and Go and Binary rated Multiplier.

Based on the base channel speed of 64 Kbps, the basic channel speed of voice communication and data communication, and operating the clock of the cryptographic algorithm chip at 40 MHz, one chip can cover about 124 channels. appear. Since this assumes only that the processor controls this algorithm, this ratio will drop in a typical communications information protection system. However, in most communication information protection systems, two chips used in both directions can be reduced to one, and communication information protection of communication systems in which 64 Kbps basic channels are multiplexed such as PCM transmission equipment and ISDN (Integrated Services Digital Network) facilities It will be useful for system design.

Claims (1)

An input register for converting and outputting parallel data input from an external processor into serial data; A linear feedback shift register for converting the serial data into linear feedback data and outputting the linear data; An output register for converting serial data output from the linear feedback shift register into parallel data and outputting the same to external data; An output latch circuit for latching parallel data output from the output register and supplying data to the external processor; A control signal for generating an output signal for controlling each of the input register, the linear feedback shift register, the output register and the output latch circuit by inputting only a read / write signal that is a control signal of a general memory from the external processor. Generator, Connected between the linear feedback shift register and the output register, and outputs any one of keystream data which is a nonlinear defect output of the linear feedback shift register and data output from a plurality of shift registers according to an output signal of the control signal generator An internal control apparatus of a cryptographic algorithm chip capable of generating a plurality of cryptographic keystreams, characterized in that it comprises a keystream / register selection circuit.

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