JPH0677474A - Method and apparatus for manufacturing semiconductor device - Google Patents

Abstract

PURPOSE:To prevent an outward diffusion in a heat treatment, to prevent a change in the threshold voltage of the title device and to prevent a drop in the current driving ability of the title device. CONSTITUTION:In a MOS transistor having an LDD structure, well regions 102, 103 are formed on the surface of a P-type silicon substrate 101, a gate oxide film 105 is formed on the substrate 101 and N<+> type polycrystalline silicon films 106, 107 to be used as gate electrodes are formed sequentially. The polycrystalline silicon films 106, 107 are doped with phosphorus atoms at about 3X10<20>/cm<3>. After that, LDD regions 110 which are to be used as source/drain regions 114 and which have been formed by implanting phosphorus are set to a state that the surface of the silicon substrate 101 is exposed. In succession, sidewalls are formed on the gate electrodes. In order to strengthen the close contact property of a sidewall material and to activate implanted phosphorus ions 109, an annealing operation is performed and an oxide film is formed. At the initial stage of a heat treatment, nitrogen gas which contains 1 to 5vol.% oxygen is used.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to semiconductor devices, especially M
The present invention relates to a semiconductor device manufacturing method and a semiconductor manufacturing apparatus in an oxide film forming method including a gate oxide film in an OS device.

[0002]

2. Description of the Related Art A semiconductor device, especially a MOS device, includes many oxide film forming steps including formation of a gate oxide film. In recent years, with the miniaturization and high integration of devices, the number of processes using multi-layered polycrystalline silicon films has increased. For example, in a 1 Mbit dynamic RAM,
The cell plate that constitutes the capacity of the cell is formed of a polycrystalline silicon film containing a high concentration of conductive impurities. After that, the gate electrodes of the select transistor and the peripheral transistor are formed of a polycrystalline silicon film containing a high concentration of conductive impurities. As described above, in recent LSI devices, the polycrystalline silicon film containing a high concentration of conductive impurities has become indispensable as a wiring material and an electrode material for MOS transistors. That is, such a polycrystalline silicon film is formed by using CVD. Therefore, the polycrystalline silicon film is formed on the front surface and the back surface of the semiconductor substrate. Since these polycrystalline silicon films contain a very high concentration of conductive impurities, the polycrystalline silicon film is regarded as a diffusion source of impurities in the semiconductor substrate on which the polycrystalline silicon film is formed. In particular, when the semiconductor substrate surface is exposed near the polycrystalline silicon layer containing these conductive impurities, after forming this polycrystalline silicon film, an oxide film is formed on the semiconductor substrate surface, annealing, etc. After this thermal process, impurities diffuse from the polycrystalline silicon film from the exposed surface of the semiconductor substrate into the inside of the substrate.

FIG. 15 shows a device cross section in a gate oxide film forming process of a DRAM transistor. In FIG. 15, 1 is a P-type silicon substrate, 2 is an isolation region, 3 is a cell plate made of N ⁺ -type polycrystalline silicon, 4 is a capacitive insulating film, 5 is an N ⁺ -type diffusion region, 6 is a P-type diffusion region, 7 is outward diffusion of phosphorus from N ⁺ type polycrystalline silicon, 8 is a gate oxide film, 9 is an N type diffusion region, and 10 is N ⁺
Type polycrystalline silicon film.

Gate Oxide Film Forming Process In FIGS. 15B and 15C, the cell plate 3 is formed of a polycrystalline silicon film containing a high concentration of conductive impurities. After forming this polycrystalline silicon film, the initial stage of formation of the gate oxide film 8, that is, introduction of the silicon substrate, temperature ramping,
When a process such as annealing is performed, phosphorus is diffused outward from the polycrystalline silicon film and is introduced into a transistor region where the substrate surface is exposed and adjacent to the phosphorus, and is thermally diffused. MO in general
The threshold voltage of the S-transistor changes sensitively to changes in the impurity concentration on the substrate surface immediately below the gate electrode. Therefore, the threshold voltage fluctuates significantly. That is, FIG.
In the case of the N-channel transistor of, the phosphorus, which is an N-type impurity, self-diffuses from the cell plate 3 and the adjacent MOS
The conductivity type of the channel region of the transistor is N type. Therefore, the threshold voltage of the MOS transistor shifts to a large negative value, and the MOS transistor always becomes conductive.

On the other hand, FIG. 16 shows a sectional view of a MOS transistor having an LDD structure. In FIG. 16, 21 is a P-type silicon substrate, 22 is a P-type well region,
23 is an N type well region, 24 is an isolation region, 25 is a gate oxide film, 26 is a P type channel gate N ⁺ type polycrystalline silicon film, 27 is an N channel gate N ⁺ type polycrystalline silicon film, 28 is a photoresist, 29 is LDD phosphorus injection, 3
0 is a phosphorus-implanted LDD region, 31 is an N-type diffusion region by self diffusion, 32 is outward diffusion of phosphorus from the gate electrode, 33
Is a channel region, 34 is an N ⁺ type source / drain region,
Reference numeral 35 is a P-type source / drain region.

The gate of the transistor is usually formed of a polycrystalline silicon film 27 containing a high concentration of conductive impurities.
After forming the gate electrode, a low concentration impurity is implanted into the source / drain regions by ion implantation to form an LDD (FIG. 16A). After this, heat treatment is usually performed to activate the ion-implanted impurities. At this time, impurities are diffused from the gate of the polycrystalline silicon film 27 to the LDD regions of the source / drain (FIG. 16).
(B)). When the conductivity type forming the LDD region is the same as the impurity conductivity type of the polycrystalline silicon film 27, the impurity concentration of the LDD region of this transistor becomes high, and as a result, this transistor becomes a short channel. That is, in FIG.
In (c), the N-channel transistor is LDD due to phosphorus atoms self-diffusing from the N-type polycrystalline silicon film 27.
The N-type impurity concentration in the region is increased, and the lateral diffusion length is also increased. Therefore, the channel region 33 becomes narrow and becomes a short channel. On the other hand, when the conductivity type of the impurities of the polycrystalline silicon film gate is opposite to the conductivity type of the LDD region, the impurities of the LDD region are compensated by the impurities diffused from the polycrystalline silicon film, and the impurity concentration of the LDD region is lowered. As a result, the resistance of the LDD region increases, and in extreme cases, the transistor becomes an offset channel type transistor. As a result, the drive capacity is reduced.

In FIG. 16B, phosphorus having the opposite conductivity to the P-type source / drain is self-diffused in the source / drain region of the P-channel transistor, so that the P-type impurity and the N-type impurity are compensated. In FIG. 16C, high resistance N-type diffusion regions 11 are formed in the source / drain regions of the P-channel transistor. In this case, it becomes an offset channel transistor, the threshold voltage is largely shifted in the positive direction, and the driving capability of the P channel transistor is significantly reduced.

FIG. 17 is a device sectional view in the case of considering a MOS transistor having a DDD (double diffused drain) structure.

In FIG. 17, 41 is a P-type silicon substrate, 42 is a P-type well region, 43 is an N-type well region, 4
4 is an isolation region, 45 is a gate oxide film, 46 is a P channel gate N ⁺ type polycrystalline silicon film, 47 is an N channel gate N ⁺ type polycrystalline silicon film, 48 is a photoresist, 4
9 is DDD phosphorus implantation, 50 is phosphorus implantation DDD region, 51
Is an N-type diffusion region by self-diffusion, 52 is an outward diffusion of phosphorus from the gate electrode, 53 is a channel region, 54 is an N ⁺ -type source / drain region, and 55 is a P-type source / drain region.

Also in the DDD structure, as in the LDD structure, low concentration impurities in the DDD region are ion-implanted (FIG. 17A). After that, in the initial stage of the heat treatment for forming the DDD region, the self-diffusion from the polycrystalline silicon film 47 containing a high concentration of the impurity, which is the gate electrode, causes D
Impurities are diffused into the DD region. Therefore, when the impurities in the DDD region are the same conductivity type as the polycrystalline silicon film gate, the short channel state is established. In the opposite case, it causes an offset channel condition (see FIG. 17).
(C)). In addition to this, when a polycrystalline silicon film containing a high concentration of conductive impurities is present on the back surface of the silicon substrate, the back surface of the silicon substrate and the front surface of the silicon substrate are placed to face each other in an oxidation furnace. Impurities may be diffused on the surface of the, thus causing the above-mentioned problems. These phenomena are phenomena in which a polycrystalline silicon film containing a high concentration of conductive impurities serves as a diffusion source and diffuses to the exposed surface of the surface of the semiconductor substrate that is close to the diffusion source, and is also called autodoping. There is. The degree of this autodoping largely depends on the heat treatment temperature in the heat treatment furnace, the time, the atmosphere, the pitch of the silicon substrate, the structure of the silicon substrate boat, the gas flow in the furnace and the structure of the electric furnace. The narrower the silicon substrate pitch is and the more closed the boat is, the more remarkable the autodoping becomes. On the other hand, in recent years, a vertical electric furnace has been attracting attention and is being introduced in place of the horizontal furnace. Autodoping is more pronounced when using a vertical furnace.

FIG. 18 shows a conventional example of a heat treatment apparatus which normally performs these annealing and oxidation. Here, a vertical diffusion furnace is shown. In the figure, 60 is a process tube, 61
Is an exhaust port, 62 is a silicon substrate, 63 is a boat, 64 is a heater, 65 is a cap, 66 is a seal, 67 is a pedestal, 68 is a gas inlet, and 69 is a process gas flow. In the conventional example, the process gas is introduced from the upper part of the process tube 60, flows through the process tube 60, and is then discharged from the exhaust port 61 at the lower part of the tube. At this time, the process gas flows from the upper part of the process tube 60 to the lower part thereof. For this reason, a laminar flow is formed around the silicon substrate 62, which makes it difficult for these process gases to flow toward the central portion of the silicon substrate 62. Since the conductive impurity gas released outward from the polycrystalline silicon film containing impurities at a high concentration formed on the front surface or the back surface of the silicon substrate in the central portion of the silicon substrate does not flow between the silicon substrates. Retain between silicon substrates. As a result, the silicon exposed portion of the silicon substrate is auto-doped. Furthermore, in an impurity diffusion furnace that uses a process gas to uniformly form an impurity region on the surface of a silicon substrate, it is difficult for the process gas to flow between silicon substrates, particularly toward the center of the silicon substrate. In this case, it is considered that the supply of the process gas to the central portion of the silicon substrate 62 is controlled by diffusion. When the impurity diffusion device having such a structure is used, the impurity concentration in the surface of the silicon substrate 62 is lower in the central portion of the silicon substrate 62 than in the periphery. Further, since the concentration of the process gas becomes lower toward the lower part of the process tube 60, a large difference occurs in the impurity concentration between the silicon substrate 62 above the process tube 60 and the silicon substrate 62 below the process tube 60. When diffusion is performed in the conventional impurity diffusion furnace, the impurity concentration in the central portion of the silicon substrate 62 becomes lower than the target value within the surface of the silicon substrate 62. As a result, the specific resistance becomes high (FIG. 19). On the other hand, between the silicon substrates 62, the impurity concentration of the silicon substrate 62 above the process tube 3, the impurity concentration of the silicon substrate 62 in the center of the process tube 60, and the process tube 6
The impurity concentration of the lower silicon substrate 62 is different. As a result, the specific resistance of the silicon substrate 62 is different. The difference in the specific resistance in the longitudinal direction of the process tube 60 changes depending on the gas flow rate and the exhaust speed. In the conventional diffusion furnace, a temperature gradient is provided in the longitudinal direction of the process tube 60 in order to compensate for such non-uniformity of the resistivity of the silicon substrate 62 in the longitudinal direction of the process tube 60. Also, the silicon substrate 6
For the uniformity in two planes, a method of rotating the boat 63 on which the silicon substrate 62 is loaded to improve the uniformity is conceivable. The specific resistance of the part is not improved. In order to improve this, it may be considered to use an injector 70 as shown in FIG. 20 in the longitudinal direction of the process tube 60. The injector 70 shown in FIG. 20 has a silicon substrate 62 along the longitudinal direction of the injector 70.
Holes having a diameter of about 1 mm are provided at intervals of an integral multiple of the pitch, and the gas is ejected in the diameter direction of the silicon substrate 62 from the plurality of holes. However, in the injector 70 having this structure, the velocity of the gas ejected from the hole near the gas inlet port 68 and the velocity of the gas ejected from the gas outlet port 71 at the tip of the injector 70 are greatly different. The gas ejection speed from the hole near the gas introduction port 68 of the injector 70 is higher than that of the tip of the injector 70. Therefore, the specific resistance at the top and bottom of the process tube 60 is
It's very different. Further, regarding the in-plane uniformity, when the holes are installed toward the silicon substrate 62, the gas flow velocity is high and the temperature of the surface of the silicon substrate 62 decreases in the portion close to the holes in the surface of the silicon substrate 62. For this reason, the specific resistance becomes high, and an appropriate value can be obtained in the part farthest from the hole. Further, the specific resistance value is high in the central portion of the silicon substrate 62. The specific resistance distribution in the plane of the silicon substrate 62 at this time is as shown in FIG. On the other hand, when this hole is directed toward the tube wall of the process tube 60 in the direction opposite to the silicon substrate 62, the gas collides with the tube wall, is decelerated, and the reflected gas flow reaches the silicon substrate 62. As a result, an appropriate value can be obtained for the specific resistance of the portion near the injector 70. However, since the gas flow speed is not sufficient in the portion away from the injector 70 from the central portion of the silicon substrate 62, the gas does not spread and the specific resistance increases. The resistivity distribution in the plane of the silicon substrate 60 at this time is shown in FIG. When such an injector 70 is used, the silicon substrate rotating mechanism is very effective. Due to the silicon substrate rotating mechanism, the specific resistance is substantially uniform around the silicon substrate 62, but remains high at the center of the silicon substrate 62. FIG. 22 shows the specific resistance distribution in the plane of the silicon substrate 62 when the injector 70 employs the rotation of the silicon substrate. However, as described above, when the silicon substrate is rotated, it is necessary to install the rotating mechanism in a high temperature and corrosive gas atmosphere, which makes it difficult to ensure the reliability of the rotating mechanism. In addition, the device itself is complicated and expensive.

These devices may be used for the purpose of impurity diffusion, or may be used for the purpose of annealing and oxidation. When used for oxidation, water vapor generated by burning hydrogen gas and oxygen gas at a temperature of 760 ° C. or higher is used as an oxidant. Such an oxidation method is known as a pyrogenic oxidation method and is used for forming a gate oxide film and an oxide film for separation. This method is excellent in terms of purity and controllability of water vapor content.
Pyrogenic oxidation is generally performed by ejecting a mixed gas of oxygen and hydrogen from the tip of an injector into a process tube inside a process tube of an oxidation furnace and burning the mixture gas in a high temperature furnace to generate steam. At this time, from the explosion limit of hydrogen, the oxygen flow rate is set to 180% or less with respect to the hydrogen flow rate in consideration of safety. Further, the temperature at the tip of the injector at this time needs to be 760 ° C. or higher. At this time, the ratio of water vapor to the entire oxidizing atmosphere can be determined by adjusting the oxygen flow rate with respect to hydrogen. In steam oxidation, the growth rate of an oxide film is determined by the partial pressure of steam in the atmosphere. That is, in the case where the film thickness such as the gate oxide film is thin and the film thickness controllability is required, the partial pressure of water vapor in the oxidizing atmosphere may be lowered. That is, steam is generated by combustion of hydrogen and oxygen in an oxygen-rich atmosphere.

These pyrogenic oxidations have traditionally been by burning in process tubes. However, when hydrogen and oxygen are burnt in the process tube, the temperature of the process tube becomes non-uniform due to the ejection of high-temperature combustion gas, which causes problems such as non-uniform film thickness. For this reason, an external combustion method is often used in which a combustion chamber is provided outside the process tube and combustion is performed by a dedicated combustion heater. FIG. 23 is a conceptual view of an external combustion type oxide film forming apparatus having a conventional structure.
81 is a process tube, 82 is a silicon substrate, 83 is a boat, 86 is an external combustion chamber, 87 is an external combustion heater, 88 is an injector, 89 is an oxygen port, 9
0 is a hydrogen port and 91 is a hydro-oxygen flame. Oxygen port 8
9 and the hydrogen and oxygen gases introduced from the hydrogen port 90 are mixed and heated in the injector 88 by the external combustion heater 87. Hydrogen and oxygen gas heated to 760 ° C. or higher are ignited and discharged from the tip of the injector 88 into the combustion chamber 86 as a hydro-oxygen flame 91, and the generated water vapor is sent into the process tube 81.

[0014]

In the conventional method of manufacturing a semiconductor device described above, the autodoping is performed by the M method as described above.
Large change in threshold voltage of OS transistor, MOS
This causes various fatal problems such as shortening the channel of the transistor and offset gate, increasing the resistance of the contact diffusion region and increasing the junction depth. However, in recent years, semiconductor devices have become more highly integrated, and multilayer polycrystalline silicon films are increasingly used as wiring and gate electrodes. Therefore, problems caused by such autodoping tend to increase. Above all,
Recently, a vertical electric furnace tends to be introduced in place of the conventional horizontal electric furnace because the oxide film thickness is good and the automation is easy. According to the research conducted by the inventors, the vertical electric furnace has a structure between the silicon substrate and the silicon substrate.
In particular, since gas does not reach the central portion sufficiently, autodoping is more likely to occur than in a horizontal electric furnace. If a polycrystalline silicon film containing conductive impurities is present on the back surface of the silicon substrate, the polycrystalline silicon film on these back surfaces is selectively removed to prevent autodoping during subsequent heat treatment. Auto-doping from a polycrystalline silicon film existing as a pattern still remains a problem.

Further, in the above-mentioned conventional heat treatment apparatus, a gas containing impurities is supplied to the surface of the silicon substrate 62 with good uniformity without using the silicon substrate rotating mechanism, and further, in the longitudinal direction of the process tube 60. In addition, it is necessary to have a structure that can uniformly supply a gas containing impurities.

In order to make the gas ejection velocity from the gas ejection port 71 arranged in the longitudinal direction of the injector 70 uniform, the diameter of the gas ejection port 71 is changed from the gas inlet port 68 of the injector 70 toward the tip. There is a method of sequentially increasing the gas ejection speed from the ejection port 71 so as to be constant, and a method of reducing the interval between the gas ejection ports 71. However, it is difficult for these methods to calculate the diameter of the gas ejection port 71 that gives a constant velocity, and it is difficult to process the diameter. Further, there is a problem that the balance of each gas ejection port 71 is easily lost due to the change in diameter of the gas ejection port 71 with time. Further, there is a method of using a plurality of injectors 70 in order to improve the uniformity within the surface of the silicon substrate 62. However, two gas systems are required and it is necessary to balance the two injectors 70. is there. Therefore, there is a problem that the spatial margin between the process tube 60 and the silicon substrate 62 becomes small.

Further, in the above-mentioned conventional pyrogenic oxidation method, in the pyrogenic oxidation in an oxygen-rich atmosphere, the combustion of hydrogen and oxygen at the tip of the injector 88 is oxygen-rich, so that a normal combustion state cannot be obtained. In a normal combustion state, the flow rate ratio of oxygen to hydrogen is 18
It is around 0%, and the temperature of the hydro-oxygen flame 91 at this time is combustion at a relatively low temperature. On the other hand, in the case of oxygen rich,
Combustion becomes explosive due to excess oxygen.
The temperature becomes very high. Further, in the structure of the conventional injector 88, hydrogen and oxygen gas are mixed and ejected from the same injector 88. Injector 8
8 Injector 88 because the diameter of the tip is normally narrowed
The ejection speed of the mixed gas of hydrogen and oxygen ejected from the tip becomes very high.

[0018]

In order to solve the above-mentioned problems, a method of manufacturing a semiconductor device of the present invention comprises forming a high-concentration impurity diffusion layer or a conductive film containing a high-concentration impurity on a semiconductor substrate, Then, in forming an oxide film on the surface of the semiconductor substrate other than the region covered with the impurity diffusion layer or the conductive film, a first step of introducing the semiconductor substrate into an oxidation device, and a predetermined temperature after the introduction. And a third step of annealing at the predetermined temperature. The first, second, and third steps are processed in a mixed atmosphere of oxygen and nitrogen.

Further, a high-concentration impurity diffusion layer or a conductive film containing high-concentration impurities is formed on the semiconductor substrate, and then the surface of the semiconductor substrate other than the region covered with the impurity diffusion layer or the conductive film is oxidized. When forming a film,
The first step comprises a first step of introducing the semiconductor substrate into an oxidizing device, a second step of bringing the semiconductor substrate to a predetermined temperature after the introduction, and a third step of annealing at the predetermined temperature. In an oxygen atmosphere, and the second and third steps are performed in a non-oxidizing atmosphere.

Further, a cell plate is formed on the semiconductor substrate via a capacitive insulating film, and the cell plate is formed of a conductive film containing a high concentration of impurities, and then the semiconductor substrate is introduced into an oxidation device. The first step, the second step of bringing the temperature to a predetermined temperature after the introduction, and the third step of annealing at the predetermined temperature are performed. The first, second and third steps are mixed with oxygen and nitrogen. Processing is performed in an atmosphere to form a gate oxide film.

In addition, a step of forming a conductive film containing impurities on the semiconductor substrate, a step of implanting a first ion with the conductive film as a mask, and a step of oxidizing the semiconductor substrate after the first ion implantation are performed. It comprises a first step of introducing, a second step of bringing the material to a predetermined temperature after the introduction, and a third step of annealing at the predetermined temperature. And a step of forming an insulating film on the sidewall of the conductive film, and a second ion implantation using the conductive film and the sidewall as a mask.

Further, a step of forming a conductive film containing impurities on the semiconductor substrate, a step of implanting first ions with the conductive film as a mask, and a step of oxidizing the semiconductor substrate after the first ion implantation are performed in an oxidizing device. It comprises a first step of introducing, a second step of bringing the material to a predetermined temperature after the introduction, and a third step of annealing at the predetermined temperature. And a step of forming an insulating film on the sidewall of the conductive film, and a second ion implantation using the conductive film and the sidewall as a mask.

Further, a conductive film containing impurities is formed on a semiconductor substrate, and the conductive film is used as a mask for ion implantation to dope the first impurity having a large diffusion coefficient to a low concentration and to make the first impurity having a small diffusion coefficient. The second step of doping the semiconductor substrate into the oxidizer after the impurity is heavily doped, the second step of bringing the semiconductor substrate into a predetermined temperature after the introduction, and the third step of annealing at the predetermined temperature. The first, second, and third steps are performed in a mixed atmosphere of oxygen and nitrogen.

In order to solve the above problems, the semiconductor manufacturing apparatus of the present invention comprises a process tube, a substrate boat having a semiconductor substrate set in the process tube, and an injector for introducing a process gas into the process tube. The process gas introduced from the injector is supplied in parallel with the plane of the semiconductor substrate.

In order to solve the above problems, the semiconductor manufacturing apparatus of the present invention comprises a process tube, a boat installed in the process tube, a gas inlet for introducing gas into the process tube, An exhaust port for discharging gas from the inside of the process tube, and a gas introduced from the gas inlet port is introduced into the process tube through an injector, and the injector is the length of the boat in the longitudinal direction of the process tube. With a length exceeding.

In order to solve the above-mentioned problems, the semiconductor device manufacturing method of the present invention comprises a polycrystalline silicon film, a silicon dioxide film, a silicon nitride film, or a combination of these films on a silicon substrate. A step of performing thermal oxidation on the composite film by burning hydrogen gas and oxygen gas in a water vapor atmosphere, and continuously after the thermal oxidation, further on the silicon substrate or on the film on the silicon substrate by chemical vapor deposition. In the step of forming a crystalline silicon film, a silicon dioxide film, a silicon nitride film and other vapor phase growth films, and in the thermal oxidation, the oxygen gas flow rate is 0.56 times the hydrogen gas flow rate with respect to the hydrogen gas flow rate and burned. Let
Oxygen is further mixed with the water vapor generated by the combustion to oxidize it.

In order to solve the above problems, the semiconductor manufacturing apparatus of the present invention has a combustion chamber for hydrogen and oxygen gas, an external combustion heater and an injector outside the process tube, and is generated in the combustion chamber. Means for automatically sending the hydrogen gas flow rate and the oxygen gas flow rate to be used for the combustion, by feeding the generated water vapor into the process tube, further introducing oxygen from another inlet provided in the process tube, and It has a calculation means for calculating the amount of oxygen to be mixed with the steam generated by the combustion.

[0028]

According to the structure of the present invention, by performing the heat treatment in accordance with the heat treatment sequence, the oxide film grown on the surface of the semiconductor substrate by the subsequent oxidation step is not adversely affected. By growing a thin oxide film that prevents impurity diffusion on the surface of the semiconductor substrate, self-diffusion from the high concentration impurity layer can be prevented. Further, by using a heat treatment apparatus having a gas injector having a structure in which a process gas flows between the semiconductor substrates in the diameter direction of the semiconductor substrate, impurities diffused outward from the high-concentration impurity layers on the front and back surfaces of the semiconductor substrate are prevented. , Cannot stay between semiconductor substrates and is carried with the process gas. Therefore, self-diffusion can be prevented. Of course, these methods may be used alone or in combination, and when used in combination, certain effects can be expected.

[0029]

EXAMPLE A case where the present invention is applied to heat treatment of a MOS transistor having an LDD structure using a vertical diffusion furnace will be described below.

When forming a MOS transistor having an LDD structure, the process is different between the N-channel transistor and the P-channel transistor as shown in FIG. First, a P-type well region 102 and an N-type well region 103 are formed on the surface of the P-type silicon substrate 101.
An isolation region 104 is provided between the well regions 102 and 103 of both.
Are formed. An N channel transistor is formed in the P type well region 102, and a P channel transistor is formed in the N type well region 103. Silicon substrate 1
01, a gate oxide film 105 is formed, and an N ⁺ type polycrystalline silicon film 106 to be a gate electrode of a P channel transistor is formed thereon. On the other side, an N ⁺ type polycrystalline silicon film 107 which will be the gate electrode of the N channel transistor is formed. These polycrystalline silicon films 106 and 107 are doped with phosphorus atoms at about 3 × 10 ²⁰ / cm ³ . Next, the gate electrode of the transistor is formed by the known photo-etching technique and dry etching technique. After that, the LDD region 110 formed by the phosphorus implantation which becomes the source / drain regions 114 is in a state where the surface of the silicon substrate 101 is exposed. This is because the gate oxide film 105 has become thinner, and even if an oxide film may remain during the dry etching when forming the gate electrode, this oxide film is damaged by etching, and the subsequent cleaning process is performed. Will be easily removed.

Next, in order to form the LDD region 110 of the N-channel transistor, the region where the P-channel transistor is formed is masked with the photoresist 108. After that, phosphorus ions 109 are implanted on the entire surface of the substrate. Thereby, the LDD region 110 is formed. At this time, phosphorus atoms are ion-implanted into the N-channel transistor by 2 × 10 ¹² / cm ² (FIG. 1A).

Subsequently, sidewalls are formed on the gate electrode. As the sidewall material, a high temperature oxide film (HTO) formed by CVD or a TEOS oxide film formed by CVD is used. Annealing and oxide film formation are performed for the purpose of enhancing the adhesion of the sidewall material and activating the phosphorus ions 109 implanted in the LDD region 110 in the previous step. By this heat treatment, phosphorus atoms diffuse outward from the gate electrodes of the polycrystalline silicon films 106 and 107, and self-diffuse into the LDD region 110. As a result, the conductivity type of the LDD region 110 becomes N type. LD
When the D region 110 becomes the N type, the phosphorus ion implantation amount of the LDD region 110 of the N channel transistor increases. As a result, the resistance of the LDD region 110 decreases,
Phosphorus ions introduced by the out-diffusion diffuse and the N-type region reaches below the gate electrode. When the N-type region reaches below the gate electrode, the channel of this N-channel transistor becomes a short channel.

On the other hand, in the P-channel transistor, the N-type phosphorus atom is compensated with the P-type impurity introduced in the later step to form the source / drain region 115. Therefore, a PN junction is formed at a position between the high resistance layer or the source / drain region 114 and immediately below the sidewall region. As a result, the P-type diffusion layer of the source / drain region 114 does not substantially reach below the gate electrode, and it becomes an offset gate transistor.

In order to prevent this, the initial step of the heat treatment shown in FIG. 1B, that is, the step of introducing the silicon substrate 101 into the furnace, the step of stabilizing the temperature, and the step of performing temperature ramping and annealing are performed. It is necessary to devise it. The heat treatment sequence in these steps is shown in FIG.

In FIG. 2, in the initial stage of heat treatment, nitrogen gas containing 1 to 5% by volume of oxygen is used for treatment. Therefore, in the initial stage of the heat treatment, a thin oxide film 117 is formed on the gate electrode surface of the polycrystalline silicon films 106 and 107 containing the high-concentration impurity which is the diffusion source. This oxide film 1
17 is a barrier against the outward diffusion of high-concentration impurities,
Suppress the outward diffusion of impurities. A thin oxide film is also formed on the surface of one of the LDD regions 110. This oxide film 117 can prevent impurities diffused outwardly from being diffused into the LDD region 110. In the initial stage of the heat treatment, it is performed in an atmosphere with low reactivity so as not to oxidize the surface of silicon. In particular, when the ions introduced into the substrate are activated by the heat treatment, oxygen existing causes OSF (Oxygen Induced Stacking Fault). Therefore, it is necessary to avoid excessively oxidizing the substrate surface. In this embodiment, it is necessary to form a thin oxide film to prevent the diffusion of impurities on the silicon surface. Therefore, when the heat treatment temperature is low, for example, about 700 ° C., diffusion of impurities is unlikely to occur, but at the same time, an oxide film on the surface is also difficult to grow. On the other hand, at a temperature of about 1000 ° C., diffusion of impurities is likely to occur, but at the same time, an oxide film is likely to grow. Thus, the amount of diffusion of impurities and the thickness of the oxide film are in a trade-off relationship. The thickness of the oxide film must be 5 nm as a minimum. Therefore, as in this embodiment, 9
When growing at a temperature of 00 ° C, the oxygen partial pressure is 1 to 5
It is set to about volume%. When the oxygen partial pressure is 1% by volume or less, the oxidizing power is weak, so that sufficient diffusion of impurities cannot be prevented.
On the other hand, if it is 5% by volume or more, the oxidizing power is strong, but an excessively large oxide film is formed, and crystal defects such as OSF occur. Here, when the growth temperature is set to about 800 ° C., the oxygen partial pressure can be used at 1% by volume to 10% by volume for the same reason.

Under the annealing / oxidation conditions, first, the silicon substrate 101 is put into the furnace at a temperature of 900.degree. The charging time is about 30 minutes. At this time, the flow rate of nitrogen gas is 14.55 liters per minute and oxygen is 0.45 liters per minute in the furnace. When the silicon substrate 101 is put into the furnace,
In order to stabilize the temperature inside the furnace, the silicon substrate 101 is left standing for 20 minutes for temperature stabilization with the position thereof fixed. By this temperature stabilization, the inside of the furnace is uniformly maintained at 900 ° C. Next, while keeping the flow rate of nitrogen (14.55 liters per minute) unchanged, oxygen is introduced into the furnace at a flow rate of 15 liters per minute and hydrogen at a flow rate of 7.5 liters per minute to perform oxidation. The oxidation time is 16 minutes. After that, the supply of oxygen and hydrogen is shut off, and only the nitrogen is flown at the same flow rate, and the silicon substrate 101 is taken out from the furnace. The take-out time of the silicon substrate 101 is 30 minutes. However, although nitrogen is simultaneously flown in the step of flowing oxygen and hydrogen, the flow of nitrogen may be stopped and only oxygen and hydrogen may be flowed. The temperature is set to 900 ° C. here because the activation after the ion implantation and the subsequent film thickness of the oxide film for protecting the surface of the silicon substrate are set to about 30 nm, the redistribution of the impurities and the oxidation are performed. It is used at 900 ° C. from the viewpoint of film thickness controllability. Further, the charging time is set to about 30 minutes so that stress due to thermal change of the silicon substrate is not applied as much as possible and crystal defects are not generated. The flow rate of nitrogen gas is set to 14.55 liters per minute so that the inside of the process tube can be purged in a short time.

At this time, the grown oxide film is the LDD region 11
0 is about 3 to 5 nm, and the polycrystalline silicon film 106,
The LDD region 1 on the surface of 107 depends on the impurity concentration.
It becomes 2 to 3 times the oxide film thickness in 10. Using the concentration of impurities contained in the polycrystalline silicon film with the above value,
An oxide film 1 having a thickness of 8 to 15 nm is formed on the polycrystalline silicon film.
17 grows. Since the growth of the oxide film 117 occurs at the same time as the phosphorus atoms contained in the gate electrode diffuse outward, it is possible to prevent the diffusion of phosphorus into the LDD region 110 due to autodoping. Therefore, there is no adverse effect on the film thickness of the oxide film formed in the subsequent oxidation step or its film quality. In this example, the atmosphere at the time of introduction was a nitrogen atmosphere containing 3% by volume of oxygen.

Further, even when a polycrystalline silicon film containing impurities at a high concentration is formed on the back surface of the P-type silicon substrate 101 or the back surface of the silicon substrate 101 is exposed, it is adjacent to these heat treatments. This embodiment can also be used when the impurities of the matching silicon substrate 101 adhere to and diffuse into the polycrystalline silicon film and the back surface.

Following these heat treatments, the LDD region 110
An oxide film forming the side wall 116 of is deposited using CVD. Then, the LDD sidewall 116 is formed through a photolithography and etching process. Thereafter, with the LDD sidewall 116 and the gate electrode as a mask, arsenic is ion-implanted into each N-channel transistor and BF ₂ is ion-implanted into each of the source / drain regions 114, and a MOS transistor having an LDD structure is completed (( FIG. 1 (c)).

That is, using the LDD sidewall 116 and the gate electrode as a mask, arsenic is used for the source / drain region 114 of the N channel transistor and BF2 is used for forming the source / drain region 115 of the P channel transistor. At this time, when arsenic is injected into the N-channel transistor, the P-channel transistor is masked with the resist, and in the opposite case, the N-channel transistor is masked with the resist.

At this time, there is no phosphorus atom diffusion region due to autodoping in the LDD regions 110 of the N-channel and P-channel transistors. Therefore, the short channel effect does not occur in the N channel transistor. Further, in the P-channel transistor, the phosphorus atom does not cause compensation with BF ₂ and therefore does not serve as an offset channel transistor.

FIG. 3 shows an embodiment of a MOS transistor having a DDD structure.

In FIG. 3, a P-type well region 122 and an N-type well region 123 are formed on a P-type silicon substrate 121. An isolation region 124 that electrically isolates the P-type well region 122 and the N-type well region 123 is formed in the boundary region between the two. A gate electrode is formed on the silicon substrate 121 in each of the well regions 122 and 123 with a gate oxide film 125 interposed therebetween. The gate electrode is the N-type well region 123.
Is a P channel transistor gate N ⁺ type polycrystalline silicon film 126, and the other is an N channel transistor gate N ^+.
It is formed of the type polycrystalline silicon film 127.

Next, the N-type well region 123 is masked with the photoresist 128. Then, phosphorus 12
Make 9 injections. By this phosphorus implantation, DDD region 1
Form 30. Next, the silicon substrate 121 is subjected to predetermined annealing and oxidation to form an oxide film 131.
At this time, the region directly under the gate electrode sandwiched between the DDD regions 130 becomes the channel region 133. Further, an N ⁺ type source / drain region 134 is formed in the P well region 122 and a P ⁺ type source / drain region 135 is formed in the N well region 123 by ion implantation using a photoresist as a mask.

Here, as in the case of the LDD structure, the DD
In the initial stage of annealing and oxidation, which is a step after implanting the low concentration phosphorus ions 129 into the D region 130,
The high-concentration impurities contained in the gate electrode diffuse out and D
It is diffused to the DD region 130. In order to prevent this, in the initial stage of these heat treatments, the heat treatment is performed according to the heat treatment sequence shown in FIG. First set the temperature to 800
Oxygen gas is caused to flow at a rate of 15 liters / minute while maintaining the temperature at 0 ° C. The silicon substrate 121 is put into this oxygen atmosphere for 30 minutes. When the charging of the silicon substrate 121 is completed, the silicon substrate 121 is left in that state for 20 minutes to stabilize the temperature in the furnace. Next, after stabilizing the temperature, the flow of oxygen gas is stopped and nitrogen gas is allowed to flow into the 15 liter furnace per minute.
At the same time, the temperature is raised at a rate of 4 ° C. for 1 minute, and the temperature is raised to 900 ° C. 25 minutes later. Then, annealing is performed for 30 minutes in a nitrogen atmosphere. As described above, the polycrystalline silicon film 12 containing high-concentration impurities is formed in the initial stage of the heat treatment.
Thin oxide film 12 on 6,127 surface and DDD area surface
8 can be formed to suppress the outward diffusion of impurities and the diffusion of the outwardly diffused impurities into the DDD region 130 (FIG. 3B).

Thereafter, the nitrogen gas is shut off, and 15 liters / minute of oxygen gas and 15 liters / minute of hydrogen gas are caused to flow into the furnace. This state is left for 16 minutes to oxidize the silicon substrate 121. What is important here is that the polycrystalline silicon films 126 and 12 that are diffusion sources are used at the earliest stage of the heat treatment.
7 and the surface of DDD region 130 are thin oxide films 1
28 is to be formed. In the embodiment shown here, the silicon substrate is charged at a low temperature of 800 ° C., so that it is less likely to diffuse outward. After the oxidation, the flow of oxygen gas and hydrogen gas is cut off, and nitrogen gas is caused to flow at 15 liters per minute. In this nitrogen atmosphere, the temperature is lowered at a rate of 4 ° C. per minute, and the temperature is raised to 800 ° C. after 25 minutes. In this state, 3
The silicon substrate 121 is taken out in 0 minutes.

The temperature at the time of charging is set to 800 ° C.
This is to reduce the diffusion of impurities phosphorus at the time of introduction and to reduce the amount of impurities diffused outward from the high-concentration impurity diffusion layer. The oxygen atmosphere at this time is 800 ° C., so even if the oxygen partial pressure is 100% by volume, the thickness of the oxide film grown in 20 minutes is 4.
This is because it becomes 5 nm, and it is possible to prevent impurities from diffusing with this film thickness. After that, the reason why nitrogen gas is caused to flow at the time of temperature rise is that it is not necessary to flow oxygen gas here because an oxide film that serves as a barrier for diffusion of impurities has already been formed in the previous step.

FIG. 5 shows a D having a two-layer polycrystalline silicon structure.
7 shows an example in a step of forming a gate oxide film of a RAM. First, a field oxide film to be the isolation region 142 is formed in a predetermined region of the P-type silicon substrate 141. Next, the P type diffusion region 146 is formed in the silicon substrate 141. Further, an N ⁺ type diffusion region 145 to be the source and drain of the MOS transistor is formed. Next, the capacitive insulating film 14 is formed on the P-type diffusion region 146 on the silicon substrate 141.
4 and an N ⁺ type polycrystalline silicon film cell plate 143 are formed (FIG. 5A). After that, a gate insulating film 148 is formed on the silicon substrate 141 forming the MOS transistor. Furthermore, a thin oxide film 1 is formed on the surface of the cell plate 143.
51 is formed. Here, the cell plate 143 is formed of a polycrystalline silicon film containing a high concentration of impurities.
Therefore, during the formation of the gate oxide film 148 of the MOS transistor that is the selection transistor, the impurities diffused out from the cell plate 143 self-diffuse into the silicon substrate 142 immediately below the gate insulating film at the initial stage of the process of forming the gate oxide film 148. To do. In order to prevent this, processing is performed by the heat treatment sequence shown in FIG. First, while maintaining the temperature at 900 ° C., oxygen gas is caused to flow at 0.45 liter / min so that the oxygen concentration becomes 14.55 liter / min and the oxygen concentration becomes 3% by volume. The silicon substrate 141 is placed in this atmosphere for 30 minutes. When the charging of the silicon substrate 141 is completed, the silicon substrate 141 is left in that state for 20 minutes to stabilize the temperature in the furnace. Next, after temperature stabilization, annealing is continuously performed for 30 minutes. Next, the flow of nitrogen gas is stopped, the flow rate of oxygen gas is set to 15 liters per minute, and further hydrogen gas is made to flow at 7.5 liters per minute to oxidize for 9 minutes. After this, the oxygen gas and the hydrogen gas are shut off, and instead, nitrogen gas is flowed at 14.55 l / min. At the same time, the temperature of the furnace is raised at a rate of 4 ° C./min for 25 minutes to change the temperature from 900 ° C. to 1000 ° C. In this state, annealing after oxidation is performed for 20 minutes. After this, in a nitrogen atmosphere, 4 ° C / min
The temperature is lowered at a rate of, and the temperature is brought to 900 ° C. in 25 minutes. Further, in this state, the silicon substrate 141 is taken out for 30 minutes. In this way, as shown in FIG. 5B, in the initial stage of the heat treatment, the thin oxide film 151 is formed in the gate region of the cell plate 143 and the select transistor, and the outward diffusion of impurities from the cell plate 143 and It is possible to prevent the impurity diffused outward from diffusing into the gate region. Also in this case, the predetermined gate oxide film 1 is formed by the heat treatment of this embodiment.
The film thickness of the oxide film 151 grown before forming 48 is about 5 nm. Gate oxide film 1 after gate oxidation (FIG. 5C)
It does not affect the film thickness and film quality of 48. As a matter of course, similar effects can be obtained even when the treatment in oxygen is performed by introducing at a low temperature, as shown in the DDD structure example.

After that, an N ⁺ type polycrystalline silicon film 150 which is a gate electrode is formed on the gate insulating film 148 (FIG. 5D).

The above is the embodiment by the improvement of the manufacturing method, and the embodiment in the case of using the manufacturing apparatus having the mechanism for solving these problems will be described below. In this embodiment, a case of using a vertical electric furnace which is generally prone to autodoping will be described. FIG. 7A shows an embodiment of the vertical electric furnace of the present invention.

In FIG. 7, the silicon substrate 160 is set on the substrate boat 165. The substrate boat 165 is installed in the vertical direction of the process tube 162 (vertical direction on the paper surface). The silicon substrates 160 are installed vertically to the substrate boat 165, that is, in the vertical direction of the substrate boat 165 at approximately equal intervals one by one in the left-right direction of the paper surface. A heater 163 is provided outside the process tube 162.
Further, the process gas 16 is placed inside the process tube 162.
An injector 161 supplying 4 is attached. In order to efficiently carry the impurities diffused outward between the silicon substrates 160 from between the silicon substrates 160,
A horizontally flowing gas flow between the silicon substrates 160 is required. In order to realize this horizontal gas flow, a gas introduction pipe of the injector 161 having a jet port of an integral multiple of the silicon substrate pitch is provided in the horizontal direction.

FIGS. 7B, 7C and 7D are detailed drawings of the gas injector 161 used in this embodiment. A quartz tube whose one side is closed is used as the injector 161, and a gas jet port 166 is formed linearly in the longitudinal direction of the injector 161.
Are evenly spaced. This space is the substrate boat 16
5, the silicon substrate 160 is arranged at a length twice as long as the space between the silicon substrates 160. FIG. 7C is a cross-sectional view taken along the longitudinal direction of the circular area A of FIG. 7B, and FIG.
FIG. 8 is a sectional view taken along the line segment BB ′ in FIG.

The injector 161 has a double pipe structure in which an inner pipe having an outer diameter of 6 mm and an inner diameter of 4 mm is installed in an outer pipe having an outer diameter of 10 mm and an inner diameter of 8 mm. Injector 16
The process gas 164 introduced from one end of No. 1 is once introduced into the inner pipe. The gas is discharged from the gas ejection port 167 into the gap between the inner pipe and the outer pipe while advancing through the inner pipe toward the tip of the injector 161. At this time, the injector 16
The flow velocity of the gas ejected from the gas ejection port 167 is different between the tip portion of 1 and the root portion. That is, the flow velocity at the tip is slower than the flow velocity at the root. However, once the process gas 164 is released into the gap between the inner pipe and the outer pipe, it serves as a buffer and the injector 161
The flow velocity distribution in the longitudinal direction of can be suppressed. The buffer prevents the flow velocity at the tip from becoming slower than the flow velocity at the root, and makes the flow velocity from the root equal at the tip. That is, by temporarily storing the gas discharged from the inner tube of the concentric tube by the buffer, the flow velocities of the tip portion and the root portion become substantially equal when the gas flows from the outer tube.

The gas outlet 166 provided on the outer tube is shown in FIG.
In the annular cross section shown in (d), the respective gas ejection ports 166 are formed so as to form an angle of 90 degrees with each other. In this embodiment, the silicon substrate 160 is the substrate boat 16
Since they are installed at intervals of 4.76 mm in No. 5, the pitch of the gas ejection ports 166 is 9.76 mm. Here, the total number of gas ejection ports 166 is 160. Furthermore, FIG.
As shown in (d), the gas ejection ports 167 having a diameter of 2 mm installed in the inner pipe are installed at positions having inner angles of 135 degrees with respect to the gas ejection ports 166 installed in the outer pipe.
However, the gas ejection ports 167 do not need to be installed at a finer interval than the gas ejection ports 166, and in this embodiment, they are installed every 5 pitches. The gas ejection port 166 allows gas to flow in the space between the silicon substrate 160 and the next substrate. For this purpose, it is preferable to provide the same number of gas injection ports as the distance between the substrates. However, since the gas ejected from the gas ejection port 166 spreads at the same time as the ejection,
In this embodiment, the substrates are arranged at a double interval. On the other hand, since the gas ejection port 167 of the inner tube may be ejected to the buffer, it is irrelevant to the distance between the substrates. However, if the distance between the substrates is made too small, the flow velocity of the gas ejected to the buffer at the tip portion and the root portion of the injector will be different. It is designed to ensure a certain flow velocity.

With the above structure, the process gas 164 once discharged into the gap between the inner pipe and the outer pipe is discharged into the process tube 162 from the gas ejection port 167 provided in the outer pipe. At this time, the flow velocity of the process gas 164 discharged from the gas ejection port 167 depends on the injector 161.
It is almost equal both at the tip and at the root. The process gas 164 emitted from the gas ejection port 166 is parallel to the front and back surfaces of the silicon substrate 160.
After flowing between 60 and reaching the other tube wall of the process tube 162, it is exhausted through the exhaust port.
At this time, the process gas 164 flowing parallel to the surface of the silicon substrate 160 diffuses outward from the back surface or the front surface of the silicon substrate 160, and the gas containing impurities released to the outside is carried from between the silicon substrates 160 by the flow rate. It is possible to prevent the process gas diffused from the silicon substrate 160 itself from being diffused again to the exposed silicon region of the surface of the silicon substrate 160. Here, the flow velocity of the gas in the longitudinal direction of the process tube having a diameter of 150 mm without such an injector is 0.7 cm / sec when oxygen or nitrogen is flown at 15 liters / min. When using an injector, 53 cm /
It is about 76 times faster than the second. As a result, the impurities diffusing outward are exhausted without reaching the substrate. That is, when an injector is used, the flow velocity at the center of the silicon substrate is about 0.3 cm / sec. Therefore, if a silicon substrate having a diameter of 6 inches is used, it takes about 50 seconds for the gas to pass through. At this time, the process gas 164
Must be evenly flowed between the silicon substrates 160. For this reason, the gas ejection ports 166 provided on the outer pipe are separated from each other by 13
It is installed with an angle of 5 degrees. Further, by rotating the silicon substrate 160, a more uniform gas flow can be secured.

Although the injector 161 has a straight pipe structure in this embodiment, it may actually have a folded structure for the purpose of residual heat of the process gas 164. Further, the same effect can be obtained whether the injector 161 is inserted from above or below the process tube 162.

When a semiconductor device having a high-concentration impurity layer or a polycrystalline silicon film containing a high-concentration impurity on part or all of the front surface and the back surface of a silicon substrate is subjected to heat treatment as in the present invention, it is removed from these impurity layers. It is possible to prevent the diffused impurities from being inadvertently diffused to the exposed portion of the surface of the silicon substrate. As a result,
In the MOS transistor having the LDD and DDD structures, it is possible to prevent the fluctuation of the threshold voltage and the fluctuation of the current driving force due to the short channel and the offset channel. In addition, in a semiconductor device having multi-layer polycrystalline silicon, it is possible to prevent autodoping in the gate oxide film forming step, and it is possible to prevent fluctuations in threshold voltage.

FIG. 8 shows a sectional structure of an impurity diffusion device which is a second vertical diffusion furnace having the structure shown in the present invention. The silicon substrate 170 is installed on the substrate boat 171. The substrate boat 171 is installed in the vertical direction of the process tube 173 (vertical direction on the paper surface). The silicon substrates 170 are installed vertically to the substrate boat 171, that is, in the vertical direction of the substrate boat 171, one by one in the left-right direction of the paper surface at approximately equal intervals. The substrate boat 171 is attached to a pedestal 179 formed on the cap 177. The substrate boat 171 loaded with the silicon substrate 170 is inserted and removed from the lower portion of the process tube 173 by an automatic machine. A heater 174 is provided outside the process tube 173.
Is provided. Further, an injector 176 for supplying a process gas 175 is attached inside the process tube 173. The process gas 175 introduced from the gas inlet 180 passes through the injector 176 and is introduced into the process tube 173. The introduced process gas 175 undergoes a predetermined treatment, and then the gas exhaust port 18
1 is exhausted to the outside. Also, the injector 176 is introduced outside the process tube 173 from a lower position, is guided to the upper part of the process tube 173, and is folded back at the upper part of the process tube 173 and is introduced into the inside of the process tube 173 to have a folded structure. There is. The process tube 173 is sealed by a cap 177 via a seal 178. In this way, the inside of the process tube 173 is operated under reduced pressure.

A gas ejection port 182 is provided at the folded back portion. By making the injector 176 have a folded structure, the process gas can be preheated in the process tube 173 and then introduced into the process tube 173. By this injector 176, the process gas 175 is spread over the entire length of the substrate boat 171 on which the silicon substrate 170 is loaded.

FIG. 9 shows the structure of an injector used in this impurity diffusion device. FIG. 10 is a longitudinal sectional view of the injector in the circular region C of FIG. FIG. 11 is an annular cross-sectional view taken along the line DD ′ of FIG. 9, 10 and 11 are configuration diagrams of the injector 176 shown in the present invention. This has the same structure as the injector of the first vertical diffusion furnace. That is, high-purity quartz was used as the constituent material of the injector 176. The injector 176 is a double pipe having a folded structure, and the process gas 175 introduced from the gas introduction port 180 is preheated up to the folding point, and passes from the folding point through the inner pipe of the double pipe to the inner pipe. The gas is ejected into the gap between the inner pipe and the outer pipe from the arranged gas ejection port 182. At this time, the velocity of the gas ejected from the gas ejection port 182 of the inner pipe is different between the tip portion of the injector 176 and the folded portion. However, once the gas is discharged into the gap between the inner tube and the outer tube, this difference in gas velocity is significantly reduced. Therefore, the gas ejection port 18 provided in the outer tube
In the case of jetting from No. 2, the difference in gas jetting speed between the tip end portion of the injector 176 and the folded portion is very small, and a uniform gas jetting speed can be realized over the entire length direction of the injector 176. As a result, it is possible to prevent out-diffusion of the device realized by the first vertical diffusion furnace, and it is possible to enhance the uniformity of the flow of the process gas 175 flowing between the silicon substrates 170. On the other hand, in the outer tube, two types of gas ejection ports 182 are arranged at an angle of 90 degrees. This gas ejection port 182 is arranged in the longitudinal direction of the injector 176 so that the substrate boat 1
The silicon substrates 170 arranged at 71 are arranged on a straight line at an interval that is an integral multiple of the interval. In this embodiment, the silicon substrate 170 is arranged at an interval of 5.84 mm,
The intervals of the gas ejection ports 182 of the outer tube were set every two pitches, that is, 11.68 mm. The diameter of the gas ejection port 182 was set to 1 mm. On the other hand, for the inner pipe, the gas ejection port 18
The intervals of 2 were 5 pitches, that is, every 29.20 mm, and the diameter of the gas ejection port 182 was 2 mm. Here, the diameter of the gas ejection port is determined by the gas ejection speed.

The injector 176 is the process tube 1
The wall surface of 73 is arranged at a distance of about 5 mm. Two
Two gas outlets 182 with an angle of 90 degrees to each other,
45 in the diameter direction of the process tube 173
It is arranged at an angle of ± 15 degrees and 135 degrees ± 15 degrees. That is, the angle 9 formed by the two gas ejection ports 182 is 9
The bisector of 0 degrees is 90 degrees to the diameter direction of the process tube 173 and parallel to the tangent to the wall surface of the process tube 173.

FIG. 12 shows how the resistivity of the polycrystalline silicon film is distributed depending on the arrangement of the gas ejection ports 182. Here, an example is shown in which diffusion is performed using a process gas obtained by bubbling phosphorus oxychloride with nitrogen gas as a diffusion source. This diffuses impurities from a process gas into a polycrystalline silicon film which is an oxide film formed on a silicon substrate. As the diffusion source, phosphorus oxychloride (purity 99.99999%) is used.
Keep the temperature at 0 ℃ and use nitrogen gas as carrier gas for gas flow rate 6
Run at 00 cc / min. As a result, 12
A process gas containing 0 mg / min of phosphorus oxychloride is generated. A mixed gas of nitrogen gas and oxygen gas is further introduced into this process gas into the process tube at flow rates of 20 liter / min and 160 cc / min, respectively. The temperature used for diffusion was 950 ° C., and the diffusion time was 20 minutes.

The circle in FIG. 12 is a view of the process tube 173 as seen from above. The outer circle is the process tube 17
3, the silicon substrate 170 is installed at the outer periphery of the process tube 173 and in the center of the process tube 173. Silicon substrate 170
The shaded area indicates a region with high resistivity, and the other regions are regions with uniform resistivity. The point where the uniformity was measured is a grid-like point which is 10 mm from the center of the obtained silicon substrate 170 in the left, right, and top, and 121 points or more in the silicon substrate 170. The uniformity was calculated by calculating the standard deviation from these measured values. The uniformity indicates the degree of dispersion of the specific resistance centered on the target sheet resistance of 27Ω / □. The direction of the gas ejection port 182 of the injector 176 is shown on the right side of the figure. The angle of the gas ejection port 182 is a value clockwise from a horizontal line passing through the center of the gas ejection port 182. The gas ejection direction is indicated by an arrow at the gas ejection port 182.

In FIG. 12A, the gas outlets 182 of the injectors 176 are arranged at 45 degrees with respect to the diameter direction of the process tube 173, and one gas outlet 182 is 45 degrees.
The distribution of the specific resistance when the other gas ejection port 182 is set to 135 degrees is shown. Although the region of high specific resistance is biased around the silicon substrate, the uniformity is relatively good. Figure 1
2 (b) is 45 ° and 315 °, respectively (the bisector is parallel to the tube diameter direction and faces the tube wall)
This is the case. The region with high resistivity occupies the left half of the silicon substrate, and the uniformity is the worst. FIG. 12C shows the case of 135 degrees and 225 degrees (the bisector is parallel to the diameter direction of the tube and faces the center of the tube). In this case, the region of high specific resistance is distributed on the right side of the silicon substrate. The uniformity at this time is also poor. Further, FIG. 12D shows the distribution of the specific resistance in the plane of the silicon substrate when it is oriented at 0 ° and 90 ° (the bisector is 45 ° with respect to the diameter direction of the tube). In this case, the distribution is similar to that in the case of FIG. 12A, but its uniformity is shown in FIG.
It turns out that it is a little worse than (a). From the above, Figure 12
(A) is the best. The angle at which the gas ejection port should be installed is preferably within ± 15 degrees from the predetermined angle. If it exceeds this range, the uniformity deteriorates.

[0065]

[Table 1]

Table 1 shows the injector 176 of FIG.
Target specific resistance is 18Ω / □, 27Ω / □, 6
It is the result of measuring the uniformity when the value is 80Ω / □.
The silicon substrate 17 is formed by using the impurity diffusion device of this embodiment.
The uniformity within the 0 plane and between the silicon substrates 170 was measured. The number of processed silicon substrates indicates the number of silicon substrates 170 filled in the substrate boat 171. As a result, in the diffusion furnace having the conventional structure, in order to make the gas flow constant, when processing a number less than or equal to the processable number of the apparatus, a dummy silicon substrate is loaded on the substrate boat 171 in addition to the target silicon substrate 170. However, although the specific resistance is made uniform, if the injector 176 is used as in the present embodiment, it is not necessary to use a dummy silicon substrate, and the substrate boat 171 can be used.
The number of silicon substrates 170 to be filled in is 25 to 100
Sufficient uniformity can be obtained regardless of the number of sheets.

By using a double coaxial injector having gas ejection ports in directions different from each other by 90 degrees as in the present invention for impurity diffusion in the gas phase, a large amount of semiconductor silicon substrates can be simultaneously treated in the silicon substrate plane. Further, it is possible to diffuse the impurities with good uniformity between the silicon substrates.

In the above embodiment, a vertical diffusion furnace is used to oxidize and
The process sequence and its structure for annealing are described. Next, an example of forming an oxide film by pyrogenic oxidation using a horizontal diffusion furnace will be described. Pyrogenic oxidation in a horizontal diffusion furnace in an oxygen-rich atmosphere does not result in normal combustion at the injector tip. Combustion becomes explosive due to excess oxygen, and the temperature of the hydrooxygen flame becomes extremely high. Since the diameter of the injector tip is normally narrowed, the ejection speed of the mixed gas of hydrogen and oxygen ejected from the injector tip is very high. Since the injector is usually composed of fused silica, the quartz at the tip of the injector is melted by the high-temperature combustion gas having a high flow velocity due to explosive combustion. Molten quartz is released with high-speed combustion gas,
It becomes fine powder and is introduced into the process tube together with the combustion gas. If the fine powder thus formed adheres to the silicon substrate when forming the device, the polycrystalline silicon film will grow abnormally with the quartz powder as the nucleus,
It reduces the uniformity during etching. Further, the reflectance of the surface changes during pattern formation by photolithography, which hinders normal pattern formation.

Examples of the horizontal diffusion furnace of the present invention will be described below with reference to the drawings. FIG. 13 is a block diagram of the horizontal diffusion furnace of the present invention. In the embodiment, the film thickness is 20 on the silicon substrate.
A description will be given of a case where a silicon oxide film of nm is subjected to pyrogenic oxidation at a growth temperature of 900 ° C. with a flow rate of hydrogen gas: a flow rate of oxygen gas = 5: 15 (liter / min).

In the figure, a silicon substrate 203 installed in a boat 202 is introduced into a process tube 201. The boat 202 is arranged on a cantilever 204. A gas baffle 206 is installed between the gas introduction port 205 introduced into the process tube 201 and the boat 202. An external combustion chamber 207 is attached to the gas inlet 205. An external combustion heater 208 and an injector 209 are attached to the external combustion chamber 207. Injector 209
Is equipped with an oxygen port 210 for supplying oxygen gas and a hydrogen / nitrogen port 211 for supplying hydrogen gas and nitrogen gas. The process tube 201 is provided with a gas inlet 205 connected to the external combustion chamber 207 and another gas inlet 212 for supplying oxygen gas. The gas inlet 212 is connected to the oxygen port 213. A hydrogen mass flow controller 214, an oxygen mass flow controller 215, and an oxygen mass flow controller 216 are connected to the hydrogen / nitrogen port 211, the oxygen port 210, and the oxygen port 213, respectively. The oxygen mass flow controller 216 is controlled by the hydrogen / oxygen mixture ratio calculation unit 217. Also, the oxygen mass flow controller 215 and the hydrogen mass flow controller 2
14 is controlled by the oxygen loss calculation unit 218.

Here, if the flow rates of hydrogen gas and oxygen gas are 5 liters / min and 15 liters / min, respectively, the flow rate ratio for preventing explosion due to hydrogen gas and oxygen gas is confirmed. . In the case of this embodiment,
The hydrogen gas: oxygen gas flow rate ratio is 3: 1. The upper limit hydrogen gas: oxygen gas flow ratio that explodes due to both gases =
It is 1.8: 1 or less, and there is no problem in the case of the embodiment. Here, the flow rate of hydrogen gas is 5 liters per minute as it is, while the flow rate of oxygen gas is to achieve a hydrogen gas flow rate: oxygen gas flow rate ratio of 1.8: 1 when performing external combustion.
The oxygen flow rate calculation unit 218 calculates 0.56 times the hydrogen gas flow rate, that is, 2.78 liters per minute.

On the other hand, the amount of oxygen gas mixed with the steam generated by the combustion is calculated by the hydrogen / oxygen mixture ratio calculation unit 217.
Calculated by In the case of this embodiment, the target oxygen gas flow rate is 15 liters per minute, so the amount of oxygen gas to be mixed with water vapor is 12.22 liters per minute. The mass flow controllers 214, 215, and 216 are controlled according to the hydrogen gas flow rate and the oxygen gas flow rate, respectively. Hydrogen and oxygen, the flow rates of which are determined by the hydrogen mass flow controller 214 and the oxygen mass flow controllers 215 and 216, are introduced into the external combustion device from the hydrogen / nitrogen port 211 and the oxygen port 210, respectively. This mixed gas is heated to 800 ° C. in the injector 209 by the external combustion heater 208 and burned at the tip of the injector 209. The injector 209 used in this example is shown in FIG.

The injector 209 is composed of an injector tip portion 220, an oxygen gas discharge end 221, an oxygen port 222, a hydrogen port 224, an O-ring seal 225 and a combustion chamber 226. Injector tip 22
At 0, a hydro-oxygen flame 227 is generated during operation. The injector 209 has a coaxial structure, and oxygen gas is introduced from the oxygen port 222 and discharged into the external combustion chamber 221 from the outer tube of the coaxial tube. On the other hand, hydrogen gas passes from the hydrogen port 223 through the inner tube of the coaxial tube and the injector tip 2
20 is introduced. Both the hydrogen gas and the oxygen gas are sufficiently heated by the external combustion heater while passing through the inside of the injector 209. In this embodiment, the injector tip 220
There is only one spout and the inner diameter of the opening is 3 mm. When the flow rate of hydrogen gas is 5 liters per minute, the jet speed of combustion gas is 11.8 m / min. Further, the heat capacity of the injector tip portion 220 is increased by making the thickness of the injector tip portion 220 sufficiently thick as 3 mm.
This is designed so that the temperature of the injector tip 220 does not rise significantly. Of course, in order to reduce the ejection speed, increase the inner diameter of the ejection port,
Injector tip 2 to further increase heat capacity
The thickness of 20 may be increased. Although high-purity fused silica of high purity was used as the injector material in this embodiment,
Synthetic quartz having a low hydroxyl group (OH) content and a low impurity content may be used. In any case, combustion occurs at the injector tip portion 220, so that the injector 209 gradually wears when used for a long period of time. Therefore, if an injector material having a high temperature resistance and a low content of impurities and a silicon carbide film deposited by CVD on the surface with a film thickness of 100 μm is formed, an injector 209 that can be used semipermanently can be obtained. It should be noted that the inner diameter and wall thickness of the ejection port need not be simply increased, but the length of the hydro-oxygen flame 227 must be taken into consideration. The length of the water oxygen flame is the injector tip 220.
To the object in front of it, usually 15
It is about 20 cm.

In this way, the injector tip portion 220
When hydrogen is burned at 5 liters per minute and oxygen at 2.78 liters per minute, steam is generated. This water vapor is introduced into the process tube 201 through the external combustion chamber 226. According to the method of this embodiment, the injector tip portion 220 is not melted, so that the fused silica powder is not introduced into the process tube as in the conventional case.

On the other hand, on the other hand, in order to achieve the target mixing ratio of hydrogen gas and oxygen gas, the mass flow controller 21
12.22 liters / minute of oxygen gas supplied by the No. 6 oxygen port 21 installed in the process tube 201
Introduced from 3. In this way, the process tube 2
In 01, the water vapor and this oxygen gas are mixed and the target mixing ratio of hydrogen gas and oxygen gas is achieved. These mixed gases become turbulent by the gas baffle 206, and then are transferred to the silicon substrate 203.

Through the above process, a very clean silicon oxide film which is a gate oxide film is formed on the silicon substrate. On the gate oxide film, there is no fused silica powder as shown in the conventional method. Therefore, even if phosphorus diffusion is performed by thermal diffusion when phosphorus atoms are doped into the polycrystalline silicon film by phosphorus oxychloride in a later step, the polycrystalline silicon film does not grow abnormally. Further, in the present example, subsequently, even in the known photolithography technique, the problem of halation due to surface roughness and the problem of etching residue in dry etching do not occur.

Although the present embodiment describes the embodiments relating to gate oxidation and polycrystalline silicon deposition, the same effect can be obtained in forming an oxide film for enhancing the adhesion of the deposited film before depositing the film by CVD. It goes without saying that you can expect it. Further, there is no difference in the effect of the present invention regardless of whether the base is a silicon oxide film on a silicon substrate, a silicon nitride film, or a pattern, instead of oxidation of the silicon substrate. However, the adhesion of the fused silica powder itself has a pattern dependency and a base material dependency, and the particle size at that time also has a dependency.

As described above, when the silicon oxide film is formed or pyrogenic oxidation is performed by the method and apparatus for forming a silicon oxide film according to the present invention, the tip portion of the quartz injector is melted regardless of the mixing ratio of hydrogen and oxygen. Can be significantly suppressed, the life of the quartz injector can be dramatically extended, and the fused quartz at the tip of the injector can be prevented from becoming fine powder and adhering to the silicon substrate. It is possible to prevent abnormal growth at the time of depositing a CVD film subsequent to particles and oxidation, and it is possible to perform the process without lowering workability and device performance and reliability.

[0079]

EFFECTS OF THE INVENTION As in the present invention, outward diffusion is performed when a semiconductor device having a high-concentration impurity layer or a polycrystalline silicon film containing high-concentration impurities on part or all of the front and back surfaces of a silicon substrate is subjected to heat treatment. It is possible to prevent the fluctuation of the threshold voltage of the MOS transistor having the LDD and DDD structures and the reduction of the current driving capability.

Further, in the semiconductor manufacturing apparatus of the present invention, it is possible to diffuse impurities into a large amount of semiconductor silicon substrates at the same time with good uniformity within the silicon substrate surface and between the silicon substrates.

Furthermore, when pyrogenic oxidation is performed, melting of the tip of the quartz injector can be significantly suppressed, and the life of the quartz injector can be dramatically extended.

[Brief description of drawings]

FIG. 1 is a process sectional view of a method for manufacturing a semiconductor device having an LDD structure according to the present invention.

FIG. 2 is a diagram showing a heat treatment sequence of a method for manufacturing a semiconductor device of the present invention.

FIG. 3 is a process sectional view of a method for manufacturing a semiconductor device having a DDD structure according to the present invention.

FIG. 4 is a diagram showing a heat treatment sequence of a method for manufacturing a semiconductor device of the present invention.

FIG. 5 is a process cross-sectional view of a method for manufacturing a semiconductor device that is a capacitive element of the present invention.

FIG. 6 is a diagram showing a heat treatment sequence of a method for manufacturing a semiconductor device of the present invention.

FIG. 7 is a diagram showing a semiconductor manufacturing apparatus of the present invention.

FIG. 8 is a diagram showing a vertical diffusion furnace which is a semiconductor manufacturing apparatus of the present invention.

FIG. 9 is a diagram showing an injector of a semiconductor manufacturing apparatus of the present invention.

FIG. 10 is a longitudinal sectional view of the injector of the semiconductor manufacturing apparatus of the present invention.

FIG. 11 is a sectional view of the injector of the semiconductor manufacturing apparatus of the present invention.

FIG. 12 is a diagram showing a specific resistance distribution on a silicon substrate formed by the semiconductor manufacturing apparatus of the present invention.

FIG. 13 is a diagram showing a configuration of a semiconductor manufacturing apparatus of the present invention.

FIG. 14 is a diagram showing an injector of a semiconductor manufacturing apparatus of the present invention.

FIG. 15 is a process sectional view of a method for manufacturing a conventional semiconductor device that is a capacitive element.

FIG. 16 is a process sectional view of a method for manufacturing a semiconductor device having a conventional LDD structure.

FIG. 17 is a process sectional view of a method for manufacturing a conventional semiconductor device having a DDD structure.

FIG. 18 is a diagram showing a conventional semiconductor manufacturing apparatus.

FIG. 19 is a diagram showing a specific resistance distribution on a silicon substrate formed by a conventional semiconductor manufacturing apparatus.

FIG. 20 is a diagram showing a conventional semiconductor manufacturing apparatus.

FIG. 21 is a diagram showing a specific resistance distribution on a silicon substrate formed by a conventional semiconductor manufacturing apparatus.

FIG. 22 is a diagram showing a specific resistance distribution on a silicon substrate formed by a conventional semiconductor manufacturing apparatus.

FIG. 23 is a diagram showing a configuration of a conventional semiconductor manufacturing apparatus.

[Explanation of symbols]

 101 Silicon Substrate 102, 103 Well Region 104 Isolation Region 105 Gate Oxide Film 106, 107 Polycrystalline Silicon Film 108 Photoresist 109 Phosphorus Ion Implantation 110 LDD Region 113 Channel Region 114, 115 Source / Drain Region 116 Sidewall 117 Oxide Film

Claims (19)

[Claims] 1. A high-concentration impurity diffusion layer or a conductive film containing a high-concentration impurity is formed on a semiconductor substrate, and thereafter, the surface of the semiconductor substrate other than the region covered with the impurity diffusion layer or the conductive film is oxidized. In forming the film, it comprises a first step of introducing the semiconductor substrate into an oxidation device, a second step of bringing the semiconductor substrate to a predetermined temperature after the introduction, and a third step of annealing at the predetermined temperature. The first, second, third
2. The method for manufacturing a semiconductor device, wherein the step is processed in a mixed atmosphere of oxygen and nitrogen. 2. A high-concentration impurity diffusion layer or a conductive film containing a high-concentration impurity is formed on a semiconductor substrate, and then the surface of the semiconductor substrate other than the region covered with the impurity diffusion layer or the conductive film is oxidized. In forming the film, it comprises a first step of introducing the semiconductor substrate into an oxidation device, a second step of bringing the semiconductor substrate to a predetermined temperature after the introduction, and a third step of annealing at the predetermined temperature, A method of manufacturing a semiconductor device, comprising performing the first step in a low-temperature oxygen atmosphere and treating the second and third steps in a non-oxidizing atmosphere. 3. A cell plate is formed on a semiconductor substrate via a capacitive insulating film, and the cell plate is formed of a conductive film containing a high concentration of impurities, and then the semiconductor substrate is introduced into an oxidation device. The first step, the second step of bringing the temperature to a predetermined temperature after the introduction, and the third step of annealing at the predetermined temperature are performed. The first, second and third steps are mixed with oxygen and nitrogen. A method of manufacturing a semiconductor device, which comprises processing in an atmosphere to form a gate oxide film. 4. The gate oxide film is formed by performing the first step in a low temperature oxygen atmosphere and treating the second and third steps in a non-oxidizing atmosphere.
A method for manufacturing a semiconductor device as described above. 5. A step of forming a conductive film containing impurities on a semiconductor substrate, a step of implanting first ions with the conductive film as a mask, and a step of oxidizing the semiconductor substrate after the first ion implantation is performed. It comprises a first step of introducing, a second step of bringing the material to a predetermined temperature after the introduction, and a third step of annealing at the predetermined temperature. In a mixed atmosphere of, and oxidizing, and then forming an insulating film on the sidewall of the conductive film,
A method of manufacturing a semiconductor device, wherein second ion implantation is performed using the conductive film and the sidewall as a mask. 6. A step of performing the first step in a low-temperature oxygen atmosphere, treating the second and third steps in a non-oxidizing atmosphere and oxidizing, and then forming an insulating film on a sidewall of the conductive film. And a second step using the conductive film and the sidewall as a mask.
6. The method of manufacturing a semiconductor device according to claim 5, wherein the ion implantation is performed. 7. A step of forming a conductive film containing impurities on a semiconductor substrate, a step of implanting first ions using the conductive film as a mask, and a step of oxidizing the semiconductor substrate after the first ion implantation is performed. It comprises a first step of introducing, a second step of bringing the material to a predetermined temperature after the introduction, and a third step of annealing at the predetermined temperature. In a mixed atmosphere of, and oxidizing, and then forming an insulating film on the sidewall of the conductive film,
A method of manufacturing a semiconductor device, wherein second ion implantation is performed using the conductive film and the sidewall as a mask. 8. A step of performing the first step in a low-temperature oxygen atmosphere, performing the second and third steps in a non-oxidizing atmosphere and oxidizing, and then forming an insulating film on a sidewall of the conductive film. And a second step using the conductive film and the sidewall as a mask.
8. The method for manufacturing a semiconductor device according to claim 7, wherein the ion implantation is performed. 9. A conductive film containing impurities is formed on a semiconductor substrate, and the first conductive film having a large diffusion coefficient is doped at a low concentration by ion-implanting the conductive film as a mask. After heavily doping the impurity of 2,
The method comprises a first step of introducing the semiconductor substrate into an oxidation device, a second step of bringing the semiconductor substrate to a predetermined temperature after the introduction, and a third step of annealing at the predetermined temperature.
A method of manufacturing a semiconductor device, which comprises performing the steps 2 and 3 in a mixed atmosphere of oxygen and nitrogen. 10. The method of manufacturing a semiconductor device according to claim 9, wherein the first step is performed in a low-temperature oxygen atmosphere and the second and third steps are performed in a non-oxidizing atmosphere. .. 11. A process tube, a substrate boat in which a semiconductor substrate is set in the process tube, and an injector for introducing a process gas into the process tube, wherein the process gas introduced from the injector is the plane of the semiconductor substrate. A semiconductor manufacturing apparatus characterized by being supplied in parallel. 12. A process tube, a boat installed in the process tube, a gas introduction port for introducing gas into the process tube, an exhaust port for discharging gas from the process tube, and the gas introduction. The gas introduced from the mouth is introduced into the process tube through an injector, and the injector has a length in the longitudinal direction of the process tube that exceeds the length of the boat. 13. The semiconductor manufacturing apparatus according to claim 12, wherein the injector is a coaxial double tube. 14. The outer pipe of the double pipe of the injector has at least 2 having an angle of 90 degrees with respect to the center of the pipe cross section.
One first gas ejection port and an inner pipe of the double pipe are provided with a second ejection port having at least an angle of 135 degrees with respect to each of the first ejection ports. Item 14. The semiconductor manufacturing apparatus according to item 13. 15. The gas introduced into the injector is discharged from the inner pipe between the inner pipe and the outer pipe, and then discharged from the outer pipe into the process tube. The semiconductor manufacturing apparatus according to claim 13. 16. Thermal oxidation in a water vapor atmosphere by burning hydrogen gas and oxygen gas on a polycrystalline silicon film, a silicon dioxide film, a silicon nitride film, or a composite film composed of a combination of these films on a silicon substrate. And a step of performing the thermal oxidation, and a polycrystalline silicon film, a silicon dioxide film, a silicon nitride film or other vapor phase growth film on the silicon substrate or on the film on the silicon substrate by a chemical vapor deposition method in succession. A step of forming
In the thermal oxidation, the oxygen gas flow rate is burned at 0.56 times the hydrogen gas flow rate with respect to the hydrogen gas flow rate, and the steam generated by the combustion is further mixed with oxygen for oxidation. Of manufacturing a semiconductor device. 17. A combustion chamber for hydrogen and oxygen gas, an external combustion heater and an injector are provided outside the process tube, and steam generated in the combustion chamber is sent into the process tube and further installed in the process tube. Means for introducing oxygen from another inlet and automatically determining the hydrogen gas flow rate and the oxygen gas flow rate used for the combustion, and the calculation for calculating the amount of oxygen to be mixed with the steam generated by the combustion. A semiconductor manufacturing apparatus having means. 18. The injector has a coaxial structure,
18. The semiconductor manufacturing apparatus according to claim 17, wherein hydrogen gas is released from the inner pipe and oxygen gas is released from the outer pipe. 19. The injector according to claim 17, wherein the injector is made of sintered silicon carbide of silicon carbide and silicon, and silicon carbide is coated around the injector.
The semiconductor manufacturing apparatus described.