JPH0677425A - Integrated circuit - Google Patents

Abstract

PURPOSE:To provide an integrated circuit including a semi-insulating GaAs substrate on which FETs of stable operation are formed. CONSTITUTION:An integrated circuit includes a semi-insulating GaAs substrate 10, on which n-channel FETs 12 and hole sources are formed. The hole source is a FET having a recessed structure in which holes are generated by collisional ionization in its active region 182. The holes from the source are diffused into the substrate near the FET 12. Since the holes are recombined with electrons, even if captured at deep levels in the substrate, the drain current of the FET is prevented from decreasing due to back-gate effects or side-gate effects. The decrease in gain of the FET is also prevented when a signal at hither frequency is applied to the gate electrode of the FET.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit capable of stably operating an FET, especially an n-channel FET.

[0002]

Hitherto, MMIC (M onolithic M icro
wave I ntergrated C ircuit) and on the IC such ultrafast logic IC, FET (F ield E ffect T ransistor), diodes, resistors, capacitance or other desired electric circuit elements thereof, a semi-insulating compound semiconductor substrate, for example G
It is provided on the aAs substrate and integrated.

[0003]

However, in the semi-insulating compound semiconductor substrate, impurity compensation is performed in order to increase its insulation resistance. Therefore, since a deep level for impurity compensation or a deep level for impurity compensation exists in the substrate, when a negative potential is applied to the substrate surface a opposite to the substrate surface a on which the FET is provided, The electrons injected into the substrate from the substrate surface b are trapped in a deep level, and the trapped electrons increase the potential of the electron on the substrate surface b side. Therefore, when the n-channel FET is provided on the substrate, the depletion layer is formed from the substrate surface b side to the n-channel FET.
To the side of the channel to narrow the channel, resulting in a decrease in drain current (this phenomenon is called back gate effect). In addition, the electrodes of other electric circuit elements are FET
Even when a negative potential is applied to this electrode provided on the substrate surface a adjacent to, the electrons injected from this electrode into the substrate are trapped in a deep level, so that the drain current decreases ( This phenomenon is called the side gate effect).

Further, when the frequency of the electric signal applied to the gate electrode of the FET reaches a certain value, for example, 50 KHz or more,
There is a problem that the gain of the FET is reduced. The generation mechanism is not necessarily clear, but it is considered as follows. That is, when an electric signal is applied to the gate electrode, electrons are trapped in a deep level and emitted from the deep level in accordance with a periodical change in the voltage amplitude of this signal. It is considered that the electrons are not emitted but remain trapped, and as a result, the gain is reduced.

In order to solve the above-mentioned conventional problems, the present invention is to provide an integrated circuit capable of eliminating the electrical influence of electrons trapped in deep levels in a substrate.

[0006]

In order to achieve this object, an integrated circuit according to the present invention is an integrated circuit in which an electric circuit element including a circuit FET is provided on a semi-insulating compound semiconductor substrate. It is characterized by comprising a hole injection source provided in the vicinity of the FET.

[0007]

According to such a structure, since the hole injection source is provided, when the electrons are trapped in the deep level in the semi-insulating compound semiconductor substrate, the holes are transferred through the hole injection source. Can be injected into the substrate and recombined with deep level trapped electrons, thus eliminating the trapped electrons.

Moreover, since the hole injection source is provided in the vicinity of the circuit FET, trapped electrons in the circuit FET vicinity region can be eliminated.

[0009]

Embodiments of the present invention will be described below with reference to the drawings. It should be noted that the drawings are merely schematic representations so that the present invention can be understood, and therefore the present invention is not limited to the illustrated examples.

FIG. 1 and FIG. 2 are a sectional view and a plan view schematically showing the structure of a main part of a first embodiment of the present invention. In these drawings, the configuration of the portion of the integrated circuit, which is mainly provided with the circuit FET and the hole injection source, is shown.

The integrated circuit of this embodiment has a circuit FET1.
2 and the hole injection source 14 provided in the vicinity of the FET 12 and other electric circuit elements (not shown) other than these are provided on the semi-insulating compound semiconductor substrate 10.

In this embodiment, the substrate 10 is made of semi-insulating Ga.
An As substrate is used, and the circuit FET 12 and the hole injection source 14 are GaAs FETs having a recess structure. And the substrate surface 10
A circuit FET 12, a hole injection source 14, and other electric circuit elements (not shown) are provided on a through an undoped GaAs buffer layer 16. The circuit FET 12 is provided within a range in which holes are diffused from the hole injection source 14.

The circuit FET 12 has an n-GaAs active layer 181 provided on the buffer layer 16 in the element forming region P1.
And n ⁺ -G provided separately from each other on the active layer 181.
aAs contact layers 191 and 192, a recess 201 provided in the active layer 181 in a region between the contact layers 191 and 192, a gate electrode 221 provided in the recess 201, and a source provided on the contact layers 191 and 192. An electrode 241 and a drain electrode 261 are provided. Further, the hole injection source 14 includes an n-GaAs active layer 182 provided on the buffer layer 16 in the element formation region P2 and an n ⁺ -GaAs provided on the active layer 182 so as to be separated from each other.
The contact layers 193 and 194, the recess 202 provided in the active layer 182 in the region between the contact layers 193 and 194, and the gate electrode 22 provided in the recess 202.
2 and a source electrode 242 and a drain electrode 262 provided on the contact layers 193 and 194.

The gate electrodes 221, 222 are Schottky electrodes, and the source electrodes 241, 242 and the drain electrodes 261, 262 are ohmic electrodes. Although it is preferable to provide the contact layers 191 to 194, it is not always necessary to provide these contact layers. Further, the hole injection source 14 is an FET having an arbitrary suitable structure other than the recess structure,
For example, a FET having a self-aligned gate structure formed by using an ion implantation process may be used.

Further, the circuit FET 12, the hole injection source 14 and other electric circuit elements (not shown) are electrically insulated and separated by the element separating portion 28. The element isolation portion 28 is an oxygen ion implantation layer, and when forming it, the undoped GaAs buffer layer 1 is sequentially formed on the substrate surface 10a.
6, after the n-GaAs layer 18 and the n ⁺ -GaAs layer 19 are laminated, oxygen is added to the region (insulation separation region) where the circuit FET 12, the hole injection source 14 and other electric circuit elements are to be insulated. Inject ions. At this time, oxygen ions are implanted to a depth from the n ⁺ -GaAs layer 19 to the buffer layer 16 or the substrate 10. The element isolation portion 28 is formed by the portion into which the oxygen ions are implanted, the active layers 181 and 182 are formed by the n-GaAs layer 18 in the portion of the element forming region where the oxygen ions are not implanted, and n ^{+ in} the portion of the element forming region is formed. -The contact layers 191 to 191 are formed by the GaAs layer 19.
194 is formed. The element isolation portion 28 thus formed is shown by being surrounded by a dotted line in FIG. The element isolation portion 28 may be any suitable element isolation means other than the oxygen ion implanted layer, for example, a groove.

When holes are generated by the hole injection source 14,
A voltage having a magnitude that causes impact ionization in the active layer 182 is applied between the source electrode 242 and the drain electrode 262 to generate holes by impact ionization. At this time, the gate electrode 222 of the hole injection source 14 may be grounded, or a voltage may be applied to the gate electrode 222. By applying a voltage of any suitable magnitude to the gate electrode 222, the efficiency of generating holes can be increased. The generated holes are
It flows into the substrate 10 in the vicinity of the circuit FET 12 through the element isolation portion 28, the buffer layer 16 or the substrate 10 and recombines with the electrons trapped in the deep level in the substrate 10 in the region near the circuit FET 14. .

When the source electrode 242 is grounded or a negative potential is applied to the source electrode 242 and a positive potential is applied to the drain electrode 262, the holes generated in the active layer 182 are closer to the source electrode than the drain electrode 262 side. 242
Since the holes are efficiently injected into the circuit FET 12, it is preferable to arrange the source electrode 242 side of the hole injection source 14 close to the circuit FET 12 in order to efficiently inject holes into the substrate 10 in the region near the circuit FET 12. . Note that the positional relationship between each constituent component of the circuit FET 12 and each constituent component of the hole injection source 14 is not limited to the illustrated example, and holes from the hole injection source 14 are provided in the substrate in the vicinity of the circuit FET 12. As long as it can be injected into 10, the positional relationship does not matter.

Next, focusing on the circuit FET 12 and the hole injection source 14 among the electric circuit elements provided in the integrated circuit of this embodiment, the manufacturing process of the circuit FET 12 and the hole injection source 14 will be described. 3 and 4 are circuit FET1
FIG. 3 is a cross-sectional view showing the main manufacturing steps of the hole injection source 2 and the hole injection source 14 in stages.

[0019] First of all, MBE (M olecular B eam E pitaxy)
Method, an undoped GaAs buffer layer 16, a Si-doped n-GaAs layer 18 and an n ⁺ -GaAs layer 19 are sequentially laminated on the semi-insulating GaAs substrate 10 (FIG. 3).
(A)).

Next, oxygen ions are implanted into an insulation isolation region for insulating the circuit FET 12, the hole injection source 14 and other electric circuit elements to form an element isolation portion 28 composed of an oxygen ion implantation layer ( FIG. 3B). At this time, oxygen ions are implanted to a depth from the n ⁺ -GaAs layer 19 to the buffer layer 16. The n-GaAs layer 18 in the element forming regions P1 and P2 is the active layer 181 of the circuit FET 12.
And the active layer 182 of the hole injection source 14.

Next, n ⁺ -Ga in the element forming region P1 is formed.
The source electrode 241 and the drain electrode 26 are formed on the As layer 19.
1 and the source electrode 242 and the drain electrode 262 are separately formed on the n ⁺ -GaAs layer 19 in the element formation region P2 (FIG. 3).
(C)).

Next, the source electrode 241 and the drain electrode 26
1 between the n ⁺ -GaAs layer 19 and the active layer 18
1 is etched and cut out, thereby dividing the n ⁺ -GaAs layer 19 in the element forming region P1 into two to form contact layers 191 and 192 and a recess 201 in the active layer 181. At the same time, the n ⁺ -GaAs layer 1 in the portion between the source electrode 242 and the drain electrode 262 is formed.
9 and the active layer 182 are notched by etching, thereby dividing the n ⁺ -GaAs layer 19 in the element forming region P2 into two to form contact layers 193 and 194 and a recess 202 in the active layer 182. (FIG. 4 (A)).

Next, a gate electrode 221 is formed in the recess 201 and a gate electrode 222 is formed in the recess 202 (FIG. 4 (B)).

As can be understood from the above description, in this embodiment, the circuit FET 12 and the hole injection source 14 can be formed in parallel by the same manufacturing process.

Next, description will be made on an experiment for investigating the influence of the hole injection performed by the hole injection source 14 of this embodiment on the back gate effect, the side gate effect and the gain fluctuation.

FIG. 5 is a sectional view schematically showing the structure of the main part of the experimental apparatus. The experimental apparatus shown in the figure includes a circuit FET 12, a hole injection source 14, and an experimental device 30 provided on a substrate surface 10a via a buffer layer 16, and a substrate surface 10b opposite to the substrate surface 10a. And an ohmic electrode 32. In this experimental apparatus, for the sake of convenience of the experiment, no element other than the circuit FET 12 and the hole injection source 14 was provided among the electric circuit elements included in the integrated circuit of the above-described embodiment.

The experimental device 30 is a device for examining the side gate effect, and is used for the buffer layer 1 in the device forming region P3.
6 on the n-GaAs layer 183 and n ⁺ -GaAs sequentially.
The layer 195 and the ohmic electrode 34 are provided. The ohmic electrode 32 is an electrode for examining the back gate effect. Hereinafter, the ohmic electrode 34 is referred to as the side gate electrode 3
4 and the ohmic electrode 32 are referred to as the back gate electrode 32.

Further, the hole injection source 14 is arranged on one side of the circuit FET 12 with a distance L _hj from the circuit FET 12, and the experimental device 30 is provided with the experimental element 30.
It is arranged on the other side of the circuit FET 12 with a distance L _sg from it.

FET 12 for these circuits and hole injection source 14
The element for experiment 30 and the element for experiment 30 are electrically insulated and separated by the element isolation portion 28, and the buffer layer 1
N-GaAs layer 18 and n ⁺ -GaAs on
After laminating the layer 19, oxygen ions are implanted into the region (insulation isolation region) of the circuit FET 12, the hole injection source 14, and the experimental device 30 excluding the device formation region. At this time, oxygen ions are implanted to a depth from the n ⁺ -GaAs layer 19 to the buffer layer 16. The portion of the insulating isolation region into which oxygen ions are implanted becomes the element isolation portion 28.

FIG. 6 is a diagram showing experimental results regarding the back gate effect. The vertical axis of the figure is the drain current I _ds1 [mA] of the circuit FET 12, and the horizontal axis is the back gate voltage (applied to the back gate electrode 32). Voltage) V _B [V].

In the experiment on the back gate effect, FIG.
FET 12 for a circuit and hole injection source 1
4 has a gate length of 0.3 μm and a gate width of 10 μm, and the separation distance L between the circuit FET 12 and the hole injection source 14
_hj was set to 20 μm. Further, the source electrode 241 and the gate electrode 221 of the circuit FET 12 are commonly connected and grounded, and the drain electrode 261 is connected to the ground via the power source V _ds1 . Similarly, the source electrode 24 of the hole injection source 14 is connected.
2 and the gate electrode 222 are commonly connected and grounded, and the drain electrode 262 is connected to ground through the power supply V _ds2 . Further, the back gate electrode 32 was connected to the ground via the power supply V _B.

Then, the drain voltage V of the circuit FET 12
_ds1 and while maintaining a constant value, the value of the drain voltage V _ds2 and the back gate voltage V _B of the hole injection source 14 by varying the respective dependence on the back gate voltage V _B of the drain current I _ds1 circuit for FET12 I checked. The characteristic curve of the drain current I _ds1 obtained in this manner is shown with reference numerals A _{0 to} A ₄ in the figure.

Characteristic curves A ₀ , A ₁ , A ₂ , A ₃ and A ₄
The drain voltage V _ds1 when obtaining
[V] and drain voltage V _ds2 are 0, 1, 2,
A 3 and 4 [V], the drain voltage V _ds1, V _ds2 a range of 0~-20 [V] to the back gate voltage V _B while holding constant the voltage value of the above when obtain each characteristic curve Was changed to obtain each characteristic curve. In the experiment on the back gate effect, the side gate electrode 34 is open.

In the experimental example of FIG. 6, when the drain voltage V _ds2 is _set to 0, 1 and 2 [V] (the characteristic curves A ₀ , A ₁ and A ₂ ), the drain current is in any case. The I _ds1 characteristics are almost the same, and the back gate voltage V
_In the range of _B = 0 to about −2 [V], the drain current I _ds1 is almost constant and does not change, but the back gate voltage V _B = about −2.
In the range of -20 [V], the drain current I _ds1 decreases as the back gate voltage V _B decreases.

[0035] When the drain voltage V _ds2 3 [V] (the case of curve A _3), when the reduction rate of the drain current I _ds1 is a drain voltage V _ds2 was 0,1 or 2 [V] The drain current I _ds1 is still conspicuously reduced although it is slightly increased as compared with the above.

When the drain voltage V _ds2 is 4 [V] (characteristic curve A ₃ ), the back gate voltage V _B = 0.
Drain current I _ds1 over the entire range of −20 [V]
Can be understood to be almost constant, and therefore the dependency of the drain current I _{ds1 on} the back gate voltage V _B (back gate effect) is eliminated.

FIG. 7 is a diagram showing the experimental results regarding the current-voltage characteristics of the hole injection source. The current-voltage characteristics shown in the figure are the drain voltage V in the hole injection source 14 included in the experimental apparatus used in the experiment on the back gate effect described above.
_ds2 changing the are of obtained by measuring a drain current I _ds2, the drain current I _ds2 the vertical axis of FIG. [mA]
And the horizontal axis represents the drain voltage V _ds2 [V].

[0038] As can be understood from the figure, the drain current I _ds2 is in the range of the drain voltage V _ds2 = 0 to about 0.6 [V] is greatly increased with increasing drain voltage V _ds2, the drain voltage V _ds2 = about In the range of 0.6 to about 3 [V], the drain voltage V _ds2 increases gradually, and
In the range of the drain voltage V _ds2 = about 3 to about 4.6 [V], the drain voltage V _ds2 relatively increases as the drain voltage V _ds2 increases.

The drain current I _ds2 is the drain voltage V _ds2
=> About 3 to about 4.6 [V], the phenomenon of a large increase again is that impact ionization occurs in the active layer 182 of the hole injection source 14 and the holes generated thereby are generated in the buffer layer 16.
It is considered that this is a phenomenon that represents the injection into the substrate 10 via the.

On the other hand, in the experimental results of FIG. 6, a decrease ratio of the drain current I _ds1 circuit for FET12 becomes gentle when the drain voltage V _ds2 of the hole injection source 14 and 3 and 4 [V], thus It can be understood that the decrease rate of the drain current I _ds1 becomes gentle with the start of hole generation or the start of injection by the hole injection source 14.

The decrease in the drain current I _ds1 of the circuit FET 12 is due to the depletion layer extending so as to narrow the channel of the circuit FET 12 due to the action of the electrons trapped in the deep level in the substrate 10. , therefore by making some or all of the trapped electrons holes and recombined to disappear, more preferably less reduction ratio of the drain current I _ds1 is considered possible to eliminate the decrease of the drain current I _ds1.

FIG. 8 is a diagram showing an experimental result regarding the side gate effect. In the figure, the vertical axis represents the drain current I _ds1 [mA] of the circuit FET 12, and the horizontal axis represents the side gate voltage (applied to the side gate electrode 32). Voltage) V _sg [V].

In the experiment on the side gate effect, FIG.
FET 12 for a circuit and hole injection source 1
4 has a gate length of 0.3 μm and a gate width of 10 μm, and the separation distance L between the circuit FET 12 and the hole injection source 14
_hj was set to 30 μm. Further, the source electrode 241 and the gate electrode 221 of the circuit FET 12 are commonly connected and grounded, and the drain electrode 261 is connected to the ground via the power source V _ds1 . Similarly, the source electrode 24 of the hole injection source 14 is connected.
2 and the gate electrode 222 are commonly connected and grounded, and the drain electrode 262 is connected to ground through the power supply V _ds2 . Further, the distance L _sg between the circuit FET 12 and the experimental device 30 was set to 30 μm, and the side gate electrode 34 was connected to the ground via the power source V _sg .

Then, the drain voltage V of the circuit FET 12
_While holding _ds1 at a constant value, the drain voltage V _ds2 and the side gate voltage V _sg of the hole injection source 14 are changed to change the side gate voltage V _ds1 of the drain current I _ds1.
The dependence on _sg was investigated. The characteristic curve of the drain current I _ds1 thus obtained is indicated by reference numerals B ₀ and B ₁ in the figure.

When the characteristic curves B ₀ and B ₁ are obtained, the drain voltage V _ds1 is a common voltage value 1 [V] and the drain voltage V _ds2 is 0 and 6 [V], respectively, and each characteristic curve is obtained. 0-1 drain voltage V _ds1, the V _ds2 while holding constant the voltage value of the aforementioned side gate voltage V _sg when
Each characteristic curve was obtained by changing in the range of 0 [V]. still,
In the experiment on the side gate effect, the back gate electrode 3
The applied voltage of 2 is 0 [V].

In the experimental example of FIG. 8, when the drain voltage V _ds2 is 0 [V] (in the case of the characteristic curve B ₀ ), the side gate voltage V _sg is decreased from 0 [V] to −10 [V]. Then, the drain current I _ds1 starts to decrease at the side gate voltage V _sg = about -2.8V. On the other hand, the drain voltage V
_{When ds2} is 6 [V] (characteristic curve B ₁ ),
Side gate voltage V _sg = about -5.8 V and drain current I
_ds1 begins to decrease. Therefore, it can be understood that the side gate effect is suppressed by the hole injection. Electrons injected from the side gate electrode 34 into the substrate 10 and trapped in deep levels are recombined with holes and disappeared,
It is thought that the side gate effect can be suppressed.

FIGS. 9 (A) and 9 (B) are diagrams showing the experimental results regarding the gain variation, and the horizontal axis of these diagrams shows the circuit F.
The frequency (signal frequency) x [Hz] of the electric signal applied to the gate electrode 221 of the ET 12 is on a logarithmic scale, the left vertical axis represents the gain g _a [dB] of the circuit FET 12 and the right vertical axis represents the signal frequency x. represents the gain g differential gain obtained by subtracting the _{a Δg a} [dB] at the signal frequency 20 [Hz] from the gain g _a in.

In the experiment concerning the gain fluctuation, the experimental device having the structure in which the experimental element 30 is omitted in the experimental device of FIG. 5 is used, and the gate length of the circuit FET 12 and the hole injection source 14 is 0.3 μm and the gate width is 150 μm. And the separation distance L _hj between the circuit FET 12 and the hole injection source 14 is 30
μm. In addition, the source electrode 24 of the circuit FET 12
1 is grounded, the gate electrode 221 is connected to ground via a signal source (not shown), the drain electrode 261 is connected to ground via a power supply V _ds1 , and the hole injection source 1
The source electrode 242 and the gate electrode 222 of _No. 4 are commonly connected and grounded, and the drain electrode 262 is connected to the ground via the power supply V _ds2 .

[0049] Then, by changing the drain voltage V _ds2 and signal frequency x as-hole injection source 14 holding the drain voltage V _ds1 of circuit FET12 a constant value gain g _a
And the dependence of the difference Δg _{a on} the signal frequency x was investigated. The characteristic curves of the gain g _a and the difference Δg _a obtained in this way are shown with reference symbols C ₀ and D ₀ in FIG. 9A, and the reference symbols C ₁ and D in FIG. Shown with ₁ .

The drain voltage V _ds1 when the characteristic curves C ₀ and D ₀ and C ₁ and D ₁ are obtained is a common voltage value of 2 [V], and the drain voltage when the characteristic curves C ₀ and D ₀ are obtained. V _ds2
Is 0 [V], and characteristic curve C _1, D ₁ the drain voltage V _ds2 when got is 5 [V], the drain voltage V _ds1, V _ds2 the aforementioned voltage value when the yield of each characteristic curve Each characteristic curve was obtained by changing the signal frequency x in the range of 10 to 1 M [Hz] while keeping it constant at. In the experiment on the gain variation, the back gate electrode 32 is open.

The characteristic curves C ₀ and D ₀ of FIG. 9A show how the gain g _a and the difference Δg _a change when the hole injection source 14 does not perform hole injection. In the state where the hole injection is not performed, when the signal frequency x is increased, the gain g _a and the difference Δg _a start to decrease from the time when the signal frequency x becomes approximately 100 [Hz]. In the range where the signal frequency x is approximately 100 to 20 K [Hz], the gain g _a
And the decrease amount of the difference Δg _a is small, but the decrease amount of the gain g _a and the difference Δg _a becomes very large when the signal frequency x exceeds approximately 20 K [Hz].

On the other hand, the characteristic curves C ₁ and D _{1 of} FIG.
Represents the state of changes in the gain g _a and the difference Δg _a when the hole injection source 14 is injecting holes. Even when holes are being injected, the signal frequency x is almost 1
From the time when it becomes 00 [Hz], the gain g _a and the difference Δg _a
Begins to decrease. However, the signal frequency x is almost 100-
The decrease amount of the gain g _a and the difference Δg _a is small in the range of 1 M [Hz], and the decrease amount is much smaller than that in the case where hole injection is not performed. By thus injecting holes, it is possible to reduce or almost eliminate the gain variation.

In the experimental example of FIG. 9A, the gain g _{a at} the signal frequency of 20 [Hz] is about 14.13 [d].
B], and signal frequencies of 50 K [Hz] and 20 [Hz]
The difference Δg _a gain g _a in is about -0.45 [d
B]. On the other hand, in the experimental example of FIG. 9B, the gain g _{a at} the signal frequency of 20 [Hz] is about 13.78.
[DB], and signal frequencies of 50 K [Hz] and 20 [H]
z] has _a difference Δg _a of about −0.15.
It was [dB].

FIG. 10 is a sectional view schematically showing the structure of the main part of the second embodiment of the present invention. The constituents corresponding to those of the first embodiment are designated by the same reference numerals, and detailed description of the same points as those of the first embodiment will be omitted.

The integrated circuit of this embodiment has a hole injection source 36.
And has the same configuration as the first embodiment except that the configuration of the hole injection source 36 is different.

The hole injection source 36 includes an n-GaAs active layer 38 provided on the buffer layer 16 in the element formation region P2, and n ⁺ -GaAs contact layers 40 and 42 provided on the active layer 38 and spaced from each other. , The current constriction portion 44 provided in the active layer 38 in the region between the contact layers 40 and 42.
And ohmic electrodes 46 and 48 provided on the contact layers 40 and 42. The current constriction portion 44 is a recess. By providing the current confinement portion 44, the active layer 3
The current path of No. 8 is narrowed to facilitate collision ionization.

The active layer 38 of the hole injection source 36, the contact layers 40 and 42, the current confinement portion 44, and the ohmic electrodes 46 and 48 are respectively the active layer 182 of the hole injection source 14 and the contact layer 193 of the first embodiment. , 194, recess 20
2, the source electrode 242 and the drain electrode 262 are formed in the same manner. Therefore, the structure of the hole injection source 36 is the same as the structure of the hole injection source 14 of the first embodiment when the gate electrode 222 is removed.

When holes are generated by the hole injection source 36,
A voltage having a magnitude that causes impact ionization in the active layer 38 is applied between the ohmic electrodes 44 and 46 to generate holes by impact ionization. Substrate 1 near circuit FET 12
In order to efficiently inject holes into 0, circuit FET
It is preferable to apply a negative potential to the ohmic electrode 46 on the side closer to 12 and a positive potential to the ohmic electrode 48 on the far side.

FIG. 11 is a sectional view schematically showing the structure of the main part of the third embodiment of the present invention. The constituents corresponding to those of the first embodiment are designated by the same reference numerals, and detailed description of the same points as those of the first embodiment will be omitted.

The integrated circuit of this embodiment has a hole injection source 50.
And has the same configuration as the first embodiment except that the configuration of the hole injection source 50 is different.

The hole injection source 50 includes an n-GaAs active layer 52 provided on the buffer layer 16 in the element formation region P2, and n ⁺ -GaAs contact layers 54 and 56 provided on the active layer 52 and spaced from each other. , The current constriction 58 provided in the active layer 52 in the region between the contact layers 54 and 56.
And ohmic electrodes 60 and 62 provided on the contact layers 54 and 56. The current constriction portion 58 is an insulating layer such as an oxygen ion implantation layer.

Next, paying attention to the hole injection source 50 among the electric circuit elements included in the integrated circuit of this embodiment, the hole injection source 50 will be described.
The manufacturing process will be briefly described. FIG. 12 is a cross-sectional view of essential parts showing the manufacturing process of the hole injection source 50 in stages.

In manufacturing the hole injection source 50, the undoped GaAs buffer layer 1 is sequentially formed on the substrate 10.
6, the n-GaAs layer 18 and the n ⁺ -GaAs layer 19 are laminated, and then the element isolation portion 28 is formed to replace the n-GaAs layer 18 and the n ⁺ -GaAs layer 19 in the element formation region P2 with another layer. It is electrically isolated from the electric circuit element (see FIG. 12).
(A). The n-GaAs layer 18 in the element isolation region P2 becomes the active layer 52.

After that, n ⁺ -GaA in the element formation region P2
Oxygen ions are implanted into regions of the s layer 19 and the active layer 52 corresponding to the current constriction portion 58 (FIG. 12B), and the hole injection source 50 is completed. By this oxygen ion implantation, the n ⁺ -GaAs layer 19 in the element forming region P2 is divided into two electrically isolated portions, which are used as contact layers 54 and 56, respectively. Further, an insulating layer serving as a current constriction portion 58 is formed in the active layer 52 by oxygen ion implantation, and the current path of the active layer 52 is constricted.

Next, the current of the hole injection source 50 of this embodiment −
The voltage characteristics will be described. FIG. 13 is a diagram conceptually showing the current-voltage characteristics of the hole injection source 50 of the third embodiment, and the vertical axis and the horizontal axis of the figure respectively show ohmic electrodes 60, 62.
It represents the current and voltage between. In the figure, the current-voltage characteristic curves of the hole injection source 50 and the comparison element for comparison therewith are indicated by reference numerals E ₀ and E ₁ , respectively. The comparative element is an element having the same configuration as the hole injection source 50 except that the current constriction portion 58 is not provided in the active layer 52.

The current-voltage characteristics of the hole injection source 50 of this embodiment are expected to show the same tendency as that of the hole injection source 14 of FIG. 1, and as shown in FIG. The current between the ohmic electrodes increases as the voltage across the ohmic electrodes increases from 0 V, and eventually becomes almost constant. When the voltage between the ohmic electrodes further increases, impact ionization occurs, which causes the current between the ohmic electrodes to increase again.

On the other hand, in the case of the comparison element, the hole injection source 5
At a voltage at which impact ionization occurs at 0, impact ionization does not occur. Therefore, it is expected that holes can be injected into the substrate 10 at a lower voltage by providing the current constriction portion 58 and constricting the current path of the active layer 52. To be done.

FIG. 14 is a sectional view schematically showing the structure of the main part of the fourth embodiment of the present invention. The components corresponding to those of the first embodiment are designated by the same reference numerals, and detailed description of the same points as those of the first embodiment will be omitted.

The integrated circuit of this embodiment has a hole injection source 64.
And has the same configuration as that of the first embodiment except that the configuration of the hole injection source 64 is different.

The hole injection source 64 is a Schottky junction type diode, and is the buffer layer 16 in the element forming region P2.
N-GaAs semiconductor layer 66 provided above and semiconductor layer 66
Schottky electrode (anode electrode) provided on one side
68 and n ⁺ − sequentially provided on the other side of the semiconductor layer 66.
It comprises a GaAs contact layer 70 and an ohmic electrode (cathode electrode) 72.

When holes are generated by the hole injection source 64, the Schottky electrode 68 is grounded or a negative potential is applied to the Schottky electrode 68 and the ohmic electrode 72 is used.
By applying a positive potential (a reverse bias voltage is applied between these electrodes 68 and 72) to the semiconductor layer 66, impact ionization is generated in the semiconductor layer 66.

Next, paying attention to the hole injection source 64 among the electric circuit elements provided in the integrated circuit of this embodiment, the hole injection source 64 will be described.
The manufacturing process will be briefly described. FIG. 15 is a cross-sectional view of essential parts showing the manufacturing process of the hole injection source 64 in stages.

In manufacturing the hole injection source 64, the undoped GaAs layer 16 and n-G are sequentially formed on the substrate 10.
The aAs layer 18 and the n ⁺ -GaAs layer 19 are laminated, and thereafter, the element isolation portion 28 is formed and n-G of the element formation region P2 is formed.
The aAs layer 18 and the n ⁺ -GaAs layer 19 are electrically isolated from other electric circuit elements (FIG. 15A). The n-GaAs layer 18 in the element formation region P2 becomes the semiconductor layer 66.

After that, n ⁺ -GaA in the element formation region P2
The other side of the s layer 19 is removed by etching to remove the semiconductor layer 6
The other side of 6 is exposed and n of the element formation region P2 is exposed.
One side of the ⁺ -GaAs layer 19 is left as the contact layer 70 (FIG. 15B).

After that, an ohmic electrode 72 is formed on the contact layer 70, and then a Schottky electrode 68 is formed on the other side of the semiconductor layer 66 (FIG. 15C) to complete the hole injection source 64. To do.

The hole injection source 64 may be a Schottky junction type diode having any suitable structure other than that described here.

FIG. 16 is a sectional view schematically showing the structure of the main part of the fifth embodiment of the present invention. The components corresponding to those of the first embodiment are designated by the same reference numerals, and detailed description of the same points as those of the first embodiment will be omitted.

The integrated circuit of this embodiment has a hole injection source 74.
And has the same configuration as that of the first embodiment except that the configuration of the hole injection source 74 is different.

The hole injection source 74 is a pn junction type diode, and is provided on the buffer layer 16 in the element formation region P2 and forms a pn junction, and a p-GaAs semiconductor layer 76 and an n-GaAs semiconductor layer 78, A p ⁺ -GaAs contact layer 80 and an ohmic electrode (anode electrode) 82 sequentially provided on the semiconductor layer 76, and an n ⁺ -GaAs contact layer 84 and an ohmic electrode (cathode electrode) 86 sequentially provided on the semiconductor layer 78. Be prepared.

Next, focusing on the hole injection source 74 included in the integrated circuit of this embodiment, the manufacturing process of the hole injection source 74 will be schematically described. FIG. 17 is a cross-sectional view of an essential part schematically showing the manufacturing process of the hole injection source 74.

In manufacturing the hole injection source 74, the undoped GaAs layer 16 and the n-G layer are sequentially formed on the substrate 10.
The aAs layer 18 and the n ⁺ -GaAs layer 19 are laminated, and then, oxygen ions are implanted into the formation region of the element isolation portion 28 to form the element isolation portion 28, and the p-type semiconductor is exposed in the element formation region P2. Oxygen ions are implanted into the region P2 _P to form the oxygen ion implanted layer 88 (FIG. 17A). At this time, oxygen ions are implanted to a depth h1 reaching the undoped GaAs buffer layer 16 or the substrate 10. Oxygen ions are not implanted into the n-type semiconductor exposed region P2 _N in the element formation region P2. n ⁺ -GaAs in exposed p-type semiconductor region P2 _P
The layer 19 portion and the n-GaAs layer 18 portion become the contact layer 84 and the n-type semiconductor layer 78.

After that, p-type impurity ions for forming the p-type semiconductor layer 76 are implanted into the p-type semiconductor exposed region P2 _P. At this time, p-type impurity ions are added to the n-GaAs layer 1
Implantation is performed to a depth h2 deeper than the depth of 8 and shallower than the depth of the oxygen ion implantation layer 88 (FIG. 17B). No p-type impurity ions are implanted into the n-type semiconductor exposed region P2 _N. The p-type impurity ion implantation region is indicated by reference numeral 90.

[0083] Thereafter, a p-type impurity ions implanted into the p-type semiconductor exposure region P2 _P to activate by performing annealing treatment to form the p-type semiconductor layer 76 to the p-type semiconductor exposure region P2 _P (FIG. 17 (C) ).

After that, the p ⁺ -GaAs contact layer 80 is formed.
And the ohmic electrode 82 to the p-type semiconductor exposed region P2 _P.
On the exposed surface of the p-type semiconductor layer 76, and then an ohmic electrode 86 is formed on the exposed surface of the contact layer 84 in the n-type semiconductor exposed region P2 _N to complete the hole injection source 74. .

The hole injection source 74 may be a pn-junction type diode of any suitable configuration other than the one described here. In the example described above, the n-type semiconductor layer 78 and the p-type semiconductor layer 76 are formed by implanting the p-type impurity ions into the p-type semiconductor exposed region P2 _P so as not to implant them into the n-type semiconductor exposed region P2 _N. Alternatively, for example, p-type impurity ions may be implanted over the entire surface of the element formation region P2 to form the n-type semiconductor layer 78 and the p-type semiconductor layer 76. In this case, n ⁺ of the n-type semiconductor exposed region P2 _N
The dose amount of the p-type impurity ions is adjusted so that the -GaAs layer 19 and the n-GaAs layer 18 are maintained as an n-type semiconductor. And the layer 1 in the portion of the n-type semiconductor exposed region P2 _N
The n-type semiconductor layer 78 may be formed from Nos. 8 and 19, and the contact layer 84 and the ohmic electrode 86 may be sequentially formed on the semiconductor layer 78.

The present invention is not limited to the above-mentioned embodiments, and therefore, the shape of each component, the arrangement position,
The forming material, the conductivity type, the method of applying a voltage, the manufacturing method, the numerical conditions, and others can be arbitrarily changed.

[0087]

As is apparent from the above description, according to the integrated circuit of the present invention, since the hole injection source is provided,
When an electron is trapped in a deep level in a semi-insulating compound semiconductor substrate, holes are injected into the substrate through a hole injection source to recombine with the trapped electron in the deep level. The trapped electrons can be extinguished. Moreover, circuit FET
Since the hole injection source is provided in the vicinity, trapped electrons in the region near the circuit FET can be eliminated.

Therefore, when the circuit FET is an n-channel FET, it is possible to prevent the drain current of the circuit FET from decreasing due to the back gate effect or the side gate effect. Further, it is possible to prevent the gain from greatly decreasing when the frequency of the electric signal applied to the gate electrode of the circuit FET is increased.

It is also possible to keep the potential of the substrate constant near the circuit FET by controlling the injection amount of holes arbitrarily and suitably.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a main part schematically showing the configuration of a first embodiment of the present invention.

FIG. 2 is a main part plan view schematically showing a configuration of a first embodiment of the present invention.

3 (A) to 3 (C) are cross-sectional views of relevant parts showing stepwise a manufacturing process of a circuit FET and a hole injection source.

4 (A) to 4 (B) are cross-sectional views of relevant parts showing stepwise a manufacturing process of a circuit FET and a hole injection source.

FIG. 5 is a main-portion cross-sectional view schematically showing the configuration of the experimental device.

FIG. 6 is a diagram schematically showing an experimental result regarding a back gate effect.

FIG. 7 is a diagram schematically showing an experimental result regarding a current-voltage characteristic of a hole injection source.

FIG. 8 is a diagram schematically showing an experimental result regarding a side gate effect.

9 (A) to 9 (B) are diagrams showing experimental results regarding gain variation.

FIG. 10 is a cross-sectional view of main parts schematically showing the configuration of a second embodiment of the present invention.

FIG. 11 is a cross-sectional view of main parts schematically showing the configuration of a third embodiment of the present invention.

FIGS. 12A to 12C are cross-sectional views of a main part schematically showing the manufacturing process of the hole injection source.

FIG. 13 is a diagram schematically showing an experimental result regarding a current-voltage characteristic of a hole injection source.

FIG. 14 is a cross-sectional view of main parts schematically showing the configuration of the fourth embodiment of the present invention.

15A to 15C are cross-sectional views of a main part schematically showing a manufacturing process of the hole injection source.

FIG. 16 is a cross-sectional view of main parts schematically showing the configuration of a fifth embodiment of the present invention.

17A to 17C are cross-sectional views of a main part schematically showing a manufacturing process of the hole injection source.

[Explanation of symbols]

10: Semi-insulating GaAs substrate 12: Circuit FET 14, 36, 50, 64, 74: Hole injection source 181, 182, 38, 52: Active layer 201, 202: Recess 221, 222: Gate electrode 241, 242 : Source electrode 261, 262: Drain electrode 28: Element isolation part 44, 58: Current constriction part 46, 48, 60, 62, 72, 82, 86: Ohmic electrode 66: Semiconductor layer 68: Schottky electrode 76: P-type Semiconductor layer 78: n-type semiconductor layer

Claims (5)

[Claims] 1. An F for a circuit on a semi-insulating compound semiconductor substrate.
An integrated circuit provided with an electric circuit element including ET, comprising a hole injection source provided near a circuit FET. 2. The integrated circuit according to claim 1, wherein the hole injection source is an injection FET. 3. The hole injection source comprises an active layer, one and the other ohmic electrodes spaced apart from each other on the active layer, and a current constriction portion provided in the active layer between the ohmic electrodes. The integrated circuit according to claim 1, wherein: 4. The integrated circuit according to claim 1, wherein the hole injection source is a Schottky junction type diode or a pn junction type diode. 5. The integrated circuit according to claim 1, wherein a circuit FET is provided within a range where holes are diffused from the hole injection source.