JPH0677418A - Integrated circuit device and manufacture thereof - Google Patents

Abstract

PURPOSE:To provide an integrated circuit device, mounted with high speed bipolar elements and reliable MISFET elements, and a method for the manufacture thereof. CONSTITUTION:The gate electrode 21 on MIS semiconductor elements 50 and 51 is covered with a gate insulating film 20 and Si3N4 film 24 formed by local Si3N4 deposition. The periphery of the base electrode 32 of a bipolar element, composed mainly of polycrystalline silicon, in contact with the substrate surface, is covered with the gate insulating film 20 and Si3N4 film in this order from the substrate. This shallows the emitter diffusion layer on the bipolar element, and thus achieves a larger hFE than conventional. Further, the gate insulating film on MISFETs is free from contaminations due to resist and so on involved in the emitter electrode formation. This improves the permanent breakdown voltage of gate insulating films for MISFETs on bipolar CMISFET integrated circuit devices.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fine and large-scale semiconductor integrated circuit device, and more particularly to a bipolar CMIS (Complementary Metal Insulato) suitable for high speed operation.
r Semiconductor) type integrated circuit device structure and manufacturing method.

[0002]

2. Description of the Related Art A bipolar CMIS element is used as a high speed and low power consumption integrated circuit element by taking advantage of the high speed of the bipolar element and the low power consumption of the CMIS element. However, since there are many types of elements used, there is a problem that the manufacturing process becomes complicated, and simplification of the process is a problem.

International Electron Device Meeting Proceedings 24 pages, 1987, "A High Speed Self-Aligned Bipolar CMOS Technology", Figure 2 , Figure 2).

[0004]

In the above conventional technique, the bipolar element and the MISFET (Metal Insulator Semicond) are used.
In order to form both the uctor field effect transistor (TFT) element in a short number of steps, the gate electrode of the MISFET element and the emitter electrode of the bipolar element are formed of the same polycrystalline silicon layer (FIG. 2 (a )reference). In this method, since the emitter electrode must be in contact with the substrate, it is necessary to remove the gate insulating film in the emitter region before depositing the emitter (gate) polycrystalline silicon. Is not disclosed, but the necessity of removing the gate insulating film can be easily inferred).

This conventional structure and manufacturing method (FIG. 2A)
In (1) to (c)), (1) a gate insulating film removing step using a resist pattern is required on the gate insulating film which is required to have extremely high quality, and therefore the quality of the gate insulating film is deteriorated due to the step. (2) Since many steps are performed after depositing the arsenic-doped polycrystalline silicon 61 for emitter, there is a problem that the total heat treatment time increases and the junction depth of the emitter diffusion layer becomes deep. The problem is to solve these problems.

[0006]

FIG. 1 shows an example of a structure for solving the above problems. This structure is characterized in that the emitter electrode of the bipolar element is formed of a polycrystalline silicon layer different from the gate electrode of the MISFET.

[0007]

In this structure, since it is not necessary to partially remove the gate insulating film using the resist on the gate insulating film, the quality of the gate insulating film can be maintained at a high level, and the polycrystalline silicon layer for the emitter electrode can be wired. Since it is formed immediately before the forming step, the impurity diffusion from the emitter electrode can be controlled shallowly.

[0008]

Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 1 shows a first embodiment of the present invention, which is a CMISFET (Complementaly Metal Insulator).
FIG. 3 is a cross-sectional structure diagram of an integrated circuit in which a semiconductor field effect transistor (SOI) element and a bipolar element are integrated.
An example of a trial production process of this embodiment is shown in FIGS. The features of the structure of this embodiment will be disclosed in FIGS. 3 to 12 by following the steps.

In making the prototype of the bipolar CMIS,
This was performed using the p-type Si substrate 11 shown in FIG. First, on the substrate, a p-type impurity region 12 having a concentration of 1 × 10 ¹⁸ cm ⁻³ for the n-channel MISFET region and the element isolation region of the bipolar element, and 1 × 10 ²⁰ for the p-channel MISFET region and the bipolar element region are formed. A cm ⁻³ n-type impurity region 13 is formed.

Next, a silicon layer 14 having a thickness of 2 μm is epitaxially grown (FIG. 4), and on its surface, a concentration of 0.5 × 10 ¹⁷ cm ⁻³ is used for the n-channel MISFET region and the element isolation region of the bipolar element. p-type impurity region 15
To form an n-type impurity region 16 of 1 × 10 ¹⁷ cm ⁻³ for the p-channel MISFET region and the bipolar element region (FIG. 5).

A field oxide film 17 having a thickness of 400 nm is formed in the element isolation region on the surface of the substrate by the selective oxidation method. In the p-type impurity region 15 where the segregation phenomenon becomes a problem, the boron concentration immediately below the field decreases, so that the singly charged ions of boron are 1 × 10 at 200 keV immediately after the field formation.
Ion implantation was performed at ¹³ cm ^-2 to increase the boron concentration. In order to increase the boron concentration in this portion, a conventional method of forming a boron layer having a sufficient concentration on the surface of the element isolation region immediately before the selective oxidation is also possible (FIG. 6).

After forming the element isolation region, the p-type impurity layer 19 for the base region is formed by the ion implantation method so that the peak impurity concentration becomes 1 × 10 ¹⁸ cm ⁻³ . After forming the base region, a gate insulating film 20 having a thickness of 15 nm was formed by a thermal oxidation method. (FIG. 7) After forming a polycrystalline silicon layer containing n-type impurities to a thickness of 150 nm on the gate insulating film by chemical vapor deposition,
Using the resist pattern formed by the known photolithography as a mask, the polycrystalline silicon electrode 21 is formed by the known dry etching technique. At this time, polycrystalline silicon having the emitter electrode size is also formed on the emitter electrode formation region of the bipolar element (FIG. 8).

In this embodiment, polycrystalline silicon containing n-type impurities was used as an electrode material. However, no impurities were added at the time of chemical vapor deposition, and an ion implantation method or the like after depositing a polycrystalline silicon layer. Therefore, n-type or p-type impurities may be added to the polycrystalline silicon on the n-channel region and the p-channel region. Also, tungsten on polycrystalline silicon,
It is also possible to reduce the resistance of the electrode by laminating one or more layers of molybdenum, titanium, or a silicide of these refractory metals.

After forming the polycrystalline silicon electrode, the source and drain diffusion layers 22 and 23 of the MISFET element are formed by using this electrode as a mask.

Next, a Si ₃ N ₄ film 24 having a thickness of 50 nm is selectively formed on the surface of the polycrystalline silicon electrode. For the formation, a chemical vapor deposition method using a gas atmosphere in which a ratio of NH ₃ gas to SiH ₂ Cl ₂ gas 1 was added was used. The pressure during film formation is 60 Pa and the temperature is 750 ° C. Si ₃ N ₄ film 2
No. 4, the selective chemical vapor deposition method uses Si ₃ N _{4 on the} SiO ₂ surface.
Since film growth is very slow and film growth occurs on silicon, various refractory metal silicides, and various refractory metal surfaces, even if a refractory metal or its silicide is laminated on the polycrystalline silicon surface There is no problem (Fig. 9).

After the Si ₃ N ₄ film 24 is formed, the gate insulating film exposed on the surface of the substrate is removed, polycrystalline silicon is deposited by chemical vapor deposition to a thickness of 150 nm, and patterned to form electrodes 26, 27 is formed. n-channel MIS
In the FET region, 1 × 10 ¹³ cm ^-2 phosphorus monovalent ions are implanted into the polycrystalline silicon at an energy of 80 keV, and in the p-channel type MISFET region and the bipolar element region, the monovalent boron is added to the polycrystalline silicon. Ions are implanted at 1 × 10 ¹³ cm ^-2 with an energy of 20 keV to form a polycrystalline silicon electrode 26 containing an n-type impurity and a polycrystalline silicon electrode 27 containing a p-type impurity.

After forming the polycrystalline silicon electrodes 26 and 27, the surface of the polycrystalline silicon electrodes is oxidized by a thermal oxidation method to form SiO ₂ 25 having a thickness of 100 nm.

Next, as shown in FIG. 10, a resist pattern 30 that opens at least the emitter region is formed, and the Si ₃ N ₄ film on the surface of the polycrystalline silicon electrode 21 of the emitter region is etched by the dry etching method to form the emitter forming portion. The hole 31 is formed. In this etching, S on the substrate surface
A high selective anisotropic etching technique using CH ₂ F ₂ gas was used to reduce the abrasion of the iO ₂ film.

Subsequently, the polycrystalline silicon electrode 21 on the emitter region is removed by using the isotropic Si etching technique, and the portion of the gate insulating film 20 immediately below the electrode is etched (FIG. 11).

Next, a base polycrystalline silicon electrode 32 containing 1 × 10 ²⁰ cm ^{-3 of} arsenic is deposited by chemical vapor deposition,
It is formed by patterning using a known photolithography technique and dry etching technique. After patterning,
Annealing was performed at 900 ° C. for 10 minutes to form an n-type impurity layer for base (FIG. 12).

After that, an insulating film was formed on the substrate, contact holes were formed, and wiring was formed to form the structure shown in FIG.

In the bipolar element formed in this embodiment, the emitter diffusion layer can be made shallower than that of the bipolar element formed by the conventional method, so that the hFE which is about twice that of the conventional one is realized. Further, in this embodiment, the gate insulating film of the MISFET is not exposed to the contamination of the resist and the like, so that the MISFET formed by the conventional method has an average of about 8 MV / c.
The breakdown voltage of the permanent insulation film was 10 MV / cm
Improved above.

(Embodiment 2) In the embodiment shown in FIG.
A structure is used in which a polycrystalline silicon electrode is stacked on the source and drain in order to reduce the junction depth of the source and drain diffusion layers of ET. By the way, when the gate length of the MISFET element exceeds about 0.5 μm, the junction depth of the source and drain may be about 0.1 to 0.2 μm. In this case, the source and drain diffusion layers formed by ion implantation can be used. The embodiment of FIG. 13 shows an embodiment in which the source and drain diffusion layers 34 and 35 are formed by an ion implantation method.

(Embodiment 3) In FIG. 9, the SiO ₂ layer 25 is formed on the surface of polycrystalline silicon by the thermal oxidation method. However, the electrical breakdown voltage of the SiO ₂ layer formed by oxidizing polycrystalline silicon is only about 10V. I can't get it. In order to realize a higher breakdown voltage, a film formed by chemical vapor deposition is superior to a film formed by oxidizing polycrystalline silicon when the thickness is the same. An example using a SiO ₂ film by this chemical vapor deposition method is shown in FIGS.

In this embodiment, a polycrystalline silicon film having a 100 nm-thick chemical vapor deposition SiO ₂ film is used as an electrode (FIG. 14A). After patterning the electrode, the SiO ₂ film having a thickness of 100nm was formed by a chemical vapor deposition method, covered with SiO ₂ film 22 of the anisotropically SiO ₂ film 100nm etched thickness of about 100nm polycrystalline electrode surrounding .

[0027]

In the bipolar element shown in the present invention, the emitter diffusion layer can be made shallower than that of the bipolar element formed by the conventional method, so that the hFE which is about twice that of the conventional one is realized.
Further, in the present invention, since the gate insulating film of the MISFET is not exposed to the contamination of the resist and the like, the breakdown voltage of the permanent insulating film is 10 MV / cm or more, which is about 8 MV / cm on average in the MISFET formed by the conventional method. Improved.

[Brief description of drawings]

FIG. 1 is a cross-sectional structure diagram of a bipolar CMIS integrated circuit device.

FIG. 2 is a conventional bipolar CMIS formation process.

FIG. 3 is a cross-sectional view showing a bipolar CMIS forming step.

FIG. 4 is a cross-sectional view showing a bipolar CMIS forming step.

FIG. 5 is a cross-sectional view showing a bipolar CMIS forming step.

FIG. 6 is a cross-sectional view showing a bipolar CMIS forming step.

FIG. 7 is a cross-sectional view showing a bipolar CMIS forming step.

FIG. 8 is a cross-sectional view showing a bipolar CMIS forming step.

FIG. 9 is a cross-sectional view showing a bipolar CMIS forming step.

FIG. 10 is a cross-sectional view showing a bipolar CMIS forming step.

FIG. 11 is a cross-sectional view showing a bipolar CMIS forming step.

FIG. 12 is a cross-sectional view showing a bipolar CMIS forming step.

FIG. 13 is a cross-sectional structural diagram of a bipolar CMIS integrated circuit element having no polycrystalline silicon electrode on the source / drain.

FIG. 14 is a cross-sectional view showing a step of forming a polycrystalline silicon electrode.

[Explanation of symbols]

11 ... p-type silicon substrate, 12 ... p-type impurity layer, 13 ...
n-type impurity layer, 14 ... Silicon epitaxial layer, 15
... p-type impurity layer, 16 ... n-type impurity layer, 17 ... field oxide film, 18 ... oxide film, 19 ... base region (p-type impurity layer), 20 ... gate insulating film, 21 ... polycrystalline silicon electrode, 22 ... n-type impurity layer, 23 ... p-type impurity layer, 24 ...
Selective Si ₃ N ₄ film, 25 ... SiO ₂ , 26 ... Polycrystalline silicon electrode (containing n-type impurities), 27 ... Polycrystalline silicon electrode (containing p-type impurities), 28 ... N-type impurity layer, 29 ... P-type impurities Layer, 30 ... Resist, 31 ... Emitter forming hole,
32 ... Polycrystalline silicon electrode for base, 33 ... n for base
-Type impurity layer, 34 ... N-type impurity layer, 35 ... P-type impurity layer, 41 ... SiO ₂ film, 42 ... SiO ₂ sidewall,
43 ... Source electrodes for n-channel MISFET, 44 ... N
Drain electrode for channel MISFET, 45 ... Source electrode for p-channel MISFET, 46 ... P-channel MIS
FET drain electrode, 47 ... Base electrode, 48 ... Emitter electrode, 49 ... Collector electrode, 50 ... N-channel MI
SFET, 51 ... P-channel MISFET, 52 ... Bipolar transistor.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Jun Sugiura 2326 Imai, Ome City, Tokyo Inside the Device Development Center, Hitachi, Ltd. (72) Inventor Atsushi Koike 5-20-1 Mizumizuhonmachi, Kodaira-shi, Tokyo Ceremony Company Hitachi, Ltd., Semiconductor Design and Development Center (72) Inventor Eiji Takeda 1-280, Higashi Koigokubo, Kokubunji, Tokyo Metropolitan Research Center, Hitachi Ltd.

Claims (6)

[Claims] 1. A MISFET (Metal Insulator Semicond)
UCtor field effect transistor) and a vertical bipolar element are integrated, the gate electrode of the MIS type semiconductor element is covered with a gate insulating film and a Si ₃ N ₄ film, and the main material is polycrystalline silicon. An integrated circuit device in which the periphery of the base electrode of the bipolar element, which contacts the surface of the substrate, is sequentially covered with the gate insulating film and the Si ₃ N ₄ film from the substrate side. 2. The integrated circuit device according to claim 1, wherein a polycrystalline silicon electrode is laminated on the source diffusion layer and the drain diffusion layer of the MISFET element and on the base diffusion layer of the bipolar element. 3. A step of forming a first high-concentration p-type impurity region, a second high-concentration p-type impurity region, and a high-concentration n-type impurity region on a p-type semiconductor substrate, and an epitaxial process on the semiconductor substrate. A step of forming a layer, and a first p-type impurity region on the first high-concentration p-type impurity region, the second high-concentration p-type impurity region and the high-concentration n-type impurity region, respectively. Type impurity layer, a second p type impurity layer, and an n type impurity layer, a step of forming a SiO ₂ layer region for element isolation on the surface of the epitaxial layer, and the first p type A step of forming a p-type impurity region for a base on the surface of the impurity layer, a step of forming a gate insulating film on the surface of the epitaxial layer, and a step of depositing the first polycrystalline silicon and using a lithography technique and an etching technique. , N-channel MISF Step of forming a gate electrode for T, a gate electrode for p-channel MISFET, and a dummy electrode for forming an emitter of a bipolar element, and forming a source and drain n-type diffusion layer for n-channel MISFET using the gate electrode for n-channel MISFET as a mask A step of forming a p-channel MISFET source and drain n-type diffusion layer using the p-channel MISFET gate electrode as a mask, a step of forming the n-channel MISFET gate electrode, the p-channel MISFET gate electrode, and the bipolar element A step of selectively forming a Si ₃ N ₄ film on the surface of the dummy electrode for forming an emitter, a step of etching the gate insulating film exposed on the surface of the substrate, and an impurity region for the base of the bipolar element exposed on the surface of the substrate Forming a second polycrystalline silicon electrode on top , By oxidizing the polycrystalline silicon electrode surface of the second, forming a second SiO ₂ film on the surface, of the the Si ₃ N ₄ film which is exposed on the substrate surface, the emitter region of the bipolar element Anisotropically etching the upper Si ₃ N ₄ film, etching the dummy electrode for forming an emitter on the bipolar element, etching the gate insulating film directly under the dummy electrode, and And forming an emitter electrode by using a lithographic technique and an etching technique. A method for manufacturing an integrated circuit device, comprising: 4. A MISFE using the same layer as the second polycrystalline silicon electrode on the bipolar element base impurity region.
4. The method for manufacturing an integrated circuit device according to claim 3, wherein a polycrystalline silicon electrode is formed on the surface of the T source diffusion layer and the drain diffusion layer. 5. An amorphous silicon layer is used instead of some of the polycrystalline silicon layers.
Manufacturing method of integrated circuit device. 6. Laminating one or more layers of a tungsten silicide layer, a molybdenum silicide layer, a titanium silicide layer, a tungsten layer, a molybdenum layer, a titanium layer, and a titanium nitride layer on the surface of some polycrystalline silicon layers. The method for manufacturing an integrated circuit device according to claim 3, wherein