JPH0677343U - AD conversion circuit with dither circuit - Google Patents

Abstract

(57) [Abstract] [Purpose] Add dither signal to the input of AD converter A
In the D conversion circuit, by adding the dither signal to the comparison voltage side of the AD converter, the dither circuit is simplified and an AD conversion circuit with a dither circuit having improved performance is provided. [Structure] An adder is provided at a comparison voltage end applied to an AD converter. A dither signal is connected to one input terminal of the adder. The comparison voltage is connected to the other input terminal of the adder. Further, a digital signal processor is connected to the output terminal of the AD converter to perform a digital averaging process to form an AD conversion circuit with a dither circuit. As another embodiment, the adder may be provided only at one end of the plurality of comparison voltage ends applied to the AD converter. Further, as another embodiment, an adder may be provided at a voltage generating terminal common to a plurality of comparison voltages.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to an AD conversion circuit with a dither circuit, which has a dither circuit and has improved performance when it has a dither circuit like an AD conversion circuit in an optical signal processing device.

[0002]

[Prior art]

 It is generally known that a quantization bit error occurs when an analog signal is quantized. It is known that a dither signal is added as a device for reducing the quantization bit error.

The dither signal is a small signal noise that is intentionally added to prevent deterioration of the S / N ratio when performing the digital averaging process. Normally, when quantization is performed, a signal having a constant cycle that is irrelevant to the input may be output from the A / D converter. This is because noise of a specific frequency occurs within the band of the input signal, and the quantization noise level is not uniform, which causes the S / N characteristic to deteriorate. A dither signal is added to prevent the deterioration of the S / N ratio.

A block diagram showing a configuration of an AD conversion circuit having a conventional dither circuit is as shown in FIG.

The analog input signal is added to the dither signal 3 by the adder 2 before being input to the AD converter 1.

Further, the AD converter 1 is supplied with a comparison voltage 4 for supplying the maximum voltage and a comparison voltage 4 for supplying the minimum voltage as reference voltages. The output of the AD converter 1 is input to the digital signal processor 5 and averaged.

[0007]

The conventional AD conversion circuit with a dither circuit has the following drawbacks.

When the analog signal has a wide band, a wide band adder is required to add dither without degrading the S / N ratio of the analog signal. For example, an optical signal processing device needs to handle an input signal in a band of several hundred MHz. Performance is limited if a sufficiently wide band adder is not available.

Further, when the digital data is logarithmically converted, the dither signal has a relatively small influence on the signal having a high level, and the addition of the dither signal is originally unnecessary, so that a wasteful configuration is required. Will be there.

The present invention has been made in view of the problems of the above-described conventional technique, and the dither circuit is simplified by adding the dither signal to the comparison voltage side of the AD converter. The present invention also provides an AD conversion circuit with a dither circuit having improved performance.

[0011]

[Means for Solving the Problems]

 According to this invention, in the AD conversion circuit for adding the dither signal to the input of the AD converter, the adder is provided at the comparison voltage end applied to the AD converter. Connect the dither signal to one input of the adder. The comparison voltage is connected to the other input terminal of the adder. Further, a digital signal processor is connected to the output terminal of the AD converter to perform digital averaging processing, thereby forming an AD conversion circuit with a dither circuit.

Further, as another embodiment, an adder is provided only at one end of the plurality of comparison voltage ends applied to the AD converter. A dither signal is connected to one input terminal of the adder. Connect the comparison voltage to the other input of the adder. The AD conversion circuit with a dither circuit may be configured in this way.

Further, as another embodiment, an adder is provided at a voltage generating terminal common to a plurality of comparison voltages applied to the AD converter. A dither signal is connected to the input terminal of the adder. Connect a common voltage to the other input of the adder. The AD conversion circuit with a dither circuit may be configured in this way.

[0014]

[Action]

 In the present invention, since the adder is provided on the comparison voltage side, the frequency band of the adder may be the frequency range through which the dither signal passes.

Generally, the frequency band of the dither signal is sufficiently narrower than that of the analog input signal. Therefore, in order to add the dither signal without degrading the S / N ratio of the wideband analog signal as in the conventional case. Since a wide band adder is not required, a simple circuit configuration is possible and the dither circuit can be simplified.

Further, since it is possible to handle a wider band analog signal with respect to the band of the adder used, the performance of the AD conversion circuit with a dither circuit can be improved.

When digital data is logarithmically converted, the dither signal is reduced and given to a high level signal, so that there is no unnecessary noise and the S / N characteristic is improved.

[0018]

【Example】

 An embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of the present invention.

FIG. 7 is an explanatory diagram of the input signal versus the output code.

As shown in FIG. 1, an adder 2 is provided at the input terminal of the reference voltage (Vmax) of the AD converter 1. The dither signal 3 is connected to one input terminal of the adder 2. The comparison voltage 4 is connected to the other input terminal of the adder 2.

The output code for the input signal is obtained as follows. First, when the dither signal is not added, the digital output code obtained when the analog input signal and the comparison voltage are given to the A / D converter is as shown in FIG.

Next, as shown in FIG. 5, in the conventional dither addition circuit, the dither signal is added to the analog input signal. Further, when the dither signal is added to the analog input signal, the digital output code obtained when the analog input signal, the dither signal and the comparison voltage are given to the A / D converter is shown in (b) of FIG. It will be as shown.

Next, as shown in FIG. 6, in the present invention, the dither signal is added to the maximum voltage end of the comparison voltage. When the dither signal is added to the reference voltage, the digital output code obtained when the analog input signal, the comparison voltage and the dither signal are given to the A / D converter is shown in (c) of FIG. As shown.

That is, when the dither signal is added to the comparison voltage, the comparison voltage is not constant, and as a result, the dither signal is added to the analog signal. However, since the dither is greatly affected by only one of the comparison voltages (for example, the one with a lower digital code), its noise width is proportional to the analog input voltage, and as shown in Fig. 6, the digital code is low. The larger dither signal is input to one side, and the smaller dither signal is input to the larger side of the digital code.

Thus, when logarithmic conversion is performed at full scale, if the digital code is large, the dither signal is not unnecessarily input.

Next, FIG. 3 shows a second embodiment as another embodiment.

In FIG. 3, the dither signal 3 is added not only to the Vmax reference voltage of the comparison voltage but also to the Vmin reference voltage.

As a result, in the case of FIG. 1, the dither signal is added to the lower digital code, while the dither signal is added to the Vmin reference voltage of the comparison voltage in the case of FIG. Therefore, the weighted addition is performed to the higher digital code, and eventually the dither signal is uniformly added from the lower digital code to the higher digital code.

That is, by adding dither to the entire comparison voltage, it is possible to obtain exactly the same performance as conventional dither.

Next, FIG. 4 shows a third embodiment as another embodiment.

In FIG. 3, the dither signal is added to the Vmin reference voltage together with the Vmax reference voltage of the comparison voltage, but in FIG. 4, the dither signal is directly dithered to the common voltage generator 6 of the comparison voltage. The signal 3 is added by the adder 2.

That is, by using a circuit that can generate dither and a comparison voltage at the same time by using a Zener diode or the like, the comparison voltage generation circuit and the circuit for generating the dither are shared and shared, and the configuration of the adder circuit is simplified. it can.

[0034]

[Effect of device]

 Since the present invention is configured as described above, it has the following effects.

By adding the dither signal to the comparison voltage of the AD converter, the dither circuit can be simplified and an AD conversion circuit with a dither circuit having improved performance can be provided.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of the present invention.

FIG. 2 is a block diagram showing a conventional configuration.

FIG. 3 is a block diagram showing a second embodiment.

FIG. 4 is a block diagram showing a third embodiment.

FIG. 5 is an operation explanatory diagram of a conventional dither addition circuit.

FIG. 6 is an operation explanatory diagram of a dither addition circuit in the present invention.

FIG. 7 is an explanatory diagram of input signals versus output codes.

[Explanation of symbols]

 1 AD converter 2 Adder 3 Dither signal generator 4 Comparison voltage generator 5 Digital signal processor 6 Common voltage generator

Claims (3)

[Scope of utility model registration request] 1. An AD conversion circuit for adding a dither signal to the input of the AD converter, wherein a digital signal processor (5) for performing digital averaging processing is provided at the output end of the AD converter (1), An adder (2) was provided at the comparison voltage end applied to the converter, a dither signal (3) was connected to one input end of the adder, and a comparison voltage (4) was connected to the other input end of the adder. AD converter circuit with dither circuit characterized by 2. An adder (2) is provided only at one end of a plurality of comparison voltage terminals applied to an AD converter, and a dither signal (3) is connected to one input terminal of the adder, The AD conversion circuit with a dither circuit according to claim 1, wherein a comparison voltage (4) is connected to the other input terminal. 3. An adder (2) is provided at a voltage generation terminal common to a plurality of comparison voltages applied to an AD converter, and a dither signal (3) is connected to one input terminal of the adder, The AD conversion circuit with a dither circuit according to claim 1, wherein a common voltage (6) is connected to the other input terminal.