JPH0677279A - Semiconductor device and bonding method - Google Patents

Abstract

PURPOSE:To provide a device which is lessened in area and enhanced the number of devices produced per wafer and a bonding method of enabling the device to be realized. CONSTITUTION:Dicing is carried out so as to make a dicing line 8 pass over the exposed part of a pad 2, and an inner lead 4 is directly bonded to the exposed pad 2 for the formation of a semiconductor device.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductors, and more particularly to miniaturized products and miniaturization methods.

[0002]

2. Description of the Related Art In a conventional semiconductor device, wiring from an LSI chip (hereinafter referred to as a device) is bonded to an inner lead via a bump. That is, normally, as shown in FIG. 4, after protecting the entire wafer with a passivation film, the pad 2 is exposed, and then the scribe line 7 is diced by the dicing line 8 to separate the device into individual units. The wiring is taken out from this device and bonded to the inner lead. Pre-chip bonding by bumps or tape carrier bonding (TAB) is used as a bonding method corresponding to the miniaturization of pads accompanying the high integration of devices. Figure 5
Fig. 3 shows the situation of the TAB method in which bump formation is performed on the chip. A pad 2 which is a conductor film made of Al, an Al—Cu alloy or the like is provided on the main body substrate 1, and a passivation film 3 as a protective film covers the pad 2. In order to perform this TAB method, it is necessary to expose the pad 2 and further project the conductive portion from the surrounding passivation film 3. Therefore, the bump 5 must be raised by plating with Au, Cu or the like. I won't. Or
Bumps on the inner lead side, as typified by mesa-shaped bumps and transfer bumps, must be raised by plating or etching.

[0003]

However, in order to carry out this plating, many steps such as resist coating, exposure, vapor deposition and cleaning must be performed. Further, since it is impossible to form bumps that are too small, there is a problem that the size of the bumps is increased due to the existence of the bumps. The development of technology that eliminates bumps is a major challenge for device miniaturization.

On the other hand, the pads which are necessary for the probe test and which are the bases of the bumps are also an object of miniaturization, but it is necessary to bond them on top of them, so that they must be sized to some extent or more. There is a problem that prevents miniaturization. In view of the above problems, a bump-free bonding method has been developed, and the scribe line and the pad area are minimized to greatly simplify the process and provide a miniaturized product and a miniaturization method. Is the object of the present invention.

[0005]

The present invention provides an inner ring
The semiconductor device is characterized in that the pad is directly bonded to the pad, and in the dicing process of the wafer, dicing is performed so that the dicing line passes through the pad exposed surface, and the inner lead is directly bonded to the pad. This is the bonding method.

[0006]

According to the present invention, since the inner leads are directly joined to the pads by dicing so as to pass through the pad exposed surface, the pad area can be made very small.

[0007]

EXAMPLES Examples of the present invention will be described below.
As shown in FIG. 1, the dicing is shifted from the scribe line 7 so that the dicing line 8 passes through the exposed surface of the pad 2. In this way, the pad 2 is also exposed on the cross section of the wafer. Even with this method, the size of the device is reduced as much as the pad is cut, and the device can be miniaturized.

Alternatively, as shown in FIG. 2, the width of the scribe line 7 may be reduced, or the blade of the cutter may be thickened so that the scribe line 8 is located outside the dicing line 7. By combining the above methods, the pad is arranged at the portion currently used as the scribe line and the pad 2 is exposed by the current dicing.

The pads are usually made of a conductive vapor-deposited film of Al or the like. Conventionally, dicing this may cause Al particles to scatter and short circuit.
Although not considered, the reliability of the passivation film has recently been improved, and it is not necessary to consider a problem such as a short circuit even if conductive particles such as Al scatter.

In this way, the size of the device is reduced,
Alternatively, by further thinning the dicing line, the number of devices per wafer can be increased and productivity can be improved. The surface of the pad of the device obtained by the above method is exposed. Inner leads 4 are placed on this and fused as shown in FIG. The pad 2 of the device obtained by the above method has conductive pads exposed not only on the surface but also on the cross section. As shown in FIG. 3B, the inner leads 4 are arranged so as to hit the corners of the pad, and the inner leads 4 are fused by ultrasonic waves or heat treatment. The joining method is not limited to the fusion bonding described here, and may be any method that allows conduction.

In this way, the pad 2 of the device can be directly bonded to the inner lead 4, and the step of bumping can be omitted. Furthermore, it becomes possible to manufacture scribeless wafers,
The number of shots per wafer can be increased. Further, it becomes possible to make the required area of the pad for bonding extremely small, and the pad can be miniaturized to the absolutely required area of probing.

[0012]

According to the present invention, the step of forming bumps can be omitted, the area of the device or scribe line can be remarkably reduced, and the number of devices per wafer can be increased, so that the productivity of semiconductor manufacturing is remarkably increased. As the device area is improved and the device area is reduced, the effect on the high integration and miniaturization of LSI is extremely large.

[Brief description of drawings]

FIG. 1 is an explanatory view showing an embodiment of dicing according to the present invention.

FIG. 2 is an explanatory view showing an embodiment of dicing according to the present invention.

FIG. 3 is an explanatory view showing a bonding state of a pad and an inner lead according to the present invention.

FIG. 4 is an explanatory diagram showing a dicing situation by a conventional method.

FIG. 5 is an explanatory view showing a bonding state of a pad and an inner lead by a conventional method.

[Explanation of symbols]

 1 substrate 2 pad 3 passivation film 4 inner lead 5 bump 6 film 7 scribe line 8 dicing line

Claims (2)

[Claims] 1. A semiconductor device in which an inner lead is directly bonded to a pad. 2. A bonding method characterized by dicing so that a dicing line passes through an exposed surface of a pad in a wafer dicing step and directly bonding an inner lead to the pad.