JPH0677266B2 - Microcomputer operation mode control circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an operation mode control circuit of a microcomputer for extending the function of the microcomputer to the outside of an LSI chip and a method of using the same.

Configuration of Conventional Example and Its Problems In recent years, single-chip microcomputers have diversified usage patterns with the expansion of their application fields. When used as a single unit, externally, ROM (read only memory) or RAM ( Peripheral chips such as random access memory) may be used by extension connection. Therefore, the single-chip microcomputer has an operation mode according to its usage pattern, and by inputting the operation mode from the terminal, the same chip is compatible with a plurality of usage patterns.

Conventionally, there are two types of operation mode control circuits. 1
One is to provide a terminal dedicated to the operation mode input and input the operation mode by directly pulling down or pulling up the terminal. The other is to input a synchronization signal from the outside without providing a dedicated terminal. By doing so, the operation mode is normally input from the terminal functioning as an input-only terminal. Each will be described below with reference to the drawings.

FIG. 1 is a block diagram of an operation mode control circuit provided with terminals dedicated to operation mode input. 1, 2 are pull-up transistors, 3 and 4 are operation mode input terminals, and 5 and 6 are clock pulse 7 Flip-flops that store the signal levels of the operation mode input terminals 3 and 4 at the fall, and 8 are operation mode control decoders that decode the outputs of the flip-flops and generate control signals required for the respective operation modes. . This operation mode control circuit can select four operation modes by a combination of simple external circuits that pull up or pull down each terminal. In recent years, however, the application field of single-chip microcomputers has expanded. Accordingly, there is a demand to provide more operation modes, and for that purpose, it is necessary to increase the number of terminals dedicated to the operation mode input. However, the number of terminals of the microcomputer is severely limited in terms of cost, and the number of operation modes cannot be increased easily.

FIG. 2 is a block diagram of an operation mode control circuit for inputting an operation mode from a normal input-only terminal according to a synchronizing signal from the outside and a block diagram showing an example of an external circuit for inputting the operation mode. Input terminals 9 and 10 are RE
When the SET signal 16 remains low, the respective signal levels are sent to the data buses 14 and 15 by the drivers 12 and 13 when the IN signal 11 is active. When the RESET signal 16 changes from the high level to the low level, the flip-flops 5 and 6 latch the signal levels of the terminals 9 and 10, respectively.
The output is decoded by the operation mode control decoder to generate the control signal necessary for each operation mode. Reference numeral 17 is a multiplexer, which outputs the levels input to the input terminals 18 and 19 of the multiplexer to the input terminals 9 and 10 when the RESET signal 16 is low level, and pulls up the resistor when the RESET signal is high level. 20,21, switch 2
The level set by 2, 23 is output to the input terminals 9, 10, and when the switch 22 is closed, the input terminal 9
When is closed, the input terminal 10 becomes low level,
It goes high when the switch is opened. Ie RE
Input terminal 1 of the multiplexer when the SET signal is low level
8 and 19 signal levels are synchronized with IN signal 11 and data bus 1
When the RESET signal input to 4, 15 changes from high level to low level, the operation mode is determined by the signal levels set by the switches 22 and 23. In the case of this operation mode input circuit, it is not necessary to provide an input terminal dedicated to the operation mode input circuit, but there is a drawback in that the external circuit becomes complicated as can be seen by comparison with the case where the input terminal dedicated to the operation mode is provided.

OBJECT OF THE INVENTION The present invention solves the above-mentioned conventional problems, and makes it possible to increase the number of operating modes without increasing the number of dedicated input terminals and without a complicated external circuit.

Configuration of the Invention The operation mode control circuit of the microcomputer of the present invention is provided with the first and second terminals for indicating the operation mode, the first terminal is a bidirectional terminal for inputting and outputting a clock signal, and the second terminal is Since the input-only terminal is used, the number of operation modes can be increased from the two operation mode control terminals by a simple external circuit without increasing the number of operation mode control terminals.

Description of Embodiments One embodiment of a CMOS configuration of the present invention will be described below with reference to the drawings.

FIG. 3 is a block diagram of the present embodiment, in which 26 and 27 designate an operation mode, 29 is a P-channel MOS transistor, and 3 is a terminal.
Reference numeral 0 is an N-channel MOS transistor, and reference numerals 31, 32 and 33 are flip-flops. CP0 and CP1 are clock pulse signals that do not overlap each other. The operation of this circuit will be described below.

First, when the single-chip microcomputer is used alone, the terminal 26 is released and the terminal 27 is pulled down. When the output of the gate 28 which inverts and outputs CP0 is at a high level, the P-channel MOS transistor 29 is turned off, the N-channel MOS transistor 30 is turned on, and a low level is output to the terminal 26. When the output of the gate 28 is low level, the P-channel MOS transistor 29 is turned on and
The channel MOS transistor 30 is turned off, and a high level is output to the terminal 26. That is, the output of the gate 28 which inverts and outputs CP0 is further inverted and output to the terminal 26. Further, the clock signal CP0 is a P channel MOS
Since the signal passes through the transistor 29 and the N-channel MOS transistor 30, a signal with a time delay is output to the terminal 26. Therefore, when CP0 is in Figure 4a, flip-flop 3
The input 1 of x ₁ is as shown in FIG. 4b, and the output y _{1 of} the flip-flop 31 that latches x ₁ at the falling edge of CP0
Holds high level. Further, since the terminal 27 is pulled down, the input x ₂ of the flip-flops 32 and 33 becomes as shown in FIG. 4b, and the output y ₂ of the flip-flop 32 which latches x ₂ at the falling edge of CP0 is low. The output y ₃ of the flip-flop 33 that holds the level and latches x ₂ at the falling edge of CP 1 holds the low level. This y ₁ , y ₂ , y ₃
5 is an example of operation mode allocation according to the present embodiment.
Referring to the figure, the single-chip mode is selected, and the operation mode control decoder generates a control signal necessary for the single-chip mode. In FIG. 5, L indicates low level and H indicates high level.

ROM outside the single-chip microcomputer
When expanding, short-circuit terminals 26 and 27. Similarly, CP0 is output to the terminal 26 and CP0 is input to the terminal 27, and x ₁ and x ₂ are as shown in FIG. 4c. Therefore, (y ₁ , y ₂ , y ₃ ) = (H, H, L) and the ROM expansion mode is selected from FIG.

Similarly, when expanding the RAM to the outside, release pin 26 and
When pulling up 7 (Fig. 4d) and expanding both ROM and RAM to the outside, invert the output of pin 26 (Fig. 4e) and input to pin 27. You can select the mode to use.

Although the above four modes are chip operation modes, this embodiment has a mode for testing two chip operations.
One of them is called debug mode, which is a mode for testing whether the developed program works properly when the single-chip microcomputer is installed in an actual device, and pulls down both terminals 26 and 27. . At this time, the terminal 26 is always at the low level regardless of the CP0 to be sent, x ₁ and x ₂ are as shown in FIG. 4f, and the debug mode is selected from FIG. Similarly, the chip test mode for testing the chip itself of the single-chip microcomputer is selected by pulling down the terminal 26 and pulling up the terminal 27 (FIG. 4g).

In the above two test modes, a large amount of current flows through the P-channel MOS transistor 29 while CP0 is at the high level in order to pull down the terminal 26, but this is a mode for testing the operation of the chip, and the P-channel MOS transistor There is no problem if you select an appropriate size.

FIG. 6 shows an example of the above-mentioned operation mode input method and its external circuit. a is a single chip mode, b is a ROM expansion mode, c is a RAM expansion mode, d is a ROM / RAM expansion mode, e is a debug mode, and f is a chip test mode. Since the usage of the ROM, the usage of the RAM, the connection and the like are known, their description will be omitted.

As described above, according to the present invention, the first and second terminals for indicating the operation mode are provided, the first terminal is a bidirectional terminal for inputting and outputting a clock signal, and the second terminal is an input-only terminal. By doing so, it is possible to input six operation modes from two operation mode input terminals with a simple external circuit.
A first mode in which a terminal is opened and a second terminal is pulled down; a second mode in which a first terminal is opened and a second terminal is pulled up;
The third mode, in which the output of the first terminal is input to the second terminal, the first
By allocating the fourth mode in which the output of the terminal is inverted and input to the second terminal to the chip operation mode, low power consumption can be realized in an LSI having a CMOS structure, which is extremely advantageous in practical use.

[Brief description of drawings]

FIG. 1 is a block diagram of an operation mode control circuit of a conventional microcomputer provided with terminals dedicated to operation modes, and FIG.
FIG. 3 is a block diagram of a conventional microcomputer operation mode control circuit for inputting an operation mode from an ordinary input terminal in response to an external synchronization signal, and FIG. 3 is a microcomputer operation mode control circuit according to an embodiment of the present invention. FIG. 4 is a block diagram, FIG. 4 is the same timing diagram, FIG. 5 is a diagram showing the same operation mode, and FIG. 6 is a block diagram of an external circuit when the circuit of FIG. 3 is used. 26 …… First terminal, 27 …… Second terminal, 29 …… P-channel MO
S-transistor, 30 ... N-channel MOS transistor, 3
1,32,33 …… Flip-flop.

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Takashi Sakao 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (72) Makoto Yamatani, 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. 56) References JP-A-59-91528 (JP, A)

Claims (1)

[Claims] 1. A first and a second terminal for instructing information for determining an operation mode of a microcomputer, and 1.
Clock sources, one driver, first and second
And a third three flip-flops, wherein the driver secures a time delay necessary for holding the clock signal of the clock source to the data of the three flip-flops by the driver, and then supplies the clock signal to the first terminal. The first flip-flop latches the signal level of the first terminal when the clock signal outputs a high level and then changes to a low level, and the second flip-flop outputs the clock signal after a high level. , The signal level of the second terminal is latched when changing to low level, and the third flip-flop latches the signal level of the second terminal when changing to high level after the clock signal outputs low level. An operation mode control circuit for a microcomputer, which is controlled by the clock signal as described above.