JPH0677250B2 - Inter-processor communication prohibition method - Google Patents

Description

DETAILED DESCRIPTION [Overview] In a duplexed distributed processing system for performing inter-processor communication, flip-flop elements are provided in the highway interfaces of # 0 system and # 1 system respectively, and when switching systems, The inter-processor communication is temporarily prohibited to the slave processor by the flip-flop element, and the inter-processor communication is started after the state after the switching operation is stabilized.

[Industrial application field]

The present invention relates to a duplicated distributed processing system for performing interprocessor communication.

In the above system, there is a problem that a communication error occurs due to the disturbance of communication data that occurs at the time of system switching, and a solution to this has been strongly desired.

[Conventional technology]

Even in a distributed processing system that performs inter-processor communication, a duplex configuration may be used to improve system reliability.

[Problems to be solved by the invention]

In such a case, in communication between processors, data may be disturbed at the time of system switching unless the clocks of both systems are completely in phase.

Therefore, there is a drawback that an error may occur in inter-processor communication.

It is an object of the present invention to provide an interprocessor communication prohibition system capable of eliminating such an interprocessor communication error.

[Means for solving problems]

The present invention is, when one is active and the other is a # 0 system and # 1 system main processor of managed inactive (1 ₀ and 1 _1), the # 0 system and # 1 system main processor (1 ₀ and 1 ₁₎ and at the duplex system of interprocessor communication consisting a slave processor (4) for performing communication, the main processor (1 ₀ and 1 ₁₎ each on the side of people flip-flop (3 ₀ and 3 ₁₎ A set input (S) is provided for the control signals (A / S ₀ and A /
S ₁ ), the reset input (R) is connected to the data signals (DATA ₀ and DATA ₁ ) output from the # 0 and # 1 main processors (1 ₀ and 1 ₁ ) respectively, and The output (Q) is commonly connected to the communication inhibit signal line on the slave processor (4) side, and further the data signal (DATA ₀
And DATA ₁ ) are commonly connected to the data signal on the slave processor (4) side, and when the system is switched, the flip-flop of the system is switched by the control signal for inhibiting the communication of the system switched to the active state. After setting the loop, the flip-flop of the system is reset by the data signal indicating the start of communication of the system, and the slave processor (4) changes the state of the communication prohibition signal line during the set period of the flip-flop. Provides an interprocessor communication prohibition method characterized by invalidating the data signal.

[Action]

According to the present invention, a signal for prohibiting communication is sent from the master processor to the slave processor when the system is switched in the redundant system, and when the slave processor recognizes this, the data disturbed by the system switching is ignored and a communication error is prevented. In addition to preventing it, there is an effect that this timing can be set by software to measure the flexibility of the entire system.

〔Example〕

FIG. 1 is a diagram showing an embodiment of an interprocessor communication prohibition system according to the present invention.

FIG. 2 is an operation flowchart of FIG.

In the figure, 1 _0, 1 ₁ are each # 0 system, # 1 system main processor, 2 _0, 2 ₁ are each # 0 system, # 1 system highway interface, 3 _0, 3 ₁ are each # 0 system , # 1 system flip-flop, 4 is a slave processor, and 100 is a management processor.

The present invention will be described in detail below with reference to the drawings.

FIG. 1 shows a relationship between a network (NW) and a line trunk (L / T) of a duplexed exchange system as an embodiment of the present invention.

In the embodiment shown in FIG. 1, the main processor and the highway interface are duplicated, and the slave processors are not duplicated.

It is in the present invention, system # 0 highway interface 2 ₀
The # 0 system flip-flop 3 ₀ is provided inside, and the # 1 system highway interface 2 ₁ is provided with the # 1 system flip-flop 3 ₁ .

Now, it is assumed that the # 0 system is active and the # 1 system is inactive.

On the other hand, each of the main processors has a control signal A / S indicating whether it is in the active state or inactive state.
Give out. A represents an active state, and S represents an inactive state.

That indicates it is active when # 0 system control signal A / S ₀ out of the main processor 1 ₀ is "1", when the control signal A / S ₀ is "0" in-active It shows that it is in a state. The same applies to the control signal A / S ₁ output from the # 1 system main processor 11 ₁ .

此control signal _{A / S 0, A / S} 1 is the main processor 1 _0, active management processor 100 that manages the main processor 1 ₁ is determined based on an instruction inactive. That is,
These control signals A / S ₀ and A / S ₁ are in the relation of antinomy signals, and correspond to the system switching instruction.

The # 0 system flip-flop 3 ₀ and # 1 system flip-flop
The outputs of 3 ₁ are both “0”, and slave processor 4 and #
Interprocessor communication is performed by the 0-system data DATA ₀ # 0 system between the main processor 1 _0.

In this state, it is assumed that the systems are switched so that the # 0 system becomes inactive and the # 1 system becomes active.

When the system is switched, the control signal A / S _{0 output} from the # 0 main processor 1 ₀ changes to "0", and the control signal A / S ₁ output from the # 1 main processor 1 ₁ changes to "1" respectively. To do.

Control signal A / S ₀ goes from “1” to “0”, control signal A / S ₁ goes from “0” to
By changing to “1”, flip-flop # 1 system 3 ₁
The output of changes from "0" to "1".

The outputs of the flip-flops 3 ₀ and 3 ₁ are control signals A / S ₀ and A / S ₁
Becomes "1" only when changes from "0" to "1".

Thus the output of the flip-flop 3 ₀ control signal A / S ₀ "1"
→ It does not change even if it changes to “0”.

While the output signal of the # 1 system flip-flop 3 ₁ becomes a transmission prohibition signal changes to "1", it is transmitted to the slave processor 4.

When the slave processor 4 receives and recognizes the communication prohibition signal "1", the communication is interrupted by the software prepared in advance.

By interrupting the communication in this way, there is no possibility of causing an error even if the inter-processor communication may be disturbed by system switching.

After system switching as the此was successful, # 1 system main processor 1 ₁ sends a reset signal # 1 system flip-flop 3 ₁ via the data DATA _1.

Since # 1 system flip-flop 3 ₁ by此reset signal is reset, the return from the state "1" to state "0", the transmission prohibition signal is eliminated.

After this result, the # 1 system becomes active, and data DA is transferred between the # 1 system main processor ₁₁ and the slave processor 4.
Inter-processor communication is performed by TA ₁ .

A summary of the above description is the flowchart of FIG.

〔The invention's effect〕

As described in detail above, according to the present invention, even during the system switching of the duplex system, even if the communication between the processors is disturbed, even if the communication data is disturbed, there is no possibility that an error will occur due to this cause. This has a great effect that it can give more flexibility.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of an interprocessor communication prohibition system according to the present invention. FIG. 2 is an operation flowchart of FIG. In the figure, 1 _0, 1 ₁ are each # 0 system, # 1 system main processor, 2 _0, 2 ₁ are each # 0 system, # 1 system highway interface, 3 _0, 3 ₁ are each # 0 system , # 1 system flip-flop, 4 is a slave processor, and 100 is a management processor.

Claims (1)

[Claims] 1. A # 0 system and # 1 system main processor (1 ₀ and 1 ₁ ) in which one is active when one is active, and a main processor of the # 0 system and # 1 system ( 1 ₀ and 1 ₁₎ and the slave performs communications processor (4) in the redundant system of the interprocessor communication consisting a, the main processor (1 ₀ and 1 ₁₎ side respectively flip-flop (3 ₀ and 3 ₁₎ Is provided and its set input (S)
Are connected to the control signals (A / S ₀ and A / S ₁ ) for prohibiting communication, and the reset input (R) is output from the main processors (1 ₀ and 1 ₁ ) of # 0 system and # 1 system, respectively. Output (Q) while being connected to the data signal (DATA ₀ and DATA ₁ )
Is commonly connected to the communication inhibit signal line on the slave processor (4) side, and the data signals (DATA ₀ and DATA ₁ ) are commonly connected to the data signal on the slave processor (4) side. At the time of switching, the flip-flop of the system is set by the control signal for prohibiting the communication of the system switched to the active state, and then the flip-flop of the system is reset by the data signal indicating the communication start of the system. In the slave processor (4), the inter-processor communication prohibition method is characterized in that the data signal is invalidated during the set period of the flip-flop by the state change of the communication prohibition signal line.